TELETEXT DATA SLICER AND METHOD THEREOF

Abstract

A data decoder decoding an input signal, comprising a comparator, a converter, and a data check module. The comparator compares the input signal with a threshold level to generate first data, such that each bit of the first data is one of two possible states, and identifies an ambiguous bit of the first data in an ambiguous range. The converter coupled to the comparator converts the first data to parallel. The data check module coupled to the converter evaluates whether the first data is inaccurate according to an error checking code thereof, and changes the ambiguous bit to the other possible state, if the first data is inaccurate. The ambiguous range includes the threshold level.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a block diagram of a conventional data decoder.

FIG. 2 is a waveform diagram of sliced input signals in a noiseless transmission environment.

FIG. 3 is a waveform diagram of input signal S_in and threshold level S_th in a noisy transmission environment.

FIGS. 4 a and 4b show error correction schemes of teletext compliant with WST system.

FIG. 5 is a block diagram of an exemplary data decoder of the invention.

FIGS. 6 a, 6 b, and 6c are waveform diagrams with ambiguous data compensation, incorporating data encoder 5 in FIG. 5.

FIGS. 7 a and 7b are block diagrams of two exemplary threshold level generators incorporated in slicer 54 in FIG. 5.

FIG. 8 is a flowchart of an exemplary decoding method incorporating data decoder 5 in FIG. 5.

FIG. 9 is another block diagram of an exemplary data decoder of the invention.

FIGS. 1 a, b, and c are waveform diagrams, slicing data with multiple threshold levels, incorporating data decoder 9 in FIG. 9.

FIG. 11 is a flowchart of an exemplary decoding method incorporating data decoder 9 in FIG. 9.

FIG. 12 is yet another block diagram of an exemplary data decoder of the invention.

FIG. 13 is a flowchart of an exemplary decoding method incorporating data decoder 12 in FIG. 12.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 5 is a block diagram of an exemplary bitstream decoder of the invention, comprising SYNC separator 10, line counter 12, slicer 54, Serial to Parallel converter 56, and bitstream check and correction module 58. SYNC separator 10 is coupled to line counter 12, slicer (comparator) 54, Serial to Parallel converter 56, and subsequently to bitstream check and correction module 58.

SYNC separator 10 receives input signal S_in to separate horizontal and vertical synchronization signals HSYNC and VSYNC for output to line counter 12, enabling slicer 54 (comparator) based thereon. Input signal S_in may be a television broadcast signal carrying bitstream D, with an error checking code.

Upon enablement, slicer 54 compares input signal S_in with threshold level S_th to generate first bitstream D_s, such that each bit of first bitstream D_s is one of two possible states, and identifies an ambiguous bit of the first bitstream when input signal S_in is determined as belonging to an ambiguous range. Data D_s may be a teletext bitstream compliant with WST, encoded by an error checking code every 8 bits. The two possible states may be “logic 1” and “logic 0”. Slicer 54 slices input signal S_in according to the frequency of clock_run_in, and determines data bit as “logic 1” if input signal S_in exceeds threshold level S_th, and “logic 1” if input signal S_in is less than threshold level S_th. The ambiguous range includes threshold level S_th, and may be a signal range plus or minus threshold level S_th. Slicer 54 detects data bit of bitstream D_s falling into the ambiguous range to identify the ambiguous bit, and generates 8-bits ambiguous bitstream D_AS accordingly. For example, if a second bit of 8-bits bitstream Ds is ambiguous, slicer 54 generates ambiguous bitstream D_AS ‘0100 0000’.

Serial to Parallel converter 56 stores 8-bits serial bitstream D_s and ambiguous bitstream D_AS in a buffer thereof, converts both into parallel bitstream D_p and D_AP, and passes both to data check and correction module 58 (data check module). Because teletext employs two ECC schemes based on the packet number and the data byte, Serial to Parallel converter 56 also delivers packet number C_P and number of data byte C_B to data check and correction module 58. In WST system, a scan line comprises 42 bytes excluding clock-run-in part and framing code, and the first two in the 42 bytes include magazine and packet number information. Thus Serial to Parallel converter 56 generates packet number C_P according to the first two bytes of a scan line, and comprises a data byte counter calculating number of data bytes C_B for each packet.

FIGS. 4 a and 4b show error correction schemes of teletext compliant with WST system. FIG. 4a illustrates ECC data format for packet number 0, and the first 10 bytes use Hamming 8/4 ECC, byte 10-41 use odd parity. FIG. 4b is ECC data format for packet number 1˜25, wherein the first 2 bytes use Hamming 8/4 ECC, and bytes 2-41 use odd parity.

Referring back to FIG. 5, data check and correction module 58 evaluates ECC of data D_p to determine accuracy, inverts the ambiguous bit to the other possible state to generate inverted bitstream, if the ECC evaluation indicates bitstream D_p is erroneous, and outputs bitstream D_p as output bitstream D_out otherwise. Data check and correction module 58 then performs another ECC check on the inverted bitstream, outputs the bitstream D_p if the inverted bitstream is erroneous, and outputs the inverted bitstream otherwise. Data check and correction module 58 performs odd parity or Hamming 8/4 check based on packet number C_P and number of bitstream byte C_B, as indicated in FIGS. 4a and 4b.

Threshold level S_th may be fixed or adaptive according to amplitude of input signal S_in. FIGS. 7a and 7b are block diagrams of two exemplary threshold level generators incorporated in slicer 54 in FIG. 5. The threshold level generator in FIG. 7a comprises gate 540a and average amplitude generator 542a. Gate 540a detects and outputs amplitude of clock_run_in part in input signal S_in to average amplitude generator 542a, thereby averaging the amplitude to generate threshold level S_th. The threshold level generator in FIG. 7b comprises gate 540b, MAX amplitude detector 542b, MIN amplitude detector 544b, and average amplitude generator 546b. Gate 540b detects and outputs amplitude of clock_run_in to MAX amplitude detector 542b and MIN amplitude detector 544b, determining and outputting the maximum and minimum amplitudes to average amplitude generator 546b, thereby averaging the maximum and minimum amplitudes to generate threshold level S_th.

FIG. 6 a is a waveform diagram with ambiguous bitstream compensation, incorporating bitstream encoder 5 in FIG. 5, odd parity ECC, and fixed threshold level S_th. Ambiguous range R_amb is a fixed range with respect to threshold level S_th, and comprises upper limit S_H and lower limit S_L. If input signal S_in is less than upper limit S_H or exceeds lower limit S_L, slicer 54 determines input signal S_in is in ambiguous range R_amb, and generates a “logic 1” indicating the ambiguous bit in ambiguous bitstream D_AS. If input signal S_in is outside ambiguous range R_amb, slicer 54 generates a “logic 0” in ambiguous bitstream D_AS. In FIG. 6a, the third bit of bitstream Ds falls into ambiguous range R_amb, and slicer 54 generates bitstream Ds ‘1010 1100’ and ambiguous bitstream D_AS ‘0010 0000’ to Serial to Parallel converter 56, both converted to parallel bitstream D_p and D_AP accordingly. The parity check in data check and correction module 58 indicates bitstream Dp is erroneous, thus bitstream Dp is XORed with bitstream D_AP to provide inverted bitstream D_SC ‘1000 1100’, errorless by another parity check according thereto. Thus bitstream slicer 5 outputs inverted bitstream D_SC as output bitstream D_out.

FIG. 6 b shows a waveform diagram with ambiguous bitstream compensation, incorporating the bitstream encoder in FIG. 5, Hamming 8/4 ECC, and fixed threshold level S_th. Slicer 54 generates bitstream Ds ‘1000 0010’ and D_AP ‘0001 0000’, converted to parallel bitstream D_p and D_AP in Serial to Parallel converter 56. Data check and correction module 58 determines bitstream D_p after Hamming 8/4 evaluation, such that XORing bitstream D_p with bitstream D_AP provides inverted bitstream D_SC ‘1001 0010’, errorless according to another Hamming 8/4 evaluation. Data slicer 5 outputs inverted bitstream D_SC as output bitstream D_out.

FIG. 6 c is a waveform diagram with ambiguous bitstream compensation, incorporating bitstream encoder 5 in FIG. 5, odd parity ECC, and adaptive threshold level S_th. Threshold level S_th is adaptive according to bitstream part of input signal S_in, and ambiguous range Ramb is fixed with respect to adaptive threshold level S_th.

FIG. 8 is a flowchart of an exemplary decoding method incorporating bitstream slicer 5 in FIG. 5. In step S800, slicer 54 determines slicing frequency and threshold level S_th according to clock_run_in during initialization. Next in step S802, slicer 54 compares input signal S_in with threshold level S_th to generate bitstream Ds, each bit of bitstream D_s being one of two possible states, and identifying ambiguous bitstream D_AP when input signal S_in is determined as belonging to the ambiguous range. After converting to parallel bitstream D_p and ambiguous bitstream D_AP in Serial to Parallel converter 56, data check and correction module 58 evaluates bitstream D_p according to the ECC type thereof in step S804, outputs parallel bitstream D_p as output bitstream D_out if the ECC evaluation is errorless (step S810), and inverts the ambiguous bit to the other possible state by XORing bitstream D_p and D_AP and producing inverted bitstream D_SC, if the ECC evaluation is erroneous (step S806). Then in step S808, data check and correction module 58 again evaluates inverted bitstream D_SC according to the ECC type thereof, outputs inverted bitstream D_SC as output bitstream D_out if the ECC evaluation is errorless (step S812), and outputs original bitstream D_p otherwise (step S810). Decoding method 8 continues to decode input signal S_in by steps S802˜S812, until the process is terminated.

FIG. 9 is another block diagram of an exemplary bitstream slicer of the invention, comprising SYNC separator 10, line counter 12, slicer 94, Serial to Parallel converter 96, and bitstream check and correction module 98. SYNC separator 10 is coupled to line counter 12, slicer 94, Serial to Parallel converter 96, and subsequently to bitstream check and correction module 98.

Data slicer 9 is identical to bitstream slicer 5, except bitstream slicer 9 generates high bitstream D_HS and low bitstream D_LS with high threshold level S_thH and low threshold level S_thL to compensate ambiguous bitstream nearby main threshold level S_th. Slicer 94 compares input signal S_in with main threshold level S_th, high threshold level S_thH, and low threshold level S_thL to generate serial main bitstream D_MS, high bitstream D_HS, and low bitstream D_LS, where each bit of bitstream D_MS, D_HS, D_LS is one of two possible states.

Serial to parallel converter 96 stores serial bitstream D_MS, D_HS, D_LS in a buffer therein, and converts and outputs serial bitstream D_MS, D_HS, D_LS to parallel bitstream D_MP, D_HP, D_LP.

Data check and correction module 98 evaluates ECC of bitstream D_MP to determine accuracy, if main bitstream D_MP is erroneous, evaluates whether high bitstream D_HP is erroneous according to the corresponding error checking code, and outputs main bitstream D_MP as output bitstream D_out otherwise. If high bitstream D_HP is erroneous, bitstream check and correction module 98 further evaluates whether low bitstream D_LP is erroneous according to the corresponding correction code, and outputs high bitstream D_HP as output bitstream D_out if ECC evaluation is correct. And finally, if low bitstream D_LP is correct, bitstream check and correction module 98 outputs low bitstream D_LP as output bitstream D_out, otherwise outputs original bitstream D_MP. Data check and correction module 58 performs odd parity or Hamming 8/4 check based on packet number C_P and number of bitstream bytes C_B, as indicated in FIGS. 4a and 4b.

FIGS. 10 a, b, and c are waveform diagrams slicing bitstream with multiple threshold levels, incorporating data slicer 9 in FIG. 9.

FIG. 10 a incorporates odd parity ECC and fixed threshold level S_th. Slicer 94 generates main bitstream D_MS ‘1010 1100’, high bitstream D_HS ‘1000 1100’, and low bitstream D_LS ‘1010 1100’ with main threshold level S_th, high threshold level S_thH, and low threshold level S_thL. Data check and correction module 98 performs parity check on main bitstream D_MS, bitstream D_MS is erroneous, and therefore performs another parity check on high bitstream D_HS. Because the parity check of high bitstream D_HS is errorless, Data check and correction module 98 outputs high bitstream D_HP as output bitstream D_out.

FIG. 10 b incorporates Hamming 8/4 ECC and fixed threshold level S_th. Slicer 94 generates main bitstream D_MS ‘1010 1100’, high bitstream D_HS ‘1000 1100’, and low bitstream D_LS ‘1010 1100’ with main threshold level S_th, high threshold level S_thH, and low threshold level S_thL. Data check and correction module 98 evaluates Hamming 8/4 ECC based on main bitstream D_MS, bitstream D_MS is erroneous, and therefore evaluates another Hamming 8/4 ECC based on high bitstream D_HS. Because the parity check of high bitstream D_HS is correct, Data check and correction module 98 outputs high bitstream D_HP as output bitstream D_out.

FIG. 10 c incorporates parity check ECC and adaptive threshold level S_th. Threshold level S_th is adaptive according to bitstream part of input signal S_in, the distance between high threshold level S_thH and adaptive threshold level S_th is fixed, as is the distance between high threshold level S_thH and adaptive threshold level S_th. Slicer 94 generates main bitstream D_MS ‘1010 1100’, high bitstream D_HS ‘1000 1100’, and low bitstream D_LS ‘1010 1100’ with main threshold level S_th, high threshold level S_thH, and low threshold level S_thL. Data check and correction module 98 performs parity check on main bitstream D_MS, bitstream D_MS is erroneous, and therefore performs another parity check on high bitstream D_HS. Because the parity check of high bitstream D_HS is correct, Data check and correction module 98 outputs high bitstream D_HP as output bitstream D_out.

FIG. 11 is a flowchart of an exemplary decoding method incorporating data slicer 9 in FIG. 9. In step S1100, slicer 94 determines slicing frequency and threshold level S_th according to clock_run_in during initialization. Next in step S1102, slicer 94 compares input signal S_in with main threshold level S_th, high threshold level S_thH, and low threshold level S_thL to generate serial main bitstream D_MS, high bitstream D_HS, and low bitstream D_LS, each bit of bitstream D_MS, D_HS, and D_LS being one of two possible states. After converting to parallel bitstream D_MP, D_HP, and D_LP in Serial to Parallel converter 96, data check and correction module 98 evaluates bitstream D_MP according to the ECC type thereof in step S1104, outputs main bitstream D_MP as output bitstream D_out if the ECC evaluation is errorless (step S1118), and evaluates ECC of high bitstream D_HP if the ECC evaluation of bitstream D_MP is erroneous (step S1108). Data check and correction module 98 outputs high bitstream D_HP as output bitstream D_out if high bitstream D_HP is errorless (step S1110), and further evaluates ECC of low bitstream D_LS otherwise (step S1114). In step S1116, data check and correction module 98 outputs low bitstream D_LS as output bitstream D_out if ECC evaluation thereof is correct, and outputs the original main bitstream D_MS otherwise. Decoding method 11 continues to decode input signal S_in by steps S1102˜S1118, until the process is terminated.

FIG. 12 is yet another block diagram of an exemplary data slicer of the invention, comprising SYNC separator 10, line counter 12, slicer 124, Serial to Parallel converter 126, and data check and correction module 128. SYNC separator 10 is coupled to line counter 12, slicer 124, Serial to Parallel converter 126, and subsequently to data check and correction module 128.

Data slicer 12 combines the ambiguous range in data slicer 5 and multiple threshold levels in data slicer 9 to compensate ambiguous bitstream near main threshold level S_th. Slicer 124 compares input signal Sin with main threshold level S_th, high threshold level S_thH, and low threshold level S_thL to generate serial main bitstream D_MS, high bitstream D_HS, and low bitstream D_LS, where each bit of bitstream D_MS, D_HS, D_LS is one of two possible states.

Serial to parallel converter 126 stores serial bitstream D_MS, D_HS, D_LS in a buffer therein, and converts and outputs serial bitstream D_MS, D_HS, D_LS to parallel bitstream D_MP, D_HP, D_LP.

Serial to parallel converter 126 performs XOR to bitstream D_HP and D_LP to generate inverted bitstream D_AP, and outputs which to data check and correction module 128.

Data check and correction module 128 evaluates ECC of bitstream D_MP to determine accuracy, and outputs bitstream D_MP as output bitstream D_out if bitstream D_MP is correct. Data check and correction module 128 then performs another ECC check on inverted bitstream D_AP, further evaluates ECC of multiple threshold levels (high bitstream D_HP or low bitstream D_LP) if inverted bitstream D_AP is erroneous, and outputs inverted bitstream D_AP otherwise. Next Data check and correction module 128 performs yet another ECC check on the bitstream of multiple threshold levels, evaluates ECC of the other multiple threshold level if the bitstream is erroneous, and outputs the correct bitstream otherwise.

FIG. 13 is a flowchart of an exemplary decoding method incorporating data slicer 12 in FIG. 12. In step S1300, slicer 124 determines slicing frequency and threshold level S_th according to clock_run_in during initialization. Next in step S1302, slicer 124 compares input signal S_in with main threshold level S_th, high threshold level S_thH, and low threshold level S_thL to generate serial main bitstream D_MS, high bitstream D_HS, and low bitstream D_LS, each bit of bitstream D_MS, D_HS, and D_LS is one of two possible states. After converting to parallel bitstream D_MP, D_HP, and D_LP, and XORing D_HP and D_LP to form inverted bitstream D_AP (step S1306) in Serial to Parallel converter 126, data check and correction module 128 evaluates validity of bitstream D_MP according to the ECC type thereof in step S1304, outputs main bitstream D_MP as output bitstream D_out if the ECC evaluation is errorless (step S1318), otherwise evaluates ECC of inverted bitstream D_AP (step S1308). Data check and correction module 128 outputs inverted bitstream D_AP as output bitstream D_out if inverted bitstream D_AP is errorless (step S1310), and further evaluates ECC of the multiple threshold level bitstream (high bitstream D_HP or low bitstream D_LP) otherwise (step S1314). In step S1316, bitstream check and correction module 128 outputs the multiple threshold level bitstream as output bitstream D_out if ECC evaluation thereof is correct, and outputs the original main bitstream D_MS otherwise. Decoding method 13 continues to decode input signal S_in by steps S1302˜S1318, until the process is terminated.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A data slicer, slicing an input signal, comprising: a comparator comparing the input signal with a threshold level to generate a first bitstream, and identifying an ambiguous bit in the first bitstream when the corresponding input signal is determined as belonging to an ambiguous range; anda data check module, evaluating whether the first bitstream is erroneous according to an error checking code thereof, and inverting at least one ambiguous bit if the first bitstream is erroneous;wherein the ambiguous range includes the threshold level.

2. The data slicer of claim 1, wherein the ambiguous range is fixed and the threshold level is the middle of the ambiguous range.

3. The data slicer of claim 1, wherein the ambiguous range is adaptive.

4. The data slicer of claim 1, wherein the threshold level is adaptive based on the first bitstream.

5. The data slicer of claim 1, wherein the error checking code is parity check code.

6. The data slicer of claim 1, wherein the error checking code is Hamming code.

7. The data slicer of claim 1, wherein the comparator generates an ambiguous bitstream carrying the ambiguous bit for the data check module.

8. The data slicer of claim 1, wherein the data check module further evaluates whether the first bitstream after inverting the ambiguous bit is erroneous according to the error checking code, and outputs the original first bitstream if the inverted first bitstream is invalid.

9. The data slicer of claim 1, wherein: the comparator further compares the input signal with a second threshold level to generate a second bitstream; andthe data check module further evaluates whether the inverted first bitstream is erroneous according to the error checking code, evaluating whether the second bitstream is erroneous according to the error checking code if the inverted first bitstream is erroneous, and outputting the second bitstream if it is errorless, else outputting the first bitstream.

10. The data slicer of claim 9, wherein: the comparator further compares the input signal with a third threshold level to generate a third bitstream; andthe data check module further evaluates whether the third bitstream is erroneous according to the error checking code if the second bitstream is erroneous, and outputting the third bitstream if it is errorless, else outputting the first bitstream.

11. The data slicer of claim 10, wherein the second threshold level is higher than the first threshold level, and the third threshold level is lower than the first threshold level.

12. The data slicer of claim 1, wherein the input signal is a television signal, and the data slicer further comprises: a SYNC separator, receiving the input signal to generate HSYNC and VSYNC signals; anda counter coupled to the SYNC separator and the comparator, receiving the HSYNC and VSYNC signals to enable the comparator.

13. A data slicer, slicing an input signal, comprising: a comparator comparing the input signal with a first threshold level to generate a first bitstream, and comparing the input signal with a second threshold level to generate a second bitstream, where each bit of the first and second bitstream is one of two possible states; anda data check module, evaluating whether the first and second bitstream are erroneous according to an error checking code thereof, and outputting one of the bitstreams based on the evaluation result.

14. The data slicer of claim 13, wherein the data check module evaluates the second bitstream if the first bitstream is erroneous, and outputs the second bitstream if the evaluation result shows the second bitstream is errorless, else outputs the first bitstream.

15. The data slicer of claim 13, wherein: the comparator further compares the input signal with a third threshold level to generate a third bitstream; andthe data check module further evaluates whether the third bitstream is erroneous according to the error checking code if the second bitstream is erroneous, and outputs the third bitstream if it is errorless.

16. The data slicer of claim 13, wherein the first threshold level is adaptive based on the input signal.

17. The data slicer of claim 13, wherein the error checking code is parity check code.

18. The data slicer of claim 13, wherein the error checking code is Hamming code.

19. The data slicer of claim 13, wherein the comparator further identifies an ambiguous bit in the first bitstream when the corresponding input signal is determined as belonging to an ambiguous range; andthe data check module further inverts at least an ambiguous bit if the second bitstream is erroneous, evaluates whether the inverted first bitstream is erroneous using the error checking code, and outputs the first bitstream if the inverted first bitstream is erroneous; andwherein the ambiguous range includes the first threshold level.

20. The data slicer of claim 13, wherein the input signal is a television signal, and the data decoder further comprises: a SYNC separator, receiving the input signal to generate HSYNC and VSYNC signals; anda counter coupled to the SYNC separator and the comparator, receiving the HSYNC and VSYNC signals to enable the comparator.

21. A method of slicing an input signal, comprising: comparing the input signal with a threshold level to generate a first bitstream;identifying an ambiguous bit in the first bitstream when the corresponding input signal is determined as belonging to an ambiguous range;evaluating whether the first data is inaccurate according to an error checking code thereof; andinverting at least an ambiguous bit if the first bitstream is erroneous; andwherein the ambiguous range includes the threshold level.

22. The method of claim 21, wherein the ambiguous range is fixed and the threshold level is the middle of the ambiguous range.

23. The method of claim 21, wherein the ambiguous range is adaptive.

24. The method of claim 21, wherein the threshold level is adaptive based on the input signal.

25. The method of claim 21, wherein the error checking code is parity check code.

26. The method of claim 21, wherein the error checking code is Hamming code.

27. The method of claim 21, further comprising evaluating whether the inverted first data is erroneous using the error checking code, and outputs the first bitstream if the inverted first bitstream is erroneous.

28. The method of claim 21, further comprising: comparing the input signal with a second threshold level to generate a second bitstream; andevaluating whether the inverted first bitstream is erroneous using the error checking code, and evaluating whether the second bitstream is erroneous according to the error checking code if the inverted first bitstream is erroneous.

29. The method of claim 21, wherein the input signal is a television signal, and the method further comprises: receiving the input signal to acquire HSYNC and VSYNC signals; andenabling comparison between the input signal and the threshold level according to the HSYNC and VSYNC signals.

30. A method of slicing an input signal, comprising: comparing the input signal with a first threshold level to generate a first bitstream,comparing the input signal with a second threshold level to generate a second bitstream;evaluating whether the first and second bitstreams are erroneous according to an error checking code thereof, andoutputting one of the bitstreams based on the evaluation result.

31. The method of claim 30, wherein the second bitstream is evaluated if the first bitstream is erroneous, and it is output if the evaluation result shows the second bitstream is errorless.

32. The method of claim 30, wherein the second threshold level exceeds the first threshold level.

33. The method of claim 30, wherein the second threshold level is less than the first threshold level.

34. The method of claim 30, wherein the first threshold level is adaptive based on the first data.

35. The method of claim 30, wherein the error checking code is a parity check code.

36. The method of claim 30, wherein the error checking code is a Hamming code.

37. The method of claim 30, further comprising outputting the first bitstream if the second bitstream is erroneous, and outputting the second bitstream otherwise.

38. The method of claim 30, further comprising: identifying an ambiguous bit in the first bitstream when the corresponding input signal is determined as belonging to an ambiguous range; andinverting the ambiguous bit if the second bitstream is erroneous;evaluating whether the inverted first bitstream is erroneous using the error checking code; andoutputting the first bitstream if the inverted first bitstream is erroneous;wherein the ambiguous range includes the threshold level.

39. The method of claim 30, wherein the input signal is a television signal, and the method further comprises: receiving the input signal to acquire HSYNC and VSYNC signals; andenabling the comparison between the input signal and the first or second threshold level according to the HSYNC and VSYNC signals.