Patent Application
20080157880
The present invention relates generally to a loop filter, e.g., for a phase locked loop (PLL) circuit. For example, they may be used in data link clocks or to generate a CPU domain clock. In particular, it pertains to temperature compensation solutions for stabilizing the damping factor in a PLL.
In PLLs such as so called non self-biased PLLs, the damping factor (which is proportional to charge-pump current and loop filter resistance) can widely vary with temperature. Unfortunately, damping factor variations adversely affect PLL response to noise sources such as reference signal phase noise, VCC phase noise and feedback-network power supply noise. As a result, the quality of the PLL output signal may degrade. Since temperature typically changes dynamically during chip operation, PLL performance changes accordingly. Therefore, to attain stable PLL operation, damping factor variations due to changes in temperature should be reduced.
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
Presented herein are novel techniques to compensate for PLL damping factor variations due to temperature variations In some embodiments, PLL response may be stabilized for wide temperature variations, As a result, PLL jitter performance may also be improved.
The phase-frequency detector compares a reference signal REF and a feedback signal FBK to determine whether a frequency and/or phase difference exists between them. The feedback signal may directly correspond to the output of the voltage-controlled oscillator or may constitute a divided version of this output, achieved, e.g., by placing a divider circuit in a feedback path connecting the VCO and phase-frequency detector.
In operation, the phase-frequency detector determines whether a phase (or frequency) difference exists between the reference and feedback signals. If a difference exists, the detector outputs one of an Up signal and a Down signal to control the output of the charge pump. If the phase of the reference signal leads the phase of the feedback signal, the charge pump sources current to the loop filter to cause the VCO to advance the output phase/frequency. Conversely, if the phase of the reference signal lags the phase of the feedback signal, the charge pump sinks current from the loop filter to cause the VCO to reduce the output signal phase/frequency.
The amount of time current is sourced to or sinked from the loop filter corresponds to the width of the pulse of Icy. Since the width of this pulse is proportional to the phase/frequency difference between the reference and feedback signals, the loop filter will charge/discharge for an amount of time that will bring the phases of these signals into coincidence. The resulting signal output from the loop filter will therefore control the VCO to output a signal at a frequency and a phase which is not substantially different from the reference signal input into the phase-frequency detector.
With reference to
The charge pump 130 drives the filter 240 to generate the control voltage -VCNTL) for the VCO. The charge pump drives current into the loop filter to charge it, or sinks current from the loop filter to discharge it. For a given amount of time (ΔT) that ICP is at a particular value (which is a function of the charge pump output voltage (V1), the filter output voltage is: VCNTL=V0+RICP+(ICPΔT)/C, where Vo is the initial voltage charge across the capacitor.
The peak voltage of VCNTL determines the PLL damping factor. The peak voltage is primarily determined by ICPR. Thus, if ICP and R varies with temperature, so to does the PLL damping factor.
The TCRG circuit 401 generates a temperature dependent reference voltage and provides it to the amplifier as shown, Since the gain of the amplifier is high, the voltage V1 at the output of the charge pump follows the TCVref voltage. In the depicted embodiment, the TCVref signal increases with temperature thereby causing V1 to also increase with temperature. This causes the charge pump current ICP to decrease with temperature, countering the increase due to temperature increases, as well as the increase in the resistance of R. (It should be appreciated that any suitable circuit to generate a temperature compensating reference may be used to appropriately limit an increase in charge pump current and/or loop filter resistance as temperature increases. An example of such a suitable circuit is described in the following section.)
Thus, the current (Iout=Ia+Ib) generated in P2 and P1 (when engaged) is proportional to the circuit temperature. In turn, the voltage, TCVref, across Rout will be indicative of the circuit temperature and thus control the charge pump output voltage, and hence the charge pump output current, based on the temperature. Note that the actual TCVref voltage level can be calibrated by setting the current ratio Y/X to a desired value.
In the depicted embodiment, the temperature compensating reference generator circuit includes an offset adjustment feature to increase or decrease, on a stepwise basis, the TCVref voltage. This may be used, for example, to calibrate the TCVref voltage. This is achieved with temperature dependent current source transistor P1, which is engaged or disengaged by P2 based on the state of a temperature band select signal (Offset Adjustment). When Offset Adjustment is asserted, the current from the switched current source P1 is added to the current from current source P2. This changes the level of the TCVref voltage in a step. When P1 is engaged, TCVref “steps” upward.
For the PLL embodiment used with regard to
With reference to
It should be noted that the depicted system could be implemented in different forms. That is, it could be implemented in a single chip module, a circuit board, or a chassis having multiple circuit boards. Similarly, it could constitute one or more complete computers or alternatively, it could constitute a component useful within a computing system.
The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chip set components, programmable logic arrays (PLA), memory chips, network chips, and the like.
Moreover, it should be appreciated that example sizes/models/values/ranges may have been given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the FIGS. for simplicity of illustration and discussion, and so as not to obscure the invention. Further, arrangements may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
