1. Field
This disclosure relates to data storage systems. More particularly, the disclosure relates to systems and methods for compensating for temperature in hybrid data storage devices.
2. Description of Related Art
Certain data storage devices, such as hybrid storage devices comprising magnetic memory as well as semiconductor memory, can be adversely affected by high device temperatures. High temperature in a data storage device may result in damage to physical device hardware and/or corruption of data stored thereon.
Various embodiments are depicted in the accompanying drawings for illustrative purposes, and should in no way be interpreted as limiting the scope of this disclosure. In addition, various features of different disclosed embodiments can be combined to form additional embodiments, which are part of this disclosure.
While certain embodiments are described, these embodiments are presented by way of example only, and are not intended to limit the scope of protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the scope of protection.
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims. Disclosed herein are example configurations and embodiments relating to controller board layouts in data storage systems.
Overview
Hybrid data storage systems are data storage systems that may comprise one or more data storage sub-systems, namely one or more hard disk drives (HDD) comprising magnetic storage media, as well as one or more solid-state storage drives (SSDs) comprising non-volatile solid-state media such as NAND flash, for example. In the context of a singular device, a hybrid data storage device may include rotating magnetic storage and solid-state storage. The various embodiments disclosed herein may be applied to both such data storage systems and data storage devices. For the sake of simplicity of description, a generic singular hybrid data storage device will be used as the primary example to refer to and cover both applications.
As shown in
Certain embodiments disclosed herein provide for utilization within a hybrid data storage system/device of one or more temperature sensors or signals, wherein the hybrid system/device (e.g., drive firmware) is configured to identify workloads that cause or may cause undesirable increases in temperature based on a detection of device temperature, as indicated by the one or more temperature sensors or signals, exceeding a predetermined threshold. When such workload(s)/temperature(s) are identified, certain embodiments disclosed herein provide systems and/or methods for managing power associated with at least one or more non-volatile solid-state storage modules of the system/device. The power management systems and/or methods disclosed herein may involve transition from a full power mode to one or more lower-power modes, such as to a medium power mode, and further to a least power mode, in an embodiment. Such progression between power modes may allow for maintenance of device/system temperature substantially within safe or desirable ranges.
Certain alternative embodiments provide for power management systems and/or methods in which the temperature is allowed to rise to a maximum value or range, wherein once such value or range is exceeded, use of the non-volatile solid-state memory (NVSM) may be discontinued and/or data stored on the NVSM is migrated at least in part to magnetic media of the hybrid drive. Access to such data may thereafter be achieved through the magnetic media.
Hybrid Data Storage Device
The host commands received by the controller 130 from the host system 110 may include data read/write commands, and the like. The controller 130 may be configured to receive data commands from a storage interface (e.g., a device driver) 112 residing on a host system 110. Data may be accessed/transferred based on such commands. The host's storage interface 112 can communicate with the hybrid data storage device 120 using any known communication protocol, such as SATA, SCSI, SAS, USB, Fibre Channel, PCIe, eMMC, or the like.
As used in this application, “non-volatile solid-state memory,” “NVSM,” “non-volatile memory,” “NVM,” or variations thereof may refer to solid-state memory such as NAND flash. However, the systems and methods of this disclosure may also be useful in more conventional hard drives and hybrid drives including both solid-state and hard drive components. Solid-state memory may comprise a wide variety of technologies, such as flash integrated circuits, Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory, NOR memory, EEPROM, Ferroelectric Memory (FeRAM), MRAM, or other discrete NVM (non-volatile solid-state memory) chips. The non-volatile solid-state memory arrays or storage devices may be physically divided into planes, blocks, pages, and sectors, as is known in the art. Other forms of storage (e.g., battery backed-up volatile DRAM or SRAM devices, magnetic disk drives, etc.) may additionally or alternatively be used.
The hybrid data storage device 120 can store data received from the host system 110 such that the data storage device 120 acts as data storage for the host system 110. To facilitate this function, the controller 130 may implement a logical interface. The logical interface can present to the host system memory as a set of logical addresses (e.g., sequential/contiguous addresses) where data can be stored. Internally, the controller 130 can map logical addresses to various physical memory addresses in the non-volatile solid-state storage 140 and/or magnetic storage module 160.
Mapping data indicating the mapping of logical addresses to physical memory addresses may be maintained in the data storage device 120. For example, mapping table data may be stored in non-volatile solid-state storage 140 and/or magnetic storage module 160 in order to allow for recreation of mapping tables following a power cycle. In certain embodiments, the controller may maintain a mapping table to address the NVSM mapping, whereas the magnetic storage 160 portion of the hybrid device 120 is addressed directly. Furthermore, the controller 130 may maintain a special mapping table to determine whether data is stored in the NVSM 140 or the magnetic storage 160.
The controller 130 may include one or more memory modules (not shown), such as non-volatile memory (e.g., ROM) and/or volatile memory (e.g., RAM, such as DRAM). In certain embodiments, the controller 130 may be configured to store information, including, for example, operating system(s) code, application code, system tables and/or other data in such memory module(s). On power-up, the controller 130 may be configured to load the data for use in operation of the data storage device. In one embodiment, the controller 130 is implemented on a SoC (System on Chip), though those skilled in the art will recognize that other hardware/firmware implementations are possible.
In order to prevent or reduce the effects of excessively-high temperatures in the storage device 120, or portion thereof, the hybrid data storage device 120 may include one or more temperature sensors 150, which may be disposed within a housing of the storage device. For example, one or more temperature sensors may be disposed in physical proximity to the magnetic storage 160, such as in, or associated with, a disk head and/or suspension structure of the magnetic storage. The temperature sensor(s) 150 may be configured to detect temperature levels associated with at least a portion of the hybrid data storage device 120.
The controller 130 may include a power management module 136, which may be configured to control the provision of power to one or more components of the hybrid data storage device 120. In certain embodiments, the power management is configured to at least partially cut off power to the solid-state storage 140, as well as to an optional bridge device 152, which may be coupled to the solid-state storage (NVSM) 140 and may perform some level of basic channel management of the NVSM, as well as signal processing. In some embodiments, the controller 130 may incorporate some of all of the functionalities of the bridge device and directly control the operations of the solid-state storage 140.
As shown and referenced above, in addition to the NVSM 140 and bridge device 152 components, the hybrid data storage device includes a magnetic storage module 160 which comprises magnetic media 164, such as a rotating hard disk drive (HDD). The controller 130 in this embodiment would thus manage data accesses to both the NVSM storage module 140 and the magnetic storage module 160. In one embodiment, a different interface may be used to connect the controller 130 to the magnetic storage module 160 than is used to connect the controller 130 to the bridge device 152 and/or NVSM 140.
Power Management
As described above, it may be necessary or desirable to prevent a data storage device, such as a hybrid device, from experiencing temperatures that exceed a maximum rating, or value, associated with the device. For example, a storage device may be adversely affected by temperatures above 60° C., or other value. Therefore, various mechanisms may be implemented within the scope of the present disclosure to reduce internal power consumption by solid-state storage modules or components, thereby reducing device temperature to some extent. In certain embodiments, the internal device temperature is monitored for the purpose of implementing power management of one or more components of the data storage system/device, such as solid-state memory components, to reduce power consumption thereof. Reducing power consumption as described herein may cause some amount of degradation of device performance; the tiered power management scheme described in greater detail below involves transitioning power allocation to solid-state storage from less power-conserving mode(s) to more power-conserving mode(s) as the device temperature crosses over predetermined threshold(s). Such transitioning may at least partially slow the device performance, while keeping the device temperature in substantially safe operational range.
At decision block 204, the process 200 involves determining whether the temperature of the storage device, or portion thereof, is greater than a predetermined threshold value. For example, the temperature threshold may be approximately 40° C., 50° C., 55° C., 60° C., or other value. If the temperature is not greater than the threshold value, the process may effectively terminate, or may involve waiting for a predetermined period of time or for the occurrence of one or more events, after which the process may return to block 202, wherein the temperature of the storage device may be reassessed.
If it is determined that the temperature is greater than the threshold value, the process 200 may involve, as shown at block 206, managing power to the solid-state memory of the data storage device according to certain power-throttling parameters. For example, the data storage system may enter a power throttling state. In a power throttling state, the storage device may implement any of the features and/or principles disclosed herein for reducing power consumption of one or more components of the data storage device in order to manage temperature. Temperature management according to the process 200 of
Power management as disclosed herein may utilize one or more timer values, which may be tracked by the device controller (e.g., controller 130). At block 308, the received host command may have been completed, or one or more operations associated with the host command may have been successfully completed. Once the host operation has been completed, the process 300 may involve waiting for receipt of a subsequent host command, wherein if such host command is not received within a pre-determined window of time defined by a timer value t1, as shown at block 310, the process 300 may involve powering down one or more components of the data storage device, such as a bridge device of the data storage device. If, however, a host command is received before the period of time t1, lapses, the process 300 may proceed back to block 312, which represents receipt of such host command. The process 300 may then continue in the illustrated loop.
The powering down of, e.g., the bridge device, as shown in block 312, may provide a mechanism for reducing temperature of the storage device, such as the temperature of one or more solid-state storage modules and/or other components of the data storage device. That is, the value of the timer variable t1 may be selected and/or implemented to create a desirable power-saving scheme. Furthermore, one or more additional timers may also be utilized in order to manage power-down of one or more additional components of the data storage device. For example, as shown, the process 300 may further involve, once the bridge device has been powered down a block 312, waiting for receipt of a subsequent host command at block 314. If a host command is received before the passage of a predetermined window of time defined by another timer value t2, similarly to the progression of the process 300 with respect to block 310, the process may proceed back to block 302 and continue in the illustrated loop. If, however, the predetermined secondary window of time represented by the timer value t2 lapses before a subsequent host command is received, the process 300 may involve further powering down one or more additional modules and/or components of the data storage device, such as the solid-state storage module. As described above, the solid-state storage module may be a component of a hybrid storage device including a magnetic storage component in addition to the solid-state memory module.
The process 300 illustrates an example power/temperature management process, wherein one or more timer values (e.g., t1, t2) are utilized to control the timing and/or sequence of powering down one or more components of the data storage device or system. Manipulation and/or variation of the timer values shown, or additional timer values (not illustrated in
If the determined rate of receipt of host commands is greater than the predetermined threshold, the process 400 proceeds to block 408 where the data storage device, or one or more components thereof, may be placed into a performance mode of operation. The performance mode may be associated with power management parameters commensurate with a general preference for high performance over power consumption concerns. That is, the performance mode 408 may be associated with maintaining one or more components of the data storage device, such as components associated with the solid-state memory, in a powered state, wherein power-down of such components is not aggressively invoked.
While in the performance mode 408, the temperature of the storage device may increase beyond one or more threshold levels. For example, in a hybrid data storage device, a data storage workload requiring simultaneous, or substantially-simultaneous, access to multiple components of the data storage device, such as to a magnetic memory module and one or more solid-state memory modules, may result in undesirable, uncomfortable and/or potentially-damaging rise in temperature within at least a portion of the data storage device. It may therefore be desirable and/or necessary to detect such a workload or condition in order to prevent temperatures from rising and/or remaining above critical levels.
In order to substantially prevent physical damage and/or integrity issues associated with storage device temperatures exceeding critical levels, the process 400 may involve implementing logical functionality in order to manage power to one or components of the data storage device. For example, as shown, the process 400 may include a decision block 410, wherein a temperature associated with one or more components of the data storage device is detected and/or determined and analyzed in some manner, as shown. For example, the process 400 may involve determining whether the detected temperature is greater than a threshold level T2. The process 400 may utilize any desirable or suitable value for T2, which serves as a threshold temperature above which power saving mechanisms may be implemented. For example, T2 may be at or around 55° C. In certain embodiments T2 is set at or about 40° C. As described in greater detail below, power throttling may involve setting timer values to effect aggressive shut off, or even complete shut off, of solid-state memory components.
If the temperature is less than the threshold level T2, the process 400 may proceed back to operational performance mode as represented by block 408. If, however, the temperature is greater than the threshold level T2, the process 400 may involve placing one or more components of the data storage device into a thermal throttling state. For example, the data storage device may be configured to operate in a plurality of thermal throttling states, depending on the temperature of the device.
As an example, when it is determined that the temperature is greater than the threshold level T2, but does not exceed a higher threshold level T1, the process 400 may involve placing the data storage device, or one or more components thereof, into a throttling state 412 (identified in
If it is determined that the temperature of the data storage device exceeds the higher threshold temperature level T1, the process 400 may involve placing the data storage device, or one or more components thereof, into a more aggressive throttling state 414 (identified in
In the process 400, when operating in one of the throttling states, or in performance mode, periodic or sporadic re-checking of temperature values may be implemented in order to continually determine which power-management/throttling state the data storage device should be in at a given time. For example, predetermined periodic intervals of time after entering any of the individual throttling states and/or performance mode state 408, such as every second, temperature may be reassessed and the power management state of the storage device may be modified accordingly in the event that the temperature condition of the storage device has changed in the interim. Furthermore, the process 400 may periodically or sporadically loop back to block 402 for reanalysis of the rate of host command receipt in order to continually determine whether the data storage device should operate in the power saving mode 406 or performance mode branch of the flow diagram 400.
Although any desirable timer values may be implemented to achieve power throttling for the various power throttling states of the process 400, the following example timer values may be used in an embodiment, wherein t1 represents a first timer associated with powering down a bridge device and t2 represents a second timer associated with powering down a solid-state memory module, as described above with reference to
Various power throttling mechanisms disclosed herein may provide the ability to maintain a hybrid storage system within an operational temperature range according to specifications associated with the device. Furthermore, embodiments may help to prevent a hybrid storage system from heating up other components of a computing system, such as in an environment in which the hybrid system (or non-hybrid solid-state storage system) is a component of a tablet computer, smartphone, laptop computer, or other computing device, where the device has a relatively small form factor, which may introduce a relatively higher risk of burn or discomfort when the user's skin or person is in direct contact with the system.
In certain embodiments, the temperature is allowed to rise to a maximum allowable temperature, at which point some or all of the data stored in the solid-state storage portion of the hybrid device is migrated to the magnetic disk portion of the device. Such a method may allow for the maintenance of device performance at an optimal level until the maximum temperature is reached.
Additional Embodiments
Those skilled in the art will appreciate that in some embodiments, other types of temperature compensation and/or power management systems can be implemented while remaining within the scope of the present disclosure. In addition, the actual steps taken in the processes discussed herein may differ from those described or shown in the figures. Depending on the embodiment, certain of the steps described above may be removed, and/or others may be added.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the protection. For example, the various components illustrated in the figures may be implemented as software and/or firmware on a processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or dedicated hardware. Also, the features and attributes of the specific embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. Although the present disclosure provides certain preferred embodiments and applications, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. Accordingly, the scope of the present disclosure is intended to be defined only by reference to the appended claims.
All of the processes described above may be embodied in, and fully automated via, software code modules executed by one or more general purpose or special purpose computers or processors. The code modules may be stored on any type of computer-readable medium or other computer storage device or collection of storage devices. Some or all of the methods may alternatively be embodied in specialized computer hardware.
Number | Name | Date | Kind |
---|---|---|---|
6856556 | Hajeck | Feb 2005 | B1 |
7126857 | Hajeck | Oct 2006 | B2 |
7430136 | Merry, Jr. et al. | Sep 2008 | B2 |
7447807 | Merry et al. | Nov 2008 | B1 |
7502256 | Merry, Jr. et al. | Mar 2009 | B2 |
7509441 | Merry et al. | Mar 2009 | B1 |
7596643 | Merry, Jr. et al. | Sep 2009 | B2 |
7653778 | Merry, Jr. et al. | Jan 2010 | B2 |
7685337 | Merry, Jr. et al. | Mar 2010 | B2 |
7685338 | Merry, Jr. et al. | Mar 2010 | B2 |
7685374 | Diggs et al. | Mar 2010 | B2 |
7733712 | Walston et al. | Jun 2010 | B1 |
7742353 | Chen | Jun 2010 | B2 |
7765373 | Merry et al. | Jul 2010 | B1 |
7898855 | Merry, Jr. et al. | Mar 2011 | B2 |
7912991 | Merry et al. | Mar 2011 | B1 |
7936603 | Merry, Jr. et al. | May 2011 | B2 |
7962792 | Diggs et al. | Jun 2011 | B2 |
8078918 | Diggs et al. | Dec 2011 | B2 |
8090899 | Syu | Jan 2012 | B1 |
8095851 | Diggs et al. | Jan 2012 | B2 |
8108692 | Merry et al. | Jan 2012 | B1 |
8122185 | Merry, Jr. et al. | Feb 2012 | B2 |
8127048 | Merry et al. | Feb 2012 | B1 |
8135903 | Kan | Mar 2012 | B1 |
8151020 | Merry, Jr. et al. | Apr 2012 | B2 |
8161227 | Diggs et al. | Apr 2012 | B1 |
8166245 | Diggs et al. | Apr 2012 | B2 |
8243525 | Kan | Aug 2012 | B1 |
8254172 | Kan | Aug 2012 | B1 |
8261012 | Kan | Sep 2012 | B2 |
8296625 | Diggs et al. | Oct 2012 | B2 |
8312207 | Merry, Jr. et al. | Nov 2012 | B2 |
8316176 | Phan et al. | Nov 2012 | B1 |
8341339 | Boyle et al. | Dec 2012 | B1 |
8375151 | Kan | Feb 2013 | B1 |
8392635 | Booth et al. | Mar 2013 | B2 |
8397107 | Syu et al. | Mar 2013 | B1 |
8407449 | Colon et al. | Mar 2013 | B1 |
8423722 | Deforest et al. | Apr 2013 | B1 |
8433858 | Diggs et al. | Apr 2013 | B1 |
8443167 | Fallone et al. | May 2013 | B1 |
8447920 | Syu | May 2013 | B1 |
8458435 | Rainey, III et al. | Jun 2013 | B1 |
8478930 | Syu | Jul 2013 | B1 |
8489854 | Colon et al. | Jul 2013 | B1 |
8503237 | Horn | Aug 2013 | B1 |
8521972 | Boyle et al. | Aug 2013 | B1 |
8549236 | Diggs et al. | Oct 2013 | B2 |
8583835 | Kan | Nov 2013 | B1 |
8601311 | Horn | Dec 2013 | B2 |
8601313 | Horn | Dec 2013 | B1 |
8612669 | Syu et al. | Dec 2013 | B1 |
8612804 | Kang et al. | Dec 2013 | B1 |
8615681 | Horn | Dec 2013 | B2 |
8638602 | Horn | Jan 2014 | B1 |
8639872 | Boyle et al. | Jan 2014 | B1 |
8683113 | Abasto et al. | Mar 2014 | B2 |
8700834 | Horn et al. | Apr 2014 | B2 |
8700950 | Syu | Apr 2014 | B1 |
8700951 | Call et al. | Apr 2014 | B1 |
8706985 | Boyle et al. | Apr 2014 | B1 |
8707104 | Jean | Apr 2014 | B1 |
8713066 | Lo et al. | Apr 2014 | B1 |
8713357 | Jean | Apr 2014 | B1 |
8719531 | Strange et al. | May 2014 | B2 |
8724422 | Agness et al. | May 2014 | B1 |
8725931 | Kang | May 2014 | B1 |
8745277 | Kan | Jun 2014 | B2 |
8751728 | Syu et al. | Jun 2014 | B1 |
8769190 | Syu et al. | Jul 2014 | B1 |
8769232 | Suryabudi et al. | Jul 2014 | B2 |
8775720 | Meyer et al. | Jul 2014 | B1 |
8782327 | Kang et al. | Jul 2014 | B1 |
8788778 | Boyle | Jul 2014 | B1 |
8788779 | Horn | Jul 2014 | B1 |
8788880 | Gosla et al. | Jul 2014 | B1 |
8793429 | Call et al. | Jul 2014 | B1 |
20070214375 | Burton | Sep 2007 | A1 |
20100174849 | Walston et al. | Jul 2010 | A1 |
20100250793 | Syu | Sep 2010 | A1 |
20110099323 | Syu | Apr 2011 | A1 |
20110283049 | Kang et al. | Nov 2011 | A1 |
20120260020 | Suryabudi et al. | Oct 2012 | A1 |
20120278531 | Horn | Nov 2012 | A1 |
20120284460 | Guda | Nov 2012 | A1 |
20120324191 | Strange et al. | Dec 2012 | A1 |
20130132638 | Horn et al. | May 2013 | A1 |
20130145106 | Kan | Jun 2013 | A1 |
20130290793 | Booth et al. | Oct 2013 | A1 |
20130311793 | Chang | Nov 2013 | A1 |
20140059405 | Syu et al. | Feb 2014 | A1 |
20140101369 | Tomlin et al. | Apr 2014 | A1 |
20140115427 | Lu | Apr 2014 | A1 |
20140133220 | Danilak et al. | May 2014 | A1 |
20140136753 | Tomlin et al. | May 2014 | A1 |
20140149826 | Lu et al. | May 2014 | A1 |
20140157078 | Danilak et al. | Jun 2014 | A1 |
20140181432 | Horn | Jun 2014 | A1 |
20140223255 | Lu et al. | Aug 2014 | A1 |