Patent Application
20240388252
This disclosure relates generally to electronic circuits, and more specifically, to systems and methods for providing temperature compensation in oscillators circuits.
An oscillator is an electronic circuit that produces a periodic, Alternating Current (AC) signal—e.g., a sine, square, or triangle wave—based upon a Direct Current (DC) input received from a power supply. Such circuits may be used in many different types of electronic devices, including clock generators, digital instruments, computers, processors, peripherals, etc.
The frequency of a conventional oscillator's output signal varies according to its operating temperature. In an “RC oscillator,” for instance, although the effective capacitance (C) of the circuit may not vary much in response to temperature changes, the effective resistance (R) does.
To address this, a temperature-compensated oscillator may include a first resistor having a positive temperature coefficient of resistance and a second resistor having a negative temperature coefficient of resistance. The resistors may be arranged in a way such that the effects of temperature upon the latter cancel out opposing effects upon the former. As a result, the frequency of a signal output by such temperature-compensated oscillator is less sensitive to temperature changes.
The inventors hereof have recognized, however, that in certain semiconductor manufacturing technologies (e.g., Fin Field Effect Transistor or “FinFET”), resistors with positive and negative coefficients may not be available on the same substrate, which again subjects oscillators fabricated thereon to frequency variation due to temperature changes.
The present invention(s) are illustrated by way of example and are not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Systems and methods described herein may reduce an oscillator's output frequency variation in response to temperature changes in order to meet the ever-increasing accuracy and precision demands faced by today's Integrated Circuit (IC) designers. These systems and methods are well suited for semiconductor manufacturing technologies where resistances have “only positive” or “only negative” temperature coefficients of resistance, such as, for example, 16 nm fin-shaped field-effect transistor (FinFET) technologies, or the like.
In various implementations, the oscillator's output frequency variation may be reduced, at least in part, through the selection of a resistor configured to couple a frequency-to-voltage converter to a common gate amplifier.
To illustrate the foregoing,
As shown, the output of current mode comparator 101 is coupled to the gate terminal of output transistor 103 (e.g., an n-channel metal-oxide semiconductor or “NMOS” transistor), which in turn is coupled to Current Controlled Oscillator (CCO) element 104 (e.g., a ring oscillator). The drain terminal of output transistor 103 is coupled to supply voltage rail (VDD), and the source terminal of output transistor 103 is coupled to CCO element 104.
CCO element 104 is coupled to level shifter 105. Level shifter 105 is configured to change the voltage level of its input, which is then provided to buffer 106 to produce output signal 107 (e.g., a clock signal or “CLKOUT”) for use by processing core 108 (e.g., in a Systems-on-Chip or “SoC”).
To attain frequency regulation, output signal 107 is received by phase splitter 109, which provides phases φ1 and φ2 (complementary clocks) back to current mode comparator 101. Frequency-to-voltage (F2V) converter 113 comprises a switched capacitor circuit configured to generate a voltage corresponding to an input frequency. Specifically, F2V converter 113 applies φ1 and φ2 to a network of switches and capacitors (C/2) coupled to common gate amplifier 116.
Current mode comparator 101 includes cascode current mirror 110, which receives voltage supply VDD. Current mode comparator 101 includes an input terminal via first NMOS transistor 112 where first current I1 flows, and an output terminal via second NMOS transistor 115 where second current I2 flows. The gates of first and second NMOS transistors 112 and 115 are coupled to each other.
The source terminal of first NMOS transistor 112 applies reference voltage Vref across reference voltage generator 111, which includes trimmed resistor R, such that Vref=I1*R.
Meanwhile, the source terminal of second NMOS transistor 115 produces feedback voltage VFB across compensating resistance Rm (coupled to ground via filter capacitor 114) and switch capacitors (C=C/2+C/2) in F2V converter 113, such that VFB=I2*(Rm+1/sC).
The drain terminal of second NMOS transistor 115 maintains Vctrl, which is coupled to compensating capacitor 102 and to the gate terminal of output transistor 103.
In some embodiments, the temperature coefficients of resistance of R and Rm may both be positive. Alternatively, the temperature coefficients of resistance of R and Rm may both be negative. Moreover, as described below, the resistance value of Rm may be selected to reduce a frequency dependency of output signal 107 with respect to changes in the operating temperature of FRO circuit 100.
FRO circuit 100 may be fabricated on an integrated circuit (IC) wafer or die using one of the many IC process technologies. For example, FRO circuit 100 may be integrated in a substrate or die manufactured from various semiconductor materials, such as Silicon (Si), Germanium (Ge), or Gallium arsenide (GaAs), using various technologies such as complementary metal-oxide semiconductor (CMOS), silicon on insulator (SOI), double-diffused metal-oxide semiconductor (DMOS), laterally diffused metal-oxide semiconductor (LDMOS), bipolar CMOS/DMOS (BCD), pseudomorphic high-electron-mobility transistor (pHEMT), enhancement/depletion mode (E/D-mode) pHEMT, etc.
In some deployments, FRO circuit 100 may be part of a larger digital logic system. For instance, FRO circuit 100 may be coupled to a power amplifier (PA) control system. In certain embodiments, all or part of the larger digital logic system including circuit 100 may be fabricated on a single chip. The single chip may be created using a single IC fabrication process or using multiple IC fabrication processes in combination.
For example, a digital logic chip containing FRO circuit 100 may be integrated in a substrate or die manufactured from various semiconductor materials. Different subsystems may each be fabricated using a unique IC material or process, or set of IC materials and processes. Within a larger digital system, circuit 100 may be fabricated using one set of IC materials and processes, and another subsystem may be fabricated using a different set of IC materials and processes. In various embodiments, FRO circuit 100 may be part of a larger digital logic system patterned onto a single chip, and it may occupy less than 5% or 1% of the total chip area.
Each of graphs 200 and 300 illustrates a different, yet positive temperature coefficient of resistance for resistors R and Rm.
Specifically, graph 200 shows that trimmed resistor R has a temperature coefficient of resistance α, such that its resistance varies linearly between approximately −0.04% and 1% as the temperature changes between −40° C. and 125° C.
Graph 300 shows that compensating resistor Rm has a temperature coefficient of resistance β, such that its resistance varies non-linearly between approximately −1% and 16% as the temperature changes between −40° C. and 125° C.
Given α and β, the resistance of compensating resistor Rm may be selected as follows. Once current mirror 110 gets locked, then:
Accordingly, the effective resistance Reff of circuit 100 is given by:
where ΔT represents a temperature change.
As such, so long as R*α=Rm*β, or Rm=R*α/β, the frequency of output signal 107 remains independent of temperature changes. In practice, although the values of α and β themselves vary with temperature, selection of Rm=R*α/β may nonetheless reduce, minimize, or eliminate frequency variation of output signal 107.
Each of graphs 400 and 500 provides curves that show a percentage of frequency variation of their respective circuits' outputs against device corners (typical-typical or “TT,” fast-fast or “FF,” slow-slow or “SS,” fast-slow or “FS,” and slow-fast “SF”) for a number of temperatures and supply voltages.
Resistance R within reference voltage generator 111 may be trimmed at typical voltage and temperature and the output frequency is maintained close to 32 kHz (within +/−1%). Trimming may be done across all process corners, and the post-trim frequency can vary due to voltage and temperature changes. Graphs 400 and 500 show that post-trim frequency variation across voltage and temperature is less than +/−1% of 32 kHz. For example, the curve labeled “sum of −40° C., 1.62 V” shows the frequency variation with respect to the frequency value at typical voltage (e.g., 1.8 V) and typical temperature (e.g., 25° C.). Furthermore, the frequency variation across voltage and temperature may be different at each device corner.
As shown, graph 400 depicts a frequency variation of 0.3738% to −0.7467% while graph 500 depicts a frequency variation of 0.5% to −1.5%. In other words, the output of FRO circuit 100 with temperature compensation (i.e., with Rm such that Rm=R*α/β) is subject to significantly reduced frequency variation compared to the output of a conventional circuit.
As such, the systems and methods described herein may provide temperature compensation in low current, low power, closed loop FRO oscillators. These systems and methods may implement temperature compensation using one or more resistors, and may be particularly applicable to devices fabricated using semiconductor manufacturing technologies where only one type of temperature coefficient of resistance (either positive or negative) is available.
In an illustrative, non-limiting embodiment, an oscillator circuit may include: a voltage generator coupled to an input terminal of a common gate amplifier through a first resistor, and a frequency-to-voltage converter coupled to another input terminal of the common gate amplifier through a second resistor. Moreover, the second resistor may be configured to reduce a frequency variation of the oscillator circuit in response to temperature changes.
In some cases, the oscillator may be fabricated with FinFET technology.
The oscillator circuit may also include a CCO coupled to an output terminal of a current mode comparator, a level shifter coupled to the CCO, a buffer coupled to the level shifter, and a phase splitter coupled to the buffer. The phase splitter may be coupled to the frequency-to-voltage converter.
In some implementations, the second resistance of the second resistor may be selected to reduce a difference between: (a) a product between a first resistance value of the first resistor and a first positive temperature coefficient of the first resistor, and (b) a product between the second resistance value of the second resistor and a second positive temperature coefficient of the second resistor. The first positive temperature coefficient may be different from the second positive temperature coefficient.
In other implementations, the second resistance of the second resistor may be selected to reduce a difference between: (a) a product between a first resistance value of the first resistor and a first negative temperature coefficient of the first resistor, and (b) a product between the second resistance value of the second resistor and a second negative temperature coefficient of the second resistor. The first negative temperature coefficient may be different from the second negative temperature coefficient.
In another illustrative, non-limiting embodiment, an electronic device may include: a circuit and an oscillator configured to provide a clock signal to the circuit, the oscillator further including a common gate amplifier coupled to a voltage generator through a first resistor and to a frequency-to-voltage converter through a second resistor, where the second resistor has a second resistance selected based, at least in part, upon a product between a first resistance of the first resistor and a temperature coefficient of the first resistor.
The temperature coefficient may include a first positive temperature coefficient, and the second resistance may be selected based, at least in part, upon a difference between: (a) a product between the first resistance and the first positive temperature coefficient, and (b) a product between the second resistance and a second positive temperature coefficient of the second resistor. The first positive temperature coefficient may be different from the second positive temperature coefficient.
Alternatively, the temperature coefficient may include a first negative temperature coefficient, and the second resistance may be selected based, at least in part, upon a difference between: (a) a product between the first resistance and the first negative temperature coefficient, and (b) a product between the second resistance and a second negative temperature coefficient of the second resistor. The first negative temperature coefficient is different from the second negative temperature coefficient.
In yet another illustrative, non-limiting embodiment, a method may include: coupling a voltage generator to a common gate amplifier through a first resistor; and coupling a frequency-to-voltage converter to the common gate amplifier through a second resistor, where the second resistor has a second resistance selected based, at least in part, upon a first resistance of the first resistor.
The second resistance may be selected based, at least in part, upon a difference between: (a) a product between the first resistance and a first positive temperature coefficient of the first resistor, and (b) a product between the second resistance and a second positive temperature coefficient of the second resistor.
Alternatively, the second resistance may be selected based, at least in part, upon a difference between: (a) a product between the first resistance and a first negative temperature coefficient of the first resistor, and (b) a product between the second resistance and a second negative temperature coefficient of the second resistor.
In many implementations, systems and methods described herein may be incorporated into a wide range of electronic devices including, for example, computer systems or Information Technology (IT) products such as servers, desktops, laptops, memories, switches, routers, etc.; telecommunications hardware; consumer devices or appliances such as mobile phones, tablets, wearable devices, Internet-of-Things (IOT) devices, television sets, cameras, sound systems, etc.; scientific instrumentation; industrial robotics; medical or laboratory electronics such as imaging, diagnostic, or therapeutic equipment, etc.; transportation vehicles such as automobiles, buses, trucks, trains, watercraft, aircraft, etc.; military equipment, etc. More generally, these systems and methods may be incorporated into any device or system having one or more electronic parts or components.
For sake of brevity, conventional techniques have not been described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein have been intended to illustrate relationships (e.g., logical) or physical couplings (e.g., electrical) between the various elements. It should be noted, however, that alternative relationships and connections may be used in other embodiments. Moreover, circuitry described herein may be implemented either in silicon or another semiconductor material or alternatively by software code representation thereof.
Although the invention(s) are described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention(s), as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention(s). Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Reference is made herein to “configuring” a device or a device “configured to” perform some operation(s). It should be understood that this may include selecting predefined logic blocks and logically associating them. It may also include programming computer software-based logic of a retrofit control device, wiring discrete hardware components, or a combination of thereof. Such configured devices are physically designed to perform the specified operation(s).
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The terms “coupled” or “operably coupled” are defined as connected, although not necessarily directly, and not necessarily mechanically. The terms “a” and “an” are defined as one or more unless stated otherwise. The terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”) and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a system, device, or apparatus that “comprises,” “has,” “includes” or “contains” one or more elements possesses those one or more elements but is not limited to possessing only those one or more elements. Similarly, a method or process that “comprises,” “has,” “includes” or “contains” one or more operations possesses those one or more operations but is not limited to possessing only those one or more operations.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311034695 | May 2023 | IN | national |
