Patent Application
20150355037
The invention relates to temperature sensing methods, and more particularly to temperature sensing methods which generate both a temperature dependent output frequency and a temperature independent output frequency.
According to a family of prior art, for example described in an article “CMOS Temperature Sensor with Ring Oscillator for Mobile DRAM Self-refresh Control” by Chan-Kyung Kim; IEEE 2008, P. 3094-3097, or in an article “Miniaturized CMOS Thermal Sensor Array for Temperature Gradient Measurement in Microprocessors” by Kosta Luria; IEEE 2010, P. 1855-1858, or in an article “A 0.0018 mm2 frequency-to-digital-converter-based CMOS smart temperature sensor” by Hokyu Lee; Analog Integr Circ Sig Process (2010); P.: 153-157, a type of digital temperature sensors is known which generates temperature dependent periodic signals, made with temperature dependent current starved ring oscillators or current starved ramp generators. As temperature gradients inside integrated chips can nowadays reach several ten of degrees Celsius, this digital temperature sensor is usually located very close to the hot spots of the integrated circuit. So, for the thermal sensor calibration, insensitive temperature current is commonly used, either to generate a second signal at the output of a matching delay line made by a ramp generator or ring oscillator which is only voltage and process dependent. Calibration solution of this type of digital temperature sensors can therefore be obtained by mixing the two signals which are respectively temperature dependent and temperature independent. However, this prior art presents several drawbacks.
Firstly, there is a limited precision in the temperature sensing. Indeed, this comes from the bad process correlation existing between temperature independent and temperature dependent currents, leading to a decrease of accuracy, because extra components are introduced, for example the resistor, for generating only one of either the temperature independent current or the temperature dependent current, but not generating the other one.
Secondly, there is a rather important needed area of the integrated circuit, which adds complexity and cost. Indeed, this comes from the need of a second oscillator associated to a second delay line, one oscillator using temperature dependent current and the other oscillator using temperature independent current. So, for the temperature sensor, the required integrated circuit area is multiplied by two.
Thirdly, there is an extra complexity in the design, coming from the need to try and match the different components which are used for these two different oscillators, in order to reduce the existing mismatch. Indeed, the two different oscillators with their two associated delay lines made with logic gates such as inverters will have to be well matched. So, layout constraints happen especially in term of device area and device routing leading either to lower temperature accuracy or to more complexity and cost to correct this temperature accuracy decrease.
All these drawbacks mainly come from the need for two different oscillators in order to be able to generate both a temperature dependent output frequency, for the sensing mode, and a temperature independent output frequency, for the calibration mode.
An object of embodiments of the present invention is to alleviate at least partly the above mentioned drawbacks.
More particularly, embodiments of the invention aim to provide a temperature sensing method allowing a calibration mode of the temperature sensor, without need for an extra oscillator dedicated to this calibration mode. Embodiments of the invention aim to provide for a temperature sensing method and a temperature sensor, presenting a sensing mode and a calibration mode, both these modes using the same oscillator to be able to make this same oscillator generate alternatively a temperature dependent signal, for the sensing mode, and a temperature independent signal, for the calibration mode.
Embodiments of the invention preferably aim to create, both and alternatively, a temperature dependent and a temperature independent frequency circuit from the same oscillator circuit, advantageously with a single and simple ramp generator. The switching between those two circuits will provide switching from a temperature independent output frequency, which is used for its calibration by using for example a reference clock usually available on the digital circuits, to a temperature dependent output frequency when the calibration is ended, which is then used for the sensing mode.
In embodiments of the invention, replacing the voltage independent of the temperature (VIOAT) signal by a voltage dependent and preferably proportional to the temperature (VPTAT) signal, without introducing any extra components and without requiring any extra circuit area, allows for the use of a single and same oscillator both in calibration and sensing mode, leading then to better accuracy and to less complexity, for the temperature sensing method and for the associated temperature sensor.
In embodiments of the invention, in a nutshell, there are a temperature dependent, for the normal sensing mode, and a temperature independent, for the calibration mode, signals which are both created by a single oscillator circuit and available at the output of this single oscillator circuit. The switching between those signals is obtained by switching between distinct parts in the controller of this single oscillator. Whereas, in the prior art, there are a temperature dependent, for the normal sensing mode, and a temperature independent, for the calibration mode, signals which are both respectively created by two distinct oscillator circuits and respectively available at the outputs of those two distinct oscillator circuits. Some interesting advantages of embodiments of the invention over prior art are globally less complexity, because of less components, and better accuracy, because of better correlation between both signals coming from same oscillator.
This object and other objects may be achieved with a temperature sensing method comprising:
This object and other objects may be achieved with a temperature sensor comprising:
Preferred embodiments comprise one or more of the following features:
According to a preferred embodiment of the invention, the temperature sensor is a digital temperature sensor.
According to a preferred embodiment of the invention, the temperature sensor, which is integrated within the integrated circuit also with the circuit of which the temperature is to be sensed that is preferably a microprocessor, is included in a square area of 100 μm by 100 μm; it covers for example an area of 70 μm by 80 μm.
Further features and advantages of the invention will appear from the following description of embodiments of the invention, given as non-limiting examples, with reference to the accompanying drawings listed hereunder.
When the integrated circuit is manufactured, including a circuit which temperature is to be sensed and a temperature sensor to sense the temperature of this circuit, the temperature sensor is calibrated in situ in a calibration step S1 where the temperature sensor generates a temperature independent output frequency. Then, in a switching step S2, a switching is performed between two circuit parts of a controller of the temperature sensor.
Then, in a sensing step S3, the temperature sensor generates a temperature dependent output frequency in the sensing mode, to sense the temperature of the circuit. This sensing mode is the normal working mode of the temperature sensor. Then, in a switching step S4, a reverse switching is performed between two circuit parts of the controller of the temperature sensor.
Then, in a calibration step S5, the temperature sensor generates again a temperature independent output frequency in the calibration mode, so that the temperature sensor can be recalibrated, that is to say calibrated again, when initial calibration has been lost due to drift of components in the course of time and use. This calibration mode is a rare and exceptional mode of the temperature sensor. Then, in a switching step S6, a switching is performed between two circuit parts of a controller of the temperature sensor.
Then, in a sensing step S7, the temperature sensor generates again a temperature dependent output frequency in the sensing mode, to sense the temperature of the circuit. The temperature sensor has come back to this sensing mode which is the normal working mode of the temperature sensor.
In
The controller 1 comprises a field effect transistor 5, preferably PMOS, one to P field effect transistors 6, preferably PMOS, disposed in parallel to one another, one to M field effect transistors 7, preferably PMOS, disposed in parallel to one another, a current source 8 generating a current IPTAT, a resistor 9 of a resistance value R2, a field effect transistor 10, preferably NMOS, a field effect transistor 11, preferably NMOS. Sources of all field effect transistors 5, 6 and 7, are connected to the voltage alimentation 3. Drain of field effect transistor 5 is both connected to gate of field effect transistor 5 and to current source 8 which in turn is connected to the ground 4.
In an alternative to the circuit shown on
The current source 8 generates a current IPTAT=VPTAT/R1, temperature dependent current IPTAT being equal to temperature dependent voltage VPTAT divided by resistance R1. The resistor 9 of resistance value R2 is preferably made with the same material as the resistance R1. Both temperature dependent current IPTAT and temperature dependent voltage VPTAT are proportional to the absolute temperature of the circuit of which temperature is to be sensed. Several design architectures for the current source 8, generating a current proportional to the absolute temperature of the circuit to be sensed, can be found using only MOS transistor or not. Some examples with only MOS transistors are given in
Gates of all field effect transistors 5, 6 and 7, are all connected together so that the current going through source and drain of field effect transistor 5 is mirrored in the current going through source and drain of all P field effect transistors 6 and of all M field effect transistors 7. Drains of the P field effect transistors 6 are connected to the drain of field effect transistor 10 and to the drain of field effect transistor 11 as well as to the gate of field effect transistor 11. The voltage on the gate of field effect transistor 11 is VREF. Sources of the field effect transistors 10 and 11 are connected to the resistor 9 which in turn is connected to the ground 4. Gate of field effect transistor 10 is connected to an external command signal SW.
The oscillator 2, which is a ramp generator 2, comprises a capacitor 12, a field effect transistor 13, preferably NMOS, a comparator 15, a pulse generator 16. Drains of the M field effect transistors 7 are connected to the capacitor 12 which in turn is connected to the ground 4, to the drain of field effect transistor 13 and to one of the inputs of the comparator 15 which then presents a voltage VRAMP which also is the voltage on the side of the capacitor 12 connected to the drains of the M field effect transistors 7. The gate of the field effect transistor 11 is connected to the other of the inputs of the comparator 15 which then presents a voltage VREF. The output of the comparator 15 is connected to the input of the pulse generator 16. The output of the pulse generator is connected to the gate of the field effect transistor 13.
Let it be assumed that for the initial conditions, VRAMP equals zero. IPTAT current coming from the drains of the M transistors 7 is used to load capacitor 12 until VRAMP reaches VREF. Then, the comparator 15 commutes. After that commutation, the pulse generator generates a pulse signal which is sent on the gate of transistor 13 to switch on transistor 13. The pulse delay time is as long as the time needed to download the capacitor 12. Following that download, transistor 13 is off again and the capacitor 12 starts again to be loaded by using the IPTAT current coming from the drains of the M transistors 7.
Switching from sensing mode to calibration mode is obtained by switching on the transistor 10 with external command signal SW. VREF signal which was temperature independent in sensing mode becomes a temperature dependent signal in calibration mode. VREF, now temperature dependent signal in calibration mode compensates for VRAMP which is always a temperature dependent signal, whether in calibration mode or in sensing mode. VREF equals VPTAT*P*(R2/R1) in calibration mode.
For this switching between transistors 11 and 10 to be fully efficient, transistor 10 should have an OFF state leakage current negligible against the current IPTAT generated by the current source 8 as well as against the IPTAT variations versus temperature. To make that, channel length of transistor 11 is preferably longer than the minimum channel length of transistor 10, at least between 4 and 20 times, for example 10 times, greater than the minimum channel length the technology. Leakage junction should also advantageously be negligible against IPTAT current generated by the current source 8 as well as against the IPTAT variations versus temperature. In sensing mode, VREF equals R2*IPTAT+VGS(N11), with VGS(N11) the drop of voltage through transistor 11. VREF then equals a constant value since VGS(N11) temperature variations exactly compensate for R2*IPTAT temperature variations.
VRAMP signal output frequency can be made a temperature independent signal or a temperature dependent signal simply by respectively switching off or on transistor 11. Offset voltage introduced in on state of transistor 11 could be negligible against input stage offset of the comparator 15 with IPTAT current value about 1 μA and on resistance value for transistor 11 about a few hundred of Ohm.
In a numerical example of an embodiment, the PMOS transistors 5, 6, 7 present following values: W=20 μm and L=2.6 μm. The NMOS transistor 11 presents following values: W=13.2 μm and L=2.6 μm. The NMOS transistor 10 presents following values: W=40 μm and L=0.26 μm. The NMOS transistor 13 presents following values: W=18 μm and L=0.5 μm. The minimal gate width value for this technology is 30 nm. The capacitor 12 presents a capacitance value of 0.57 pF.
It can be seen that neither additional component nor extra area is needed to generate the two different VRAMP signals, the temperature dependent and independent signals.
When VRAMP frequency is temperature independent, the oscillations period does not depend on IPTAT current, but this period is only proportional to the R2*C product, as has been seen in the calibration mode discussed above. The calibration system uses a reference clock, TCLK period, which can be used to adjust R2*C product. As the ratio R2/R1 is given to make VREF signal a temperature independent signal, R2*C product and VREF signal could be adjusted simultaneously. VRAMP calibration via R2*C product could be made even if the junction temperature is variable because VRAMP is temperature independent signal. This property is interesting when the oscillator 2 of the temperature sensor is placed close to hot spot circuits which have to run even during calibration phase or if junction temperature is not accurately known (few degrees Celsius error).
The oscillation period Tosc of the VRAMP voltage can be written: Tosc=(VREF*R1*C)/(M*VPTAT), what gives for the oscillation frequency Fosc: Fosc=(M*VPTAT)/(VREF*R1*C). Fosc is proportional to the absolute temperature if VREF is temperature independent when transistor 13 is switched off. The oscillator 2, which is a ramp generator 2, works in the sensing mode of the temperature sensor, which is its usual and normal mode.
When, on the contrary, in the calibration mode, VREF is temperature dependent, the oscillation period Tosc of the VRAMP voltage can be written: Tosc=[(R2*P)/(R1*M)]*R1*C=(P/M)*R2*C. Tosc is proportional to the product (R2*C) and does not depend on IPTAT temperature dependent current when transistor 10 is switched on. This calibration mode can be used for (R2*C) calibration from a reference signal Tref available on the circuit. Tref is the reference temperature, for example 27° C.
A reference clock, with TCLK period, coming from a Phase Loop Lock (PLL), is used to count the number of TCLK periods which can be found in an oscillation period Tosc. The calibration can be made the following way. A few hundreds of clock periods correspond to a reference temperature of 25° C. A two few hundreds of clock periods correspond to a temperature of 125° C. With a linear variation in between for the frequency, that makes each supplementary Celsius degree correspond to a few more clock periods that can be counted within the oscillation frequency Fosc. Frequency Fosc corresponds to a period Tosc.
Simulation results of temperature dependent and temperature independent frequency circuit oscillator designed to make digital temperature sensor in C28FDSOI technology are now shown, as an illustration of the solution proposed by an embodiment of the invention.
In the horizontal direction of the plotted diagrams are to be found the process cases: there are here 15 of them, numbered from P1 to P15. These process cases correspond to the following situations, with respect to the circuit described in
Process case P1, called TT_RC_TYP, corresponds to NMOS transistors being typical transistors, to PMOS transistors being typical transistors, to resistances having typical values within a dispersion range, to capacitor having a typical value within a dispersion range. Process case P2, called TT_RC_MIN, corresponds to NMOS transistors being typical transistors, to PMOS transistors being typical transistors, to resistances having minimal values within a dispersion range, to capacitor having a minimal value within a dispersion range. Process case P3, called TT_RC_MAX, corresponds to NMOS transistors being typical transistors, to PMOS transistors being typical transistors, to resistances having maximal values within a dispersion range, to capacitor having a maximal value within a dispersion range.
Process case P4, called FFA_RC_TYP, corresponds to NMOS transistors being fast transistors, to PMOS transistors being fast analogical transistors, to resistances having typical values within a dispersion range, to capacitor having a typical value within a dispersion range. Process case P5, called FFA_RC_MIN, corresponds to NMOS transistors being fast transistors, to PMOS transistors being fast analogical transistors, to resistances having minimal values within a dispersion range, to capacitor having a minimal value within a dispersion range. Process case P6, called FFA_RC_MAX, corresponds to NMOS transistors being fast transistors, to PMOS transistors being fast analogical transistors, to resistances having maximal values within a dispersion range, to capacitor having a maximal value within a dispersion range.
Process case P7, called SSA_RC_TYP, corresponds to NMOS transistors being slow transistors, to PMOS transistors being slow analogical transistors, to resistances having typical values within a dispersion range, to capacitor having a typical value within a dispersion range. Process case P8, called SSA_RC_MIN, corresponds to
NMOS transistors being slow transistors, to PMOS transistors being slow analogical transistors, to resistances having minimal values within a dispersion range, to capacitor having a minimal value within a dispersion range. Process case P9, called SSA_RC_MAX, corresponds to NMOS transistors being slow transistors, to PMOS transistors being slow analogical transistors, to resistances having maximal values within a dispersion range, to capacitor having a maximal value within a dispersion range.
Process case P10, called FS_RC_TYP, corresponds to NMOS transistors being fast transistors, to PMOS transistors being slow transistors, to resistances having typical values within a dispersion range, to capacitor having a typical value within a dispersion range. Process case P11, called FS_RC_MIN, corresponds to NMOS transistors being fast transistors, to PMOS transistors being slow transistors, to resistances having minimal values within a dispersion range, to capacitor having a minimal value within a dispersion range. Process case P12, called FS_RC_MAX, corresponds to NMOS transistors being fast transistors, to PMOS transistors being slow transistors, to resistances having maximal values within a dispersion range, to capacitor having a maximal value within a dispersion range.
Process case P13, called SF_RC_TYP, corresponds to NMOS transistors being slow transistors, to PMOS transistors being fast transistors, to resistances having typical values within a dispersion range, to capacitor having a typical value within a dispersion range. Process case P14, called SF_RC_MIN, corresponds to NMOS transistors being slow transistors, to PMOS transistors being fast transistors, to resistances having minimal values within a dispersion range, to capacitor having a minimal value within a dispersion range. Process case P15, called SF_RC_MAX, corresponds to NMOS transistors being slow transistors, to PMOS transistors being fast transistors, to resistances having maximal values within a dispersion range, to capacitor having a maximal value within a dispersion range.
In the vertical direction of the plotted diagrams are to be found a family of curves corresponding respectively to the following set of temperatures, 125° C., 100° C., 75° C., 50° C., 25° C., 0° C., and corresponding to plotting parameters. Depending on the parameter which is plotted, either all the curves of the family are distinct from one another, meaning that the parameter is temperature dependent, or all the curves are all mixed into one and a single curve, meaning that the parameter is temperature independent.
The invention has been described with reference to preferred embodiments. However, many variations are possible within the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 13305194.6 | Feb 2013 | EP | regional |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2014/052537 | 2/10/2014 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 61815027 | Apr 2013 | US |
