Patent Application
20100164954
This relates generally to graphics processing, including the use of graphics processors and general purpose processors used for graphics processing.
The graphics pipeline may be responsible for rendering graphics for games, computer animations, medical applications, and the like.
The level of detail of the graphics images that are generated may be less than ideal due to limitations in the graphics pipeline. The greater the detail that is provided, the slower the resulting graphics processing. Thus, there is a tradeoff between processing speed and graphics detail. New graphics processing pipelines, such as Microsoft® DirectX 11, increase the geometric detail by increasing the tessellation detail.
Tessellation is the formation of a series of triangles to render an image of an object starting with a coarse polygonal model. A patch is a basic unit at the coarse level describing a control cage for a surface. A patch may represent a curve or region. The surface can be any surface that can be described as a parametric function. A control cage is a low resolution model used by artists to generate smooth surfaces.
Thus, by providing a higher extent of tessellation, the level of graphical detail that can be depicted is greater. However, the processing speed may be adversely affected. In general, the processing time increases quadractically with increased image level of detail.
In accordance with some embodiments, tessellation time increases only linearly with the amount of tessellation. Conventionally, tessellation time grows as a quadratic function with the amount of tessellation detail. As a result, in some embodiments, tessellation time may be decreased and, in other embodiments, less powerful tessellators can be used to perform more detailed tessellations.
In some embodiments, the tessellation time may be saved and/or tessellation processing capability may be increased by pre-computing a series of pre-computed inner tessellations over a range of edge level of detail. This saves re-computing the inner tessellations at run time.
In accordance with some embodiments, the tessellation may use a triangular or quad primitive domain. Edge partitioning may involve dividing the edges into intervals. The more intervals that are used the higher level of detail of tessellation that is possible. Thus, increasing the edge level of detail may increase the resolution of the resulting tessellation.
The inner tessellation is the tessellation of primitive points inside the outer perimeter of the primitive. The outer band is made up of the perimeter of the primitive.
Referring to
The input assembler 12 reads vertices out of memory using fixed function operations, forming geometry, and creating pipeline work items. Auto generated identifiers enable identifier-specific processing, as indicated on the dotted line on the right in
The vertex shader 14 performs operations such as transformation, skinning, or lighting. It inputs one vertex and outputs one vertex. In the control point phase, invoked per output control point and each identified by a control point identifier, the vertex shader has the ability to read all input control points for a patch independent from output number. The hull shader 16 outputs the control point per invocation. The aggregate output is a shared input to the next hull shader phase and to the domain shader 20. Patch constant phases may be invoked once per patch with shared read input of all input and output control points. The hull shader 16 outputs edge tessellation factors and other patch constant data. As used herein, edge tessellation factor and edge level of detail with a number of intervals per edge of the primitive domain may be used interchangeably. Codes are segmented so that independent work can be done with parallel finishing with a join step at the end.
The tessellator 18 may be implemented in hardware or in software. In some advantageous embodiments, the tessellator may be a software implemented tessellator. By speeding up the operation of tessellator, as described herein, the cores that were doing tessellator operations may be freed up to do other tasks. The tessellator 18 may input, from the hull shader, numbers defining how much to tessellate. It generates primitives, such as triangles or quads, and topologies, such as points, lines, or triangles. The tessellator inputs one domain location per shaded read only input of all hull shader outputs for the patch in one embodiment. It may output one vertex.
The geometry shader 22 may input one primitive and outputs up to four streams, each independently receiving zero or more primitives. A stream arising at the output of the geometry shader can provide primitives to the rasterizer 24, while up to four streams can be concatenated to buffers 30. Clipping, perspective dividing, view ports, and scissor selection implementation and primitive set up may be implemented by the rasterizer 24.
The pixel shader 26 inputs one pixel and outputs one pixel at the same position or no pixel. The output merger 28 provides fixed function target rendering, blending, depth, and stencil operations.
Thus, referring to
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Thus, in some embodiments such as DirectX 11, there are only 64 discrete edge levels of detail. Other embodiments may use other numbers of edge levels of detail. The inner tessellation may be pre-computed for each of these edge levels of detail and stored for use at run time.
During run time, when an image is being processed, different edge levels of detail may be specified for different regions of the image. Typically, things closer to the camera (and, hence, the ones occupying larger screen space) will be tessellated more than the ones farther away from the camera. Thus, in an animation where a punch is thrown, the level of detail for the first may be highest and the regions away from the first may use lower level of detail. Thus, a relatively realistic rendering can be created because users may not notice the different levels of detail used in regions of less interest within the depiction. As a result, a wide variety of edge levels of detail may be encountered. Instead of calculating each of these levels of detail for the inner tessellation at run time as they arise, they may all be pre-computed, in some embodiments, and then looked up at run time and simply used without delaying the run time calculation with determining the values of the inner tessellation points and connectivity or triangulation.
In some embodiments, the patches may be sorted, based on their inner tessellation factor, using threading and vectorizing. The patches with the same level of detail are then tessellated on the same physical core of a multi-core processor 50, as indicated in
In accordance with one embodiment, the pseudo code may be implemented as follows:
The graphics processing techniques described herein may be implemented in various hardware architectures. For example, graphics functionality may be integrated within a chipset. Alternatively, a discrete graphics processor may be used. As still another embodiment, the graphics functions may be implemented by a general purpose processor, including a multicore processor.
References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
