Claims
- 1. A switching regulator having first, second, third and fourth terminals, comprising:
a first power transistor disposed between the first terminal and a first node, the first power transistor being partitioned into a plurality of individually-addressable first transistor segments; a second power transistor disposed between the first node and a second node, the second node coupling the second and fourth terminals, the second power transistor being partitioned into a plurality of individually-addressable second transistor segments; a filter including a capacitor and an inductor, the inductor being disposed between the first node and the third terminal, and the capacitor being disposed between the third and fourth terminals; and a controller operable in a plurality of modes including
a normal mode in which the controller opens and closes all of the first transistor segments and all of the second transistor segments; and a test mode in which the controller opens and closes less than all of the first transistor segments and all of the second transistor segments.
- 2. The switching regulator of claim 1, wherein each first transistor segment has a source coupled to the first terminal, a drain coupled to the first node and a gate coupled to the controller through a segment control line.
- 3. The switching regulator of claim 1, wherein each second transistor segment has a source coupled to the first node, a drain coupled to the second node arid a gate coupled to the controller through a segment control line.
- 4. The switching regulator of claim 1, wherein the controller operates in the normal mode in response to a substantially constant load.
- 5. The switching regulator of claim 4, wherein the controller is configured to switch to the test mode in response to a request to measure an on-resistance of a power transistor.
- 6. The switching regulator of claim 1, wherein the first power transistor is a p-channel MOSFET and the second power transistor is a n-channel MOSFET.
- 7. The switching regulator of claim 1, wherein all the second transistor segments have an equivalent transistor width.
- 8. A method for measuring an on-resistance of a power transistor integrated onto an integrated circuit chip, comprising:
providing a power transistor including a plurality of individually-addressable transistor segments; closing less than all of the transistor segments; measuring an on-resistance of the closed transistor segments; and deriving an on-resistance of the power transistor from the on-resistances of the transistor segments.
- 9. The method of claim 8, wherein:
the transistor segments are closed one at a time; an on-resistance of each closed transistor segment is measured; and an on-resistance of the power transistor is derived by averaging the on-resistances of all of the transistor segments.
- 10. The method of claim 8, wherein the transistor segments have an equivalent width.
- 11. The method of claim 8, wherein each transistor segment includes one or more single transistors connected in parallel.
- 12. A method of testing a switching regulator with a power transistor on an integrated circuit chip for use with an application board having circuitry that includes a first inductor with a first inductance and a first capacitor with a first capacitance, comprising:
providing a power transistor including a plurality of individually-addressable transistor segments on a chip; installing the chip on a testing board having circuitry that includes a second inductor with a second inductance greater than the first inductance and a first capacitor with a second capacitance less than the first capacitance; operating the circuit with the power transistor on the integrated circuit chip using less than all of the transistor segments; and measuring a closed-loop performance characteristic of the switching regulator.
- 13. The method of claim 12, wherein the performance characteristic is output voltage.
- 14. The method of claim 12, wherein the performance characteristic is line regulation.
- 15. The method of claim 14, wherein measuring the line regulation includes measuring first and second output voltages with different input voltages.
- 16. The method of claim 12, wherein the performance characteristic is load regulation.
- 17. The method of claim 16, wherein measuring the load regulation includes measuring first and second output voltages with different load currents.
- 18. The method of claim 17, wherein the different load currents include a minimum load current and a modified maximum load current.
- 19. The method of claim 18, wherein the modified maximum load current is less than a maximum load current for the switching regulator when installed on an application board.
- 20. The method of claim 18, wherein the application board has a first load current, and the test board has a second load current that is less than the first load current.
- 21. The method of claim 12, further comprising installing the chip on an application board having circuitry that includes a first inductor with a first inductance and a first capacitor with a first capacitance.
- 22. The method of claim 21, wherein the power transistor includes N transistor segments, and the operating step is performed using exactly one of the N transistor segments.
- 23. The method of claim 22, wherein the first inductance is L and the second inductance is L*N.
- 24. The method of claim 22, wherein the first capacitance is C and the second capacitance is C/N.
- 25. The method of claim 12, further comprising measuring an on-resistance of a closed transistor segment during operation of the circuitry.
- 26. The method of claim 25, further comprising deriving an on-resistance of the power transistor from the on-resistance of the closed transistor segment.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to provisional U.S. Application Serial No. 60/218,433, filed on Jul. 14, 2000.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60218433 |
Jul 2000 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
09766231 |
Jan 2001 |
US |
Child |
10461844 |
Jun 2003 |
US |