BRIEF DESCRIPTION OF DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 is a block diagram of a conventional graphics processing unit (GPU).
FIG. 2 a block diagram of a GPU according to an embodiment of the invention.
FIG. 3 is a block diagram of the pixel shader and texture engine in FIG. 2 according to an embodiment of the invention.
FIG. 4 shows a detailed structure of the video process unit according to an embodiment of the invention.
FIG. 5 is a flowchart showing a video processing method in a texture engine according to an embodiment of the invention.
DETAILED DESCRIPTION OF INVENTION
The following description comprises the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 2 shows a GPU 200 according to an embodiment of the invention. The GPU 200 is similar to the GPU 100 in FIG. 1 except for a pixel shader 208, a texture engine 210, and a memory unit 212. FIG. 2 uses the same reference numerals on elements shown as FIG. 1 which perform the same functions, and thus are not described in further detail. In addition to perform rendering process as conventional pixel shader, the pixel shader 208 dispatches a texture and video request with respect to each pixel data set to the texture engine 210 to fetch texture data therefor and allow the texture engine 210 to apply video processing on the pixel data according to the texture and video request. The texture engine 210 determines and provides the texture data to the pixel shader 208 in accordance with the received texture and video request, performs the video processing specified in the texture and video request on the pixel data, and outputs to the pixel shader 208. The memory unit 212, a local memory in a graphics card or a system memory in an integrated graphic chip, stores a plurality of texture maps and graphics data accessed by the texture engine 210.
FIG. 3 shows detailed structures of the pixel shader 208 and the texture engine 210 in FIG. 2 according to an embodiment of the invention. The pixel shader 208 comprises a texture access unit 302 and an arithmetic logic unit (ALU) pipe 304. The texture access unit 302 generates the texture and video request with respect to each pixel data set to the texture engine 210, wherein the texture and video request includes location information of the texture data required for the pixel data in a texture map stored in the memory unit 212 and information of the video processing required for the pixel data. The texture engine 210 comprises a texel location calculator 306, a texture cache unit 308 and a video processing unit 310. Receiving the texture and video request from the texture access unit 302 of the pixel shader 208, the texel location calculator 306 determines the texture data required for the pixel data and computes the memory address of the texture data in a texture map stored in the memory unit 212 in accordance with the information contained in the texture and video request.
Moreover, according to the texture and video request, the texel location calculator 306 also computes the memory addresses of graphics data in the memory unit 212. The texture cache unit 308 retrieves a copy of graphics data and texture data from the memory unit 212 with the memory addresses computed by the texel location calculator 306. The video processing unit 310, coupled to the texture cache unit 308, receives the graphics data therefrom and performs the video processing function required for the pixel data and specified in the texture and video request on the graphics data. The video processing unit 310 then outputs the texture data required in the texture and video request and graphics data after the video processing specified in the texture and video request to the ALU pipe 304 which then performs three-dimensional (3D) graphics computations thereon.
FIG. 4 shows a detailed structure of the video process unit 310 according to an embodiment of the invention. The video process unit 310 may comprise a de-interlacing unit 402, an edge detection unit 404, a motion detection unit 406, a de-blocking unit 408, a scaling unit 502, a color space conversion unit 504, and a gamma correction unit 506. The de-interlacing unit 402 is required when the input graphics data is in field format for conversion to frame mode. Various algorithms such as statistics-based or real-time estimation-based algorithms can be utilized in the edge detection unit 404 and motion detection unit 406. The de-block unit 408 eliminates rings appearing in the boundary of an image block. To perform de-block operations, the texture cache unit 308 retrieves these boundary pixels in the image block and the de-block unit 408 may simply apply filtering thereon. The scaling unit 502 may apply up-sampling or down sampling algorithms. For both algorithms, new rows or columns are obtained from the weighted sum of the neighboring rows or columns. Thus, the texture cache unit 308 may store these pixels of the neighboring rows and columns for scaling operations The-color space conversion unit 504 is required for graphics data input with different color formats while in the GPU, the color format of the pixel data is uniform. Further, to adjust non-linear display devices, the gamma correction unit 506 may be applied to perform gamma correction on the pixel data before displaying. Those skilled in the art may include other video processing units in accordance with design necessities.
FIG. 5 is a flowchart showing a video processing method in a texture engine according to an embodiment of the invention. First, a texture and video request for a pixel is received (S1). Here, the texture and video request may comprise location information of texture data for the pixel in a texture map stored in a memory unit 212 shown in FIG. 2 and information of video functions required for the pixel. Next, memory addresses of the texture data in the memory unit and graphics data required for the pixel is computed when performing the video functions specified in the texture and video request in the memory unit (S2). Next, a copy of graphics data and texture data is retrieved from the memory unit with the memory addresses (S3). Finally, the video functions specified in the texture and video request are performed on the graphics data (S4). The video functions may comprise such as, for example, performing de-interlacing operations, edge detection, motion detection, de-block operations, scaling processing, color space conversion, or gamma correction on the graphics data.
In the invention, the texture engine 210 not only provides texture data for the pixel data to the pixel shader 208 as conventional texture engines but also performs video operations on pixel data. Thus, the corresponding execution time required for the video operations on the pixel data is reduced, improving the execution efficiency of the pixel shader. For example, to apply 4×4 filter and color space conversion operation with the texture engine of the invention, the PS code therefor is as follows.
- texld r0, t0, s0//define s0 with 4×4 filter and color space conversion Mov oC0.rgba r0.rgba
Obviously, the execution time of the pixel shader is reduced compared to the PS code listed in the Table 1.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20080024510
