TFT array substrate and method for fabricating the same

Abstract

A four-mask process thin film transistor (TFT) array substrate and a method for fabricating the same is disclosed, which prevents a semiconductor tail from being formed. An open area is thus obtained and wavy noise is prevented from occurring. The method of fabricating a TFT array substrate comprises: forming a gate line, a gate electrode and a pad electrode on a substrate; sequentially depositing a gate insulation layer, a silicon layer and a metal layer on an entire surface of the substrate including the gate line; forming an open area in the pad electrode; forming a semiconductor layer, data line and source/drain electrodes by patterning the silicon layer and the metal layer; and forming a pixel electrode connected with the drain electrode and a transparent conductive layer connected with the pad electrode by depositing and patterning a transparent conductive material on the entire surface of the substrate including the data line, and simultaneously defining a channel region by separating the source and drain electrodes from each other.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention.

In the drawings:

FIGS. 1A through 1G are cross sectional views illustrating a method for fabricating a related art TFT array substrate;

FIG. 2 is a cross sectional view illustrating defects of a related art TFT array substrate;

FIG. 3 is a plan view illustrating a TFT array substrate according to the first embodiment of the present invention;

FIG. 4 is a cross sectional view illustrating a TFT array substrate according to the first embodiment of the present invention;

FIG. 5 is a cross sectional view illustrating an LCD device according to the present invention;

FIGS. 6A through 6K are cross sectional views illustrating a method for fabricating a TFT array substrate according to the first embodiment of the present invention;

FIG. 7 is a plan view illustrating a TFT array substrate according to the second embodiment of the present invention;

FIG. 8 is a cross sectional view illustrating a TFT array substrate according to the second embodiment of the present invention;

FIGS. 9A through 9D are plan views illustrating a TFT array substrate according to the second embodiment of the present invention;

FIGS. 10A through 10K are cross sectional views illustrating a method for fabricating a TFT array substrate according to the second embodiment of the present invention;

FIG. 11 is a plan view illustrating a TFT array substrate according to the third embodiment of the present invention;

FIG. 12 is a cross sectional view illustrating a TFT array substrate according to the third embodiment of the present invention;

FIG. 13 is a plan view illustrating a TFT array substrate according to the fourth embodiment of the present invention; and

FIG. 14 is a cross sectional view illustrating a TFT array substrate according to the fourth embodiment of the present invention.

Claims

1. A TFT array substrate comprising: a gate line and a gate electrode formed on a substrate;a gate insulation layer formed on the gate line and the gate electrode;a data line formed substantially perpendicular to the gate line to define a sub-pixel, and source and drain electrodes formed above the gate electrode;a semiconductor layer formed below the data line and the source and drain electrodes, wherein the semiconductor layer is formed in substantially the same pattern as those of the data line and the source and drain electrodes;a pixel electrode directly connected with the drain electrode without a contact hole;a gate pad electrode formed at the end of the gate line as one body; anda data pad electrode formed at the end of the data line.

2. The TFT array substrate of claim 1, further comprising a passivation layer above the pixel electrode, on the entire TFT substrate except the pixel electrode.

3. The TFT array substrate of claim 2, wherein the passivation layer is formed in a channel region between the source and drain electrodes.

4. The TFT array substrate of claim 1, wherein the edges of the source and drain electrodes in the channel region are positioned substantially along the same vertical lines as that of the pixel electrode above the source and drain electrodes.

5. The TFT array substrate of claim 1, further comprising a transparent conductive layer above the gate and data pad electrodes contacting with the gate and data pad electrodes.

6. The TFT array substrate of claim 5, wherein the transparent conductive layer is formed on the same layer as the pixel electrode.

7. The TFT array substrate of claim 5, further comprising a passivation layer above the transparent conductive layer on the entire TFT substrate except the transparent conductive layer.

8. The TFT array substrate of claim 1, wherein the data pad electrode is formed on the same layer as the gate pad electrode.

9. The TFT array substrate of claim 8, wherein the data line is electrically connected with the data pad electrode through the transparent conductive layer in contact with the data pad electrode.

10. The TFT array substrate of claim 1, wherein the data pad electrode is on the same layer as the data line and is formed as one body with the data line.

11. The TFT array substrate of claim 1, wherein the gate pad electrode is formed on the same layer as the gate line.

12. The TFT array substrate of claim 1, further comprising: a storage capacitor with a lower capacitor electrode on the same layer as the gate line;an upper capacitor electrode extending from the pixel electrode and overlapping with the lower capacitor electrode;and a gate insulation layer between the lower and upper capacitor electrodes.

13. The TFT array substrate of claim 1, wherein the gate insulation layer is on an entire surface of the substrate including the gate line or on the entire substrate except an open area of the sub-pixel.

14. The TFT array substrate of claim 1, wherein the passivation layer is formed on the entire surface of the substrate including the pixel electrode, or on the substrate except an open area of the sub-pixel.

15. The TFT array substrate of claim 1, wherein the pixel electrode is formed inside the entire area of the sub-pixel.

16. The TFT array substrate of claim 1, further comprising a common electrode formed in parallel to the pixel electrode on the substrate, to thereby form a horizontal electric field between the two electrodes.

17. A method of fabricating a TFT array substrate comprising: forming a gate line, a gate electrode and a pad electrode on a substrate;sequentially depositing a gate insulation layer, a silicon layer and a metal layer on an entire surface of the substrate including the gate line;forming an open area in the pad electrode;forming a semiconductor layer, data line and source/drain electrodes by patterning the silicon layer and the metal layer;and forming a pixel electrode connected with the drain electrode and a transparent conductive layer connected with the pad electrode by depositing and patterning a transparent conductive material on the entire surface of the substrate including the data line, and simultaneously defining a channel region by separating the source and drain electrodes from each other.

18. The method of claim 17, wherein the etching process for forming the pixel electrode and the etching process for separating the source and drain electrodes from each other are performed at the same time.

19. The method of claim 17, wherein a plasma treatment is performed on the channel region after defining the channel region by separating the source and drain electrodes from each other.

20. The method of claim 17, further comprising forming a passivation layer on the entire substrate except the portion having the transparent conductive layer.

21. The method of claim 20, wherein the channel region is covered with the passivation layer.

22. The method of claim 17, wherein the process of forming the open area in the pad electrode and the process of forming the semiconductor layer, the data line and source/drain electrodes by patterning the silicon layer and the metal layer are performed by one photolithography process.

23. The method of claim 22, wherein the process of forming the open area in the pad electrode and the process of forming the semiconductor layer, the data line and source/drain electrodes by patterning the silicon layer and the metal layer include: coating a photoresist onto the metal layer;patterning the photoresist the step coverage, whereby the photoresist has varied thicknesses therein;forming the open area in the pad electrode by etching the gate insulation layer, the silicon layer and the metal layer exposed by the patterned photoresist;ashing the photoresist to remove a substantially small thickness; andforming the semiconductor layer, the data line and source/drain electrodes by patterning the gate insulation layer, the silicon layer and the metal layer using the ashed photoresist as a mask.

24. The method of claim 23, wherein the silicon layer and the metal layer are etched at the same time, in the step of forming the semiconductor layer, the data line and the source/drain electrodes by patterning the gate insulation layer, the silicon layer and the metal layer using the ashed photoresist as a mask.

25. The method of claim 23, wherein the process of patterning the photoresist of the step coverage uses a diffraction exposure mask.

26. The method of claim 23, wherein the process of etching the gate insulation layer, the silicon layer and the metal layer includes: etching the metal layer above the pad electrodes by a wet-etching method; andetching the silicon layer and the gate insulation layer above the pad electrode by a dry-etching method.

27. The method of claim 23, wherein the process of etching the gate insulation layer, the silicon layer and the metal layer is performed in one dry-etching chamber.

28. The method of claim 17, wherein the pad electrodes include a gate pad electrode and a data pad electrode.

29. The method of claim 28, wherein the gate pad electrode is formed as one body with the gate line, and the data pad electrode is connected with the data line.

30. The method of claim 28, wherein the transparent conductive layer contacting the data pad electrode extends to the data line so that the transparent conductive layer contacts with the data line.

31. The method of claim 17, wherein a gate pad electrode is formed as one body with the gate line when forming the pad electrode, and a data pad electrode is formed as one body with the data line when forming the data line.

32. The method of claim 17, wherein a lower capacitor electrode is formed when forming the gate line.

33. The method of claim 32, wherein an upper capacitor electrode is electrically connected with the drain or pixel electrode formed on the gate insulation layer above the lower capacitor electrode.

34. The method of claim 17, wherein the gate and data lines are formed substantially perpendicular to one another to define a sub-pixel.

35. The method of claim 34, wherein the gate insulation layer is removed from the open area of the sub-pixel when forming the open area in the pad electrode.

36. The method of claim 34, wherein the pixel electrode is formed inside the entire area of the sub-pixel.

37. The method of claim 34, wherein a plurality of pixel electrodes are formed in the sub-pixel, and the common electrode is formed substantially in parallel to the pixel electrodes.

38. The method of claim 37, wherein the common electrode and the gate line are formed at the same time.