Patent Application
20150379919
This application claims the benefit of priority to Chinese Patent Application No. 201410309116.3, filed with the Chinese Patent Office on Jun. 30, 2014 and entitled “TFT ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE” the content of which is incorporated herein by reference in its entirety.
The present invention relates to the field of display technologies and particularly to a TFT array substrate, a display panel and a display device.
Display devices are becoming increasingly popular. The problem of inconvenient conversion between a 2D display effect and a 3D display effect of a display device exists in practical applications.
One inventive aspect is a TFT array substrate, including a plurality of gate lines, and a first gate drive circuit, where the first gate drive circuit includes m levels of first repeat units. Each level of first repeat unit includes a first shift register including a first input terminal, and a first output terminal connected with a corresponding gate line. The substrate also includes a second gate drive circuit, where the second gate drive circuit includes n levels of second repeat units. Each level of second repeat unit includes a second shift register including a second input terminal, and a second output terminal connected with a corresponding gate line. The substrate also includes a first start signal line. The substrate also includes a first start transistor, where a drain of the first start transistor is electrically connected with the first start signal line, a source of the first start transistor is electrically connected with the first input terminal of the first shift register of the first level of first repeat unit, and a gate of the first start transistor is electrically connected with a first control line. The substrate also includes a second start transistor, where a drain of the second start transistor is electrically connected with the first start signal line, a source of the second start transistor is electrically connected with the second input terminal of the second shift register of the first level of second repeat unit, and a gate of the second start transistor is electrically connected with a second control line. Among the second to m-th levels of first repeat units, the first input terminal of the first shift register in an i-th level of first repeat unit is electrically connected with the first output terminal of the first shift register in an (i−1)-th level of first repeat unit. In addition, among the second to n-th levels of second repeat units, the second input terminal of the second shift register in i-th level of second repeat unit is electrically connected with the second output terminal of the second shift register in (i−1)-th level of second repeat unit. Each of m, n and i are positive integers, and i is greater than or equal to 2 and less than or equal to at least one of m and n.
The drawings described here are intended to provide further understanding of the invention and constitute a part of the invention but not limit the invention. In the drawings:
a illustrates a simplified schematic diagram of a TFT array substrate according to an embodiment of the invention;
b illustrates a schematic structural diagram of another TFT array substrate according to an embodiment of the invention;
c illustrates a waveform diagram of a first control signal, a second control signal, a first switch signal and a second switch signal respectively in 3D and 2D display according to an embodiment of the invention;
a illustrates an enlarged diagram of the region C in
b illustrates an enlarged diagram of the region D in
The invention will be described below in further details and more fully with reference to the drawings and particular embodiments. As can be appreciated, the particular embodiments described here are merely intended to explain but not to limit the invention. Moreover it shall be further noted that only those parts relevant to the invention but not all the parts of the invention will be illustrated in the drawings for the sake of the convenient description.
Researchers have identified from their researches that an existing 3D display device includes a 3D display panel, on the surface of which a lens film is adhered, where each pixel is divided into two sub-pixels configured to transmit image data signals of left and right eyes respectively. When the 3D effect need be displayed, an image processing system processes the image data signals so that the image data signals transmitted by the two sub-pixels are different; when the 2D effect need be displayed, the image processing system processes the image data signals so that the image data signals transmitted by the two sub-pixels are the same. Thus it is necessary for the specialized image processing system to process the image data signals so that it may be inconvenient to convert between the 3D display effect and the 2D display effect.
Technical solutions of the invention will be described below by way of particular embodiments, and it shall be noted that:
1. In the course of scanning each frame in a gate drive circuit, it is typically necessary to perform pre-scan resetting and post-scan zeroing on each level of shift register (all the levels of shift registers include all the first to eighth shift registers). The pre-scan resetting refers to pulling the potential at the output terminal of the shift register down to a low potential to thereby zero out the shift register, that is, the pre-scan resetting ensures that the potential at the output terminal of the shift register is the low potential until the level of shift register is scanned, so that the quality of the display image can be ensured. The zeroing refers to pulling the potential at the output terminal of the shift register down to the low potential after the shift register is scanned, that is, after the shift register outputs a gate drive signal, to thereby ensure the shift register to be maintained at the low potential after being scanned so as to avoid interference to the image display and prepare for next scanning
2. Both a first gate drive circuit and a second gate drive circuit are applicable to forward scanning and backward scanning, and for the sake of the convenient description, both the first gate drive circuit and the second gate drive circuit adopt the forward scanning by way of an example in an embodiment, but the embodiment of the invention will not be limited thereto. In this embodiment, a first transistor T1 to a ninth transistor T9 are NMOS transistors, but the first transistor T1 to the ninth transistor T9 can alternatively be PMOS transistors in another embodiment, and the embodiment of the invention will not be limited thereto.
3. In an embodiment of the invention, a TFT array substrate will not be limited to a TFT array substrate for a Liquid Crystal Display (LCD), a TFT array substrate for an Organic Light Emitting Display (OLED), or a TFT array substrate for an electronic paper or the like. Additionally in the embodiment of the invention, the TFT array substrate will not be limited to an amorphous silicon TFT array substrate, an LTPS TFT array substrate or an oxide TFT array substrate.
4. In an embodiment of the invention, first to eighth start transistors, first to sixteenth clock transistors and first to second pre-scan reset transistors will not be limited to N-type transistors or P-type transistors. In the following respective embodiments and respective drawings, the first to eighth start transistors, the first to sixteenth clock transistors and the first to second pre-scan reset transistors will be described as N-type transistors only by way of an example for the sake of the convenient description.
5. In an embodiment of the invention, the internal circuit structures and drive operating processes of first to eighth shift registers, voltage ranges of first to sixteenth clock signals, voltage ranges of first to eighth start signals, waveforms of the first to sixteenth clock signals, and voltage ranges and waveforms of first to second pre-scan reset signals are all well known in the art, so the repeated description thereof will be omitted in the embodiment.
6. An embodiment of the invention will not limit voltage ranges of a first control line and a second control line as long as such a condition is satisfied that in 2D display, the first control line controls the first start transistor, the third start transistor, the fifth start transistor, the seventh start transistor, the first clock transistor, the third clock transistor, the fifth clock transistor, the seventh clock transistor, the ninth clock transistor, the eleventh clock transistor, the thirteenth clock transistor, the fifteenth clock transistor and the first transistor to be turned off, and the second control line controls the second start transistor, the fourth start transistor, the sixth start transistor, the eighth start transistor, the second clock transistor, the fourth clock transistor, the sixth clock transistor, the eighth clock transistor, the tenth clock transistor, the twelfth clock transistor, the fourteenth clock transistor, the sixteenth clock transistor and the second transistor to be turned on; and in 3D display, the first control line controls the first start transistor, the third start transistor, the fifth start transistor, the seventh start transistor, the first clock transistor, the third clock transistor, the fifth clock transistor, the seventh clock transistor, the ninth clock transistor, the eleventh clock transistor, the thirteenth clock transistor, the fifteenth clock transistor and the first transistor to be turned on, and the second control line controls the second start transistor, the fourth start transistor, the sixth start transistor, the eighth start transistor, the second clock transistor, the fourth clock transistor, the sixth clock transistor, the eighth clock transistor, the tenth clock transistor, the twelfth clock transistor, the fourteenth clock transistor, the sixteenth clock transistor and the second transistor to be turned off
7. In the following embodiments, the first to eighth start switches, the first to second signal switches, and the first to sixteenth clock switches are typically transistors, where respective gates are connected correspondingly with the first switch line W1 and the second switch line W2, and turned on and off according to the timings of W1 and W2 in
Technical solutions of the invention will be described below in connection with the particular embodiments:
As illustrated in
As illustrated in
The second gate drive circuit 102 includes n levels of second repeat units B (the n levels of second repeat units B are B1 to Bn respectively), where each level of second repeat unit B includes a second shift register SR2 including a second input terminal IN2 and a second output terminal OUT2 connected with the corresponding gate line.
The TFT array substrate 100 further includes a first start transistor K1 and a second start transistor K2.
The drain of the first start transistor K1 is electrically connected with the first start signal line S1, the source S thereof is electrically connected with the first input terminal IN1 of the first shift register SR1 of the first level of first repeat unit A1, and the gate thereof is electrically connected with a first control line SW1.
Among the second to m-th levels of first repeat units A, the first input terminal IN1 of the first shift register SR1 in the i-th level of first repeat unit A is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the (i−1)-th level of first repeat unit A, for example, the first input terminal IN1 of the first shift register SR1 in the second level of first repeat unit A2 is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the first level of first repeat unit A1.
The drain of the second start transistor K2 is electrically connected with the first start signal line S1, the source S thereof is electrically connected with the second input terminal IN2 of the second shift register SR2 of the first level of second repeat unit B1, and the gate thereof is electrically connected with a second control line SW2.
Among the second to n-th levels of second repeat units B, the second input terminal IN2 of the second shift register SR2 in the i-th level of second repeat unit B is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the (i−1)-th level of second repeat unit B, for example, the second input terminal IN2 of the second shift register SR2 in the second level of second repeat unit B2 is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the first level of second repeat unit B1.
A frame includes a first period of time P1 and a second period of time P2.
In 2D display, during both the first period of time P1 and the second period of time P2, the first control line SW1 controls the first start transistor K1 to be turned on, and the second control line SW2 controls the second start transistor K2 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the first start transistor K1 to be turned on, and the second control line SW2 controls the second start transistor K2 to be turned off; and during the second period of time P2, the first control line SW1 controls the first start transistor K1 to be turned off, and the second control line SW2 controls the second start transistor K2 to be turned on.
Here all of m, n and i are positive integers, and i is larger than or equal to 2 and smaller than or equal to m and/or n.
The first shift register SR1 further includes a first zeroing terminal R1, and the second shift register SR2 further includes a second zeroing terminal R2.
Among the first to (m−1)-th levels of first repeat units A, the first zeroing terminal R1 of the first shift register SR1 in the k-th level of first repeat unit A is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the (k+1)-th level of first repeat unit A, for example, the first zeroing terminal R1 of the first shift register SR1 in the first level of first repeat unit A1 is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the second level of first repeat unit A2; and
Among the first to (n−1)-th levels of second repeat units B, the second zeroing terminal R2 of the second shift register SR2 in the k-th level of second repeat unit B is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the (k+1)-th level of second repeat unit B, for example, the second zeroing terminal R2 of the second shift register SR2 in the first level of second repeat unit B1 is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the second level of second repeat unit B2, where K is a positive integer, and 1<<k<<m−1 and 1<<k<<n−1.
With the TFT array substrate according to the embodiment of the invention, in 2D display, during the first period of time and the second period of time, the first control line controls the first start transistor to be turned on, and the second control line controls the second start transistor to be turned on; and in 3D display, during the first period of time, the first control line controls the first start transistor to be turned on, and the second control line controls the second start transistor to be turned off, and during the second period of time, the first control line controls the first start transistor to be turned off, and the second control line controls the second start transistor to be turned on, so that the convenient and rapid conversion between the 2D display effect and the 3D display effect of the display device can be achieved.
The invention further provides a second embodiment as illustrated in
The first input terminal IN1 of the first shift register SR1 in the first level of first repeat unit A1 is further electrically connected with the low level signal line VGL through the first start switch SWT1; and
The second input terminal IN2 of the second shift register SR2 in the first level of second repeat unit B1 is further electrically connected with the low level signal line VGL through the second start switch SWT2.
In 2D display, during the first period of time P1 and the second period of time P2, the first start switch SWT1 and the second start switch SWT2 are turned off; and
In 3D display, during the first period of time P1, the first start switch SWT1 is turned off, and the second start switch SWT2 is turned on; and during the second period of time P2, the first start switch SWT1 is turned on, and the second start switch SWT2 is turned off
With the TFT array substrate, the display panel and the display device according to the embodiments of the invention, in 2D display, during the first period of time and the second period of time, the first control line controls the first start transistor to be turned on, and the second control line controls the second start transistor to be turned on; and in 3D display, during the first period of time, the first control line controls the first start transistor to be turned on, and the second control line controls the second start transistor to be turned off, and during the second period of time, the first control line controls the first start transistor to be turned off, and the second control line controls the second start transistor to be turned on, so that the convenient and rapid conversion between the 2D display effect and the 3D display effect of the display device can be achieved.
In 2D display, during the first period of time P1 and the second period of time P2, the first start switch SWT1 and the second start switch SWT2 are turned off so that the adverse influence due to leakage current of the respective transistors can be prevented to improve the performance of the TFT array substrate.
In 3D display, during the first period of time P1, the first start switch SWT1 is turned off and the second start switch SWT2 is turned on so that the adverse influence due to leakage current of the respective transistors connected with the first start switch SWT1 can be prevented to improve the performance of the TFT array substrate; and during the second period of time P2, the first start switch SWT1 is turned on and the second start switch SWT2 is turned off so that the adverse influence due to leakage current of the respective transistors connected with the second start switch SWT2 can be prevented to improve the performance of the TFT array substrate.
The invention further provides a third embodiment as illustrated in
In each level of first repeat unit A, the drain of the first clock transistor T1 is electrically connected with the first clock signal line C1, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the first clock signal terminal CK1; and the drain of the third clock transistor T3 is electrically connected with the second clock signal line C2, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the third clock signal terminal CK3; and
In each level of second repeat unit B, the drain of the second clock transistor T2 is electrically connected with the first clock signal line C1, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the second clock signal terminal CK2; and the drain of the fourth clock transistor T4 is electrically connected with the second clock signal line C2, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the fourth clock signal terminal CK4.
In 2D display, during the first period of time P1 and the second period of time P2, the first control line SW1 controls the first clock transistor T1 and the third clock transistor T3 to be turned on, and the second control line SW2 controls the second clock transistor T2 and the fourth clock transistor T4 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the first clock transistor T1 and the third clock transistor T3 to be turned on, and the second control line SW2 controls the second clock transistor T2 and the fourth clock transistor T4 to be turned off; and during the second period of time P2, the first control line SW1 controls the first clock transistor T1 and the third clock transistor T3 to be turned off, and the second control line SW2 controls the second clock transistor T2 and the fourth clock transistor T4 to be turned on.
Furthermore the TFT array substrate 100 further includes a first signal line RS, a first transistor RT1 and a second transistor RT2; the first shift register SR1 further includes a first terminal RST1; and the second shift register SR2 further includes a second terminal RST2.
In each level of first repeat unit A, the drain of the first transistor RT1 is electrically connected with the first signal line RS, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the first terminal RST1; and
In each level of second repeat unit B, the drain of the second transistor RT2 is electrically connected with the first signal line RS, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the second terminal RST2.
In 2D display, during the first period of time P1 and the second period of time P2, the first control line SW1 controls the first transistor RT1 to be turned on, and the second control line SW2 controls the second transistor RT2 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the first transistor RT1 to be turned on, and the second control line SW2 controls the second transistor RT2 to be turned off; and during the second period of time P2, the first control line SW1 controls the first transistor RT1 to be turned off, and the second control line SW2 controls the second transistor RT2 to be turned on.
It shall be noted that the first signal line RS can output a pre-scan rest signal; or the first signal line RS can output a constant high level signal; or the first signal line RS can output a constant low level signal; or the first signal line RS can output a forward scan signal; or the first signal line RS can output a backward scan signal.
The invention further provides a fourth embodiment as illustrated in
The first clock signal terminal CK1 of the first shift register SR1 in the first level of first repeat unit A1 is further electrically connected with the low level signal line VGL through the first clock switch CWT1, and the third clock signal terminal CK3 of the first shift register SR1 in the first level of first repeat unit A1 is further electrically connected with the low level signal line VGL through the third clock switch CWT3.
The second clock signal terminal CK2 of the second shift register SR2 in the first level of second repeat unit B1 is further electrically connected with the low level signal line VGL through the second clock switch CWT2, and the fourth clock signal terminal CK4 of the second shift register SR2 in the first level of second repeat unit B1 is further electrically connected with the low level signal line VGL through the fourth clock switch CWT4.
In 2D display, during the first period of time P1 and the second period of time P2, the first clock switch CWT1, the second clock switch CWT2, and the third clock switch CWT3 and the fourth clock switch CWT4 are turned off; and
In 3D display, during the first period of time P1, the first clock switch CWT1 and the third clock switch CWT3 are turned off, and the second clock switch CWT2 and the fourth clock switch CWT4 are turned on; and during the second period of time P2, the first clock switch CWT1 and the third clock switch CWT3 are turned on, and the second clock switch CWT2 and the fourth clock switch CWT4 are turned off.
Furthermore the TFT array substrate 100 further includes a low level signal line VGL, a first signal switch RWT1 and a second signal switch RWT2.
The first terminal RST1 of the first shift register SR1 in the first level of first repeat unit A1 is further electrically connected with the low level signal line VGL through the first signal switch RWT1; and
The second terminal RST2 of the second shift register SR2 in the first level of second repeat unit B1 is further electrically connected with the low level signal line VGL through the second signal switch RWT2.
In 2D display, during the first period of time P1 and the second period of time P2, the first signal switch RWT1 and the second signal switch RWT2 are turned off; and
In 3D display, during the first period of time P1, the first signal switch RWT1 is turned off, and the second signal switch RWT2 is turned on; and during the second period of time P2, the first signal switch RWT1 is turned on, and the second signal switch RWT2 is turned off
In 2D display, during the first period of time P1 and the second period of time P2, the first signal switch RWT1 and the second signal switch RWT2 are turned off so that the adverse influence due to leakage current of the respective transistors can be prevented to improve the performance of the TFT array substrate.
In 3D display, during the first period of time P1, the first signal switch RWT1 is turned off and the second signal switch RWT2 is turned on so that the adverse influence due to leakage current of the respective transistors connected with the first signal switch RWT1 can be prevented to improve the performance of the TFT array substrate; and during the second period of time P2, the first signal switch RWT1 is turned on and the second signal switch RWT2 is turned off so that the adverse influence due to leakage current of the respective transistors connected with the second signal switch RWT2 can be prevented to improve the performance of the TFT array substrate.
The invention further provides a fifth embodiment as illustrated in
Each level of first repeat unit A further includes a third shift register SR3 including a third input terminal IN3 and a third output terminal OUT3 connected with the corresponding gate line; and
Each level of second repeat unit B further includes a fourth shift register SR4 including a fourth input terminal IN4 and a fourth output terminal OUT4 connected with the corresponding gate line.
The TFT array substrate 100 further includes a third start transistor K3 and a fourth start transistor K4.
The drain of the third start transistor K3 is electrically connected with the second start signal line S2, the source S thereof is electrically connected with the third input terminal IN3 of the third shift register SR3 in the first level of first repeat unit A1, and the gate thereof is electrically connected with the first control line SW1;
Among the second to m-th levels of first repeat units A, the first input terminal IN1 of the first shift register SR1 in the i-th level of first repeat unit A is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the (i−1)-th level of first repeat unit A, and the third input terminal IN3 of the third shift register SR3 in the i-th level of first repeat unit A is electrically connected with the third output terminal OUT3 of the third shift register SR3 in the (i−1)-th level of first repeat unit A, for example, the first input terminal IN1 of the first shift register SR1 in the second level of first repeat unit A2 is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the first level of first repeat unit A1, and the third input terminal IN3 of the third shift register SR3 in the second level of first repeat unit A2 is electrically connected with the third output terminal OUT3 of the third shift register SR3 in the first level of first repeat unit Al; and
The drain of the fourth start transistor K4 is electrically connected with the second start signal line S2, the source S thereof is electrically connected with the fourth input terminal IN4 of the fourth shift register SR4 of the first level of second repeat unit B1, and the gate thereof is electrically connected with the second control line SW2;
Among the second to n-th levels of second repeat units B, the second input terminal IN2 of the second shift register SR2 in the i-th level of second repeat unit B is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the (i−1)-th level of second repeat unit B, and the fourth input terminal IN4 of the fourth shift register SR4 in the i-th level of second repeat unit B is electrically connected with the fourth output terminal OUT4 of the fourth shift register SR4 in the (i−1)-th level of second repeat unit B, for example, the second input terminal IN2 of the second shift register SR2 in the second level of second repeat unit B2 is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the first level of second repeat unit B 1, and the fourth input terminal IN4 of the fourth shift register SR4 in the second level of second repeat unit B2 is electrically connected with the fourth output terminal OUT4 of the fourth shift register SR4 in the first level of second repeat unit B1.
In 2D display, during the first period of time P1 and the second period of time P2, the first control line SW1 controls the third start transistor K3 to be turned on, and the second control line SW2 controls the fourth start transistor K4 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the third start transistor K3 to be turned on, and the second control line SW2 controls the fourth start transistor K4 to be turned off; and during the second period of time P2, the first control line SW1 controls the third start transistor K3 to be turned off, and the second control line SW2 controls the fourth start transistor K4 to be turned on.
Furthermore the first shift register SR1 further includes a first zeroing terminal R1, the second shift register SR2 further includes a second zeroing terminal R2, the third shift register SR3 further includes a third zeroing terminal R3, and the fourth shift register SR4 further includes a fourth zeroing terminal R4.
Among the first to (m−1)-th levels of first repeat units A, the first zeroing terminal R1 of the first shift register SR1 in the k-th level of first repeat unit A is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the (k+1)-th level of first repeat unit A, and the third zeroing terminal R3 of the third shift register SR3 in the k-th level of first repeat unit A is electrically connected with the third output terminal OUT3 of the third shift register SR3 in the (k+1)-th level of first repeat unit A, for example, the first zeroing terminal R1 of the first shift register SR1 in the first level of first repeat unit A1 is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the second level of first repeat unit A2, and the third zeroing terminal R3 of the third shift register SR3 in the first level of first repeat unit A1 is electrically connected with the third output terminal OUT3 of the third shift register SR3 in the second level of first repeat unit A2; and
Among the first to (n−1)-th levels of second repeat units B, the second zeroing terminal R2 of the second shift register SR2 in the k-th level of second repeat unit B is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the (k+1)-th level of second repeat unit B, and the fourth zeroing terminal R4 of the fourth shift register SR4 in the k-th level of second repeat unit B is electrically connected with the fourth output terminal OUT4 of the fourth shift register SR4 in the (k+1)-th level of second repeat unit B, for example, the second zeroing terminal R2 of the second shift register SR2 in the first level of second repeat unit B1 is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the second level of second repeat unit B2, and the fourth zeroing terminal R4 of the fourth shift register SR4 in the first level of second repeat unit B1 is electrically connected with the fourth output terminal OUT4 of the fourth shift register SR4 in the second level of second repeat unit B2, where K is a positive integer, and 1<<k<<m−1 and 1<<k<<n−1.
The invention further provides a sixth embodiment as illustrated in
In the first level of first repeat unit A1, the first input terminal IN1 of the first shift register SR1 is further electrically connected with the low level signal line VGL through the first start switch SWT1, and the third input terminal IN3 of the third shift register SR3 is further electrically connected with the low level signal line VGL through the third start switch SWT3; and
In the first level of second repeat unit B1, the second input terminal IN2 of the second shift register SR2 is further electrically connected with the low level signal line VGL through the second start switch SWT2, and the fourth input terminal IN4 of the fourth shift register SR4 is further electrically connected with the low level signal line VGL through the fourth start switch SWT4.
In 2D display, during the first period of time P1 and the second period of time P2, the first start switch SWT1, the second start switch SWT2, the third start switch SWT3 and the fourth start switch SWT4 are turned off; and
In 3D display, during the first period of time P1, the first start switch SWT1 and the third start switch SWT3 are turned off, and the second start switch SWT2 and the fourth start switch SWT4 are turned on; and during the second period of time P2, the first start switch SWT1 and the third start switch SWT3 are turned on, and the second start switch SWT2 and the fourth start switch SWT4 are turned off.
The invention further provides a seventh embodiment as illustrated in
In each level of first repeat unit A, the drain of the first clock transistor T1 is electrically connected with the first clock signal line C1, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the first clock signal terminal CK1; the drain of the third clock transistor T3 is electrically connected with the second clock signal line C2, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the third clock signal terminal CK3; the drain of the fifth clock transistor T5 is electrically connected with the third clock signal line C3, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the fifth clock signal terminal CK5; and the drain of the seventh clock transistor T7 is electrically connected with the fourth clock signal line C4, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the seventh clock signal terminal CK7; and
In each level of second repeat unit B, the drain of the second clock transistor T2 is electrically connected with the first clock signal line C1, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the second clock signal terminal CK2; the drain of the fourth clock transistor T4 is electrically connected with the second clock signal line C2, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the fourth clock signal terminal CK4; the drain of the sixth clock transistor T6 is electrically connected with the third clock signal line C3, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the sixth clock signal terminal CK6; and the drain of the eighth clock transistor T8 is electrically connected with the fourth clock signal line C4, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the eighth clock signal terminal CK8.
In 2D display, during the first period of time P1 and the second period of time P2, the first control line SW1 controls the first clock transistor T1, the third clock transistor T3, the fifth clock transistor T5 and the seventh clock transistor T7 to be turned on, and the second control line SW2 controls the second clock transistor T2, the fourth clock transistor T4, the sixth clock transistor T6 and the eighth clock transistor T8 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the first clock transistor T1, the third clock transistor T3, the fifth clock transistor T5 and the seventh clock transistor T7 to be turned on, and the second control line SW2 controls the second clock transistor T2, the fourth clock transistor T4, the sixth clock transistor T6 and the eighth clock transistor T8 to be turned off; and during the second period of time P2, the first control line SW1 controls the first clock transistor T1, the third clock transistor T3, the fifth clock transistor T5 and the seventh clock transistor T7 to be turned off, and the second control line SW2 controls the second clock transistor T2, the fourth clock transistor T4, the sixth clock transistor T6 and the eighth clock transistor T8 to be turned on.
Furthermore the TFT array substrate 100 further includes a first signal line RS, a first transistor RT1 and a second transistor RT2; each of the first shift register SR1 and the third shift register SR3 further includes a first terminal RST1; and each of the second shift register SR2 and the fourth shift register SR4 further includes a second terminal RST2.
In each level of first repeat unit A, the drain of the first transistor RT1 is electrically connected with the first signal line RS, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the first terminal RST1; and
In each level of second repeat unit B, the drain of the second transistor RT2 is electrically connected with the first signal line RS, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the second terminal RST2.
In 2D display, during the first period of time P1 and the second period of time P2, the first control line SW1 controls the first transistor RT1 to be turned on, and the second control line SW2 controls the second transistor RT2 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the first transistor RT1 to be turned on, and the second control line SW2 controls the second transistor RT2 to be turned off; and during the second period of time P2, the first control line SW1 controls the first transistor RT1 to be turned off, and the second control line SW2 controls the second transistor RT2 to be turned on.
It shall be noted that the first signal line RS can output a pre-scan rest signal; or the first signal line RS can output a constant high level signal; or the first signal line RS can output a constant low level signal; or the first signal line RS can output a forward scan signal; or the first signal line RS can output a backward scan signal.
The invention further provides an eighth embodiment as illustrated in
In the first level of first repeat unit A1, the first clock signal terminal CK1 of the first shift register SR1 is further electrically connected with the low level signal line VGL through the first clock switch CWT1, the third clock signal terminal CK3 of the first shift register SR1 is further electrically connected with the low level signal line VGL through the third clock switch CWT3, the fifth clock signal terminal CK5 of the third shift register SR3 is further electrically connected with the low level signal line VGL through the fifth clock switch CWT5, and the seventh clock signal terminal CK7 of the third shift register SR3 is further electrically connected with the low level signal line VGL through the seventh clock switch CWT7; and
In the first level of second repeat unit B1, the second clock signal terminal CK2 of the second shift register SR2 is further electrically connected with the low level signal line VGL through the second clock switch CWT2, the fourth clock signal terminal CK4 of the second shift register SR2 is further electrically connected with the low level signal line VGL through the fourth clock switch CWT4, the sixth clock signal terminal CK6 of the fourth shift register SR4 is further electrically connected with the low level signal line VGL through the sixth clock switch CWT6, and the eighth clock signal terminal CK8 of the fourth shift register SR4 is further electrically connected with the low level signal line VGL through the eighth clock switch CWT8.
In 2D display, during the first period of time P1 and the second period of time P2, the first clock switch CWT1, the second clock switch CWT2, the third clock switch CWT3, the fourth clock switch CWT4, the fifth clock switch CWT5, the sixth clock switch CWT6, the seventh clock switch CWT7 and the eighth clock switch CWT8 are turned off; and
In 3D display, during the first period of time P1, the first clock switch CWT1, the third clock switch CWT3, the fifth clock switch CWT5 and the seventh clock switch CWT7 are turned off, and the second clock switch CWT2, the fourth clock switch CWT4, the sixth clock switch CWT6 and the eighth clock switch CWT8 are turned on; and during the second period of time P2, the first clock switch CWT1, the third clock switch CWT3, the fifth clock switch CWT5 and the seventh clock switch CWT7 are turned on, and the second clock switch CWT2, the fourth clock switch CWT4, the sixth clock switch CWT6 and the eighth clock switch CWT8 are turned off.
Furthermore the TFT array substrate 100 further includes a low level signal line VGL, a first signal switch RWT1 and a second signal switch RWT2.
The first terminal RST1 of the first shift register SR1 in the first level of first repeat unit A1 is further electrically connected with the low level signal line VGL through the first signal switch RWT1; and
The second terminal RST2 of the second shift register SR2 in the first level of second repeat unit B1 is further electrically connected with the low level signal line VGL through the second signal switch RWT2.
In 2D display, during the first period of time P1 and the second period of time P2, the first signal switch RWT1 and the second signal switch RWT2 are turned off; and
In 3D display, during the first period of time P1, the first signal switch RWT1 is turned off, and the second signal switch RWT2 is turned on; and during the second period of time P2, the first signal switch RWT1 is turned on, and the second signal switch RWT2 is turned off
The invention further provides a ninth embodiment as illustrated in
Each level of first repeat unit A further includes a fifth shift register SR5 and a seventh shift register SR7, where the fifth shift register SR5 includes a fifth input terminal IN5 and a fifth output terminal OUTS connected with the corresponding gate line, and the seventh shift register SR7 includes a seventh input terminal IN7 and a seventh output terminal OUT7 connected with the corresponding gate line; and
Each level of second repeat unit B further includes a sixth shift register SR6 and an eighth shift register SR8, where the sixth shift register SR6 includes a sixth input terminal IN6 and a sixth output terminal OUT6 connected with the corresponding gate line, and the eighth shift register SR8 includes an eighth input terminal IN8 and an eighth output terminal OUT8 connected with the corresponding gate line.
The TFT array substrate 100 further includes a fifth start transistor K5, a sixth start transistor K6, a seventh start transistor K7 and an eighth start transistor K8.
The drain of the fifth start transistor K5 is electrically connected with the third start signal line S3, the source S thereof is electrically connected with the fifth input terminal IN5 of the fifth shift register SR5 in the first level of first repeat unit A1, and the gate thereof is electrically connected with the first control line SW1;
The drain of the sixth start transistor K6 is electrically connected with the third start signal line S3, the source S thereof is electrically connected with the sixth input terminal IN6 of the sixth shift register SR6 in the first level of second repeat unit B1, and the gate thereof is electrically connected with the second control line SW2;
The drain of the seventh start transistor K7 is electrically connected with the fourth start signal line S4, the source S thereof is electrically connected with the seventh input terminal IN7 of the seventh shift register SR7 in the first level of first repeat unit A1, and the gate thereof is electrically connected with the first control line SW1; and
The drain of the eighth start transistor K8 is electrically connected with the fourth start signal line S4, the source S thereof is electrically connected with the eighth input terminal IN8 of the eighth shift register SR8 in the first level of second repeat unit B1, and the gate thereof is electrically connected with the second control line SW2.
Among the second to m-th levels of first repeat units A, the first input terminal IN1 of the first shift register SR1 in the i-th level of first repeat unit A is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the (i−1)-th level of first repeat unit A, the third input terminal IN3 of the third shift register SR3 in the i-th level of first repeat unit A is electrically connected with the third output terminal OUT3 of the third shift register SR3 in the (i−1)-th level of first repeat unit A, the fifth input terminal IN5 of the fifth shift register SR5 in the i-th level of first repeat unit A is electrically connected with the fifth output terminal OUTS of the fifth shift register SR5 in the (i−1)-th level of first repeat unit A, and the seventh input terminal IN7 of the seventh shift register SR7 in the i-th level of first repeat unit A is electrically connected with the seventh output terminal OUT7 of the seventh shift register SR7 in the (i−1)-th level of first repeat unit A, for example, the first input terminal IN1 of the first shift register SR1 in the second level of first repeat unit A2 is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the first level of first repeat unit A1, the third input terminal IN3 of the third shift register SR3 in the second level of first repeat unit A2 is electrically connected with the third output terminal OUT3 of the third shift register SR3 in the first level of first repeat unit A1, the fifth input terminal IN5 of the fifth shift register SR5 in the second level of first repeat unit A2 is electrically connected with the fifth output terminal OUTS of the fifth shift register SR5 in the first level of first repeat unit A1, and the seventh input terminal IN7 of the seventh shift register SR7 in the second level of first repeat unit A2 is electrically connected with the seventh output terminal OUT7 of the seventh shift register SR7 in the first level of first repeat unit A1; and
Among the second to n-th levels of second repeat units B, the second input terminal IN2 of the second shift register SR2 in the i-th level of second repeat unit B is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the (i−1)-th level of second repeat unit B, the fourth input terminal IN4 of the fourth shift register SR4 in the i-th level of second repeat unit B is electrically connected with the fourth output terminal OUT4 of the fourth shift register SR4 in the (i−1)-th level of second repeat unit B, the sixth input terminal IN6 of the sixth shift register SR6 in the i-th level of second repeat unit B is electrically connected with the sixth output terminal OUT6 of the sixth shift register SR6 in the (i−1)-th level of second repeat unit B, and the eighth input terminal IN8 of the eighth shift register SR8 in the i-th level of second repeat unit B is electrically connected with the eighth output terminal OUT8 of the eighth shift register SR8 in the (i−1)-th level of second repeat unit B, for example, the second input terminal IN2 of the second shift register SR2 in the second level of second repeat unit B2 is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the first level of second repeat unit B1, the fourth input terminal IN4 of the fourth shift register SR4 in the second level of second repeat unit B2 is electrically connected with the fourth output terminal OUT4 of the fourth shift register SR4 in the first level of second repeat unit B1, the sixth input terminal IN6 of the sixth shift register SR6 in the second level of second repeat unit B2 is electrically connected with the sixth output terminal OUT6 of the sixth shift register SR6 in the first level of second repeat unit B1, and the eighth input terminal IN8 of the eighth shift register SR8 in the second level of second repeat unit B2 is electrically connected with the eighth output terminal OUT8 of the eighth shift register SR8 in the first level of second repeat unit B1.
In 2D display, during the first period of time P1 and the second period of time P2, the first control line SW1 controls the fifth start transistor K5 and the seventh start transistor K7 to be turned on, and the second control line SW2 controls the sixth start transistor K6 and the eighth start transistor K8 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the fifth start transistor K5 and the seventh start transistor K7 to be turned on, and the second control line SW2 controls the sixth start transistor K6 and the eighth start transistor K8 to be turned off; and during the second period of time P2, the first control line SW1 controls the fifth start transistor K5 and the seventh start transistor K7 to be turned off, and the second control line SW2 controls the sixth start transistor K6 and the eighth start transistor K8 to be turned on.
Furthermore the first shift register SR1 further includes a first zeroing terminal R1, the second shift register SR2 further includes a second zeroing terminal R2, the third shift register SR3 further includes a third zeroing terminal R3, the fourth shift register SR4 further includes a fourth zeroing terminal R4, the fifth shift register SR5 further includes a fifth zeroing terminal R5, the sixth shift register SR6 further includes a sixth zeroing terminal R6, the seventh shift register SR7 further includes a seventh zeroing terminal R7, and the eighth shift register SR8 further includes an eighth zeroing terminal R8.
Among the first to (m−1)-th levels of first repeat units A, the first zeroing terminal R1 of the first shift register SR1 in the k-th level of first repeat unit A is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the (k+1)-th level of first repeat unit A, the third zeroing terminal R3 of the third shift register SR3 in the k-th level of first repeat unit A is electrically connected with the third output terminal OUT3 of the third shift register SR3 in the (k+1)-th level of first repeat unit A, the fifth zeroing terminal R5 of the fifth shift register SR5 in the k-th level of first repeat unit A is electrically connected with the fifth output terminal OUTS of the fifth shift register SR5 in the (k+1)-th level of first repeat unit A, and the seventh zeroing terminal R7 of the seventh shift register SR7 in the k-th level of first repeat unit A is electrically connected with the seventh output terminal OUT7 of the seventh shift register SR7 in the (k+1)-th level of first repeat unit A, for example, the first zeroing terminal R1 of the first shift register SR1 in the first level of first repeat unit A1 is electrically connected with the first output terminal OUT1 of the first shift register SR1 in the second level of first repeat unit A2, the third zeroing terminal R3 of the third shift register SR3 in the first level of first repeat unit A1 is electrically connected with the third output terminal OUT3 of the third shift register SR3 in the second level of first repeat unit A2, the fifth zeroing terminal R5 of the fifth shift register SR5 in the first level of first repeat unit A1 is electrically connected with the fifth output terminal OUTS of the fifth shift register SR5 in the second level of first repeat unit A2, and the seventh zeroing terminal R7 of the seventh shift register SR7 in the first level of first repeat unit A1 is electrically connected with the seventh output terminal OUT7 of the seventh shift register SR7 in the second level of first repeat unit A2; and
Among the first to (n−1)-th levels of second repeat units B, the second zeroing terminal R2 of the second shift register SR2 in the k-th level of second repeat unit B is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the (k+1)-th level of second repeat unit B, the fourth zeroing terminal R4 of the fourth shift register SR4 in the k-th level of second repeat unit B is electrically connected with the fourth output terminal OUT4 of the fourth shift register SR4 in the (k+1)-th level of second repeat unit B, the sixth zeroing terminal R6 of the sixth shift register SR6 in the k-th level of second repeat unit B is electrically connected with the sixth output terminal OUT6 of the sixth shift register SR6 in the (k+1)-th level of second repeat unit B, and the eighth zeroing terminal R8 of the eighth shift register SR8 in the k-th level of second repeat unit B is electrically connected with the eighth output terminal OUT8 of the eighth shift register SR8 in the (k+1)-th level of second repeat unit B, for example, the second zeroing terminal R2 of the second shift register SR2 in the first level of second repeat unit B1 is electrically connected with the second output terminal OUT2 of the second shift register SR2 in the second level of second repeat unit B2, the fourth zeroing terminal R4 of the fourth shift register SR4 in the first level of second repeat unit B1 is electrically connected with the fourth output terminal OUT4 of the fourth shift register SR4 in the second level of second repeat unit B2, the sixth zeroing terminal R6 of the sixth shift register SR6 in the first level of second repeat unit B1 is electrically connected with the sixth output terminal OUT6 of the sixth shift register SR6 in the second level of second repeat unit B2, and the eighth zeroing terminal R8 of the eighth shift register SR8 in the first level of second repeat unit B1 is electrically connected with the eighth output terminal OUT8 of the eighth shift register SR8 in the second level of second repeat unit B2, where K is a positive integer, and 1<<k<<m−1 and 1<<k<<n−1.
The invention further provides a tenth embodiment as illustrated in
In the first level of first repeat unit A1, the first input terminal IN1 of the first shift register SR1 is further electrically connected with the low level signal line VGL through the first start switch SWT1, the third input terminal IN3 of the third shift register SR3 is further electrically connected with the low level signal line VGL through the third start switch SWT3, the fifth input terminal IN5 of the fifth shift register SR5 is further electrically connected with the low level signal line VGL through the fifth start switch SWT5, and the seventh input terminal IN7 of the seventh shift register SR7 is further electrically connected with the low level signal line VGL through the seventh start switch SWT7; and
In the first level of second repeat unit B1, the second input terminal IN2 of the second shift register SR2 is further electrically connected with the low level signal line VGL through the second start switch SWT2, the fourth input terminal IN4 of the fourth shift register SR4 is further electrically connected with the low level signal line VGL through the fourth start switch SWT4, the sixth input terminal IN6 of the sixth shift register SR6 is further electrically connected with the low level signal line VGL through the sixth start switch SWT6, and the eighth input terminal IN8 of the eighth shift register SR8 is further electrically connected with the low level signal line VGL through the eighth start switch SWT8.
In 2D display, during the first period of time P1 and the second period of time P2, the first start switch SWT1, the second start switch SWT2, the third start switch SWT3, the fourth start switch SWT4, the fifth start switch SWT5, the sixth start switch SWT6, the seventh start switch SWT7 and the eighth start switch SWT8 are all turned off; and
In 3D display, during the first period of time P1, the first start switch SWT1, the third start switch SWT3, the fifth start switch SWT5 and the seventh start switch SWT7 are turned off, and the second start switch SWT2, the fourth start switch SWT4, the sixth start switch SWT6 and the eighth start switch SWT8 are turned on; and during the second period of time P2, the first start switch SWT1, the third start switch SWT3, the fifth start switch SWT5 and the seventh start switch SWT7 are turned on, and the second start switch SWT2, the fourth start switch SWT4, the sixth start switch SWT6 and the eighth start switch SWT8 are turned off
The invention further provides an eleventh embodiment as illustrated in
In each level of first repeat unit A, the drain of the first clock transistor T1 is electrically connected with the first clock signal line C1, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the first clock signal terminal CK1; the drain of the third clock transistor T3 is electrically connected with the second clock signal line C2, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the third clock signal terminal CK3; the drain of the fifth clock transistor T5 is electrically connected with the third clock signal line C3, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the fifth clock signal terminal CK5; the drain of the seventh clock transistor T7 is electrically connected with the fourth clock signal line C4, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the seventh clock signal terminal CK7; the drain of the ninth clock transistor T9 is electrically connected with the fifth clock signal line C5, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the ninth clock signal terminal CK9; the drain of the eleventh clock transistor T11 is electrically connected with the sixth clock signal line C6, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the eleventh clock signal terminal CK11; the drain of the thirteenth clock transistor T13 is electrically connected with the seventh clock signal line C7, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the thirteenth clock signal terminal CK13; and the drain of the fifteenth clock transistor T15 is electrically connected with the eighth clock signal line C8, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the fifteenth clock signal terminal CK15; and
In each level of second repeat unit B, the drain of the second clock transistor T2 is electrically connected with the first clock signal line C1, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the second clock signal terminal CK2; the drain of the fourth clock transistor T4 is electrically connected with the second clock signal line C2, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the fourth clock signal terminal CK4; the drain of the sixth clock transistor T6 is electrically connected with the third clock signal line C3, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the sixth clock signal terminal CK6; the drain of the eighth clock transistor T8 is electrically connected with the fourth clock signal line C4, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the eighth clock signal terminal CK8; the drain of the tenth clock transistor T10 is electrically connected with the fifth clock signal line C5, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the tenth clock signal terminal CK10; the drain of the twelfth clock transistor T12 is electrically connected with the sixth clock signal line C6, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the twelfth clock signal terminal CK12; the drain of the fourteenth clock transistor T14 is electrically connected with the seventh clock signal line C7, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the fourteenth clock signal terminal CK14; and the drain of the sixteenth clock transistor T16 is electrically connected with the eighth clock signal line C8, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the sixteenth clock signal terminal CK16.
In 2D display, during the first period of time P1 and the second period of time P2, the first control line SW1 controls the first clock transistor T1, the third clock transistor T3, the fifth clock transistor T5, the seventh clock transistor T7, the ninth clock transistor T9, the eleventh clock transistor T11, the thirteenth clock transistor T13 and the fifteenth clock transistor T15 to be turned on, and the second control line SW2 controls the second clock transistor T2, the fourth clock transistor T4, the sixth clock transistor T6, the eighth clock transistor T8, the tenth clock transistor T10, the twelfth clock transistor T12, the fourteenth clock transistor T14 and the sixteenth clock transistor T16 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the first clock transistor T1, the third clock transistor T3, the fifth clock transistor T5, the seventh clock transistor T7, the ninth clock transistor T9, the eleventh clock transistor T11, the thirteenth clock transistor T13 and the fifteenth clock transistor T15 to be turned on, and the second control line SW2 controls the second clock transistor T2, the fourth clock transistor T4, the sixth clock transistor T6, the eighth clock transistor T8, the tenth clock transistor T10, the twelfth clock transistor T12, the fourteenth clock transistor T14 and the sixteenth clock transistor T16 to be turned off; and during the second period of time P2, the first control line SW1 controls the first clock transistor T1, the third clock transistor T3, the fifth clock transistor T5, the seventh clock transistor T7, the ninth clock transistor T9, the eleventh clock transistor T11, the thirteenth clock transistor T13 and the fifteenth clock transistor T15 to be turned off, and the second control line SW2 controls the second clock transistor T2, the fourth clock transistor T4, the sixth clock transistor T6, the eighth clock transistor T8, the tenth clock transistor T10, the twelfth clock transistor T12, the fourteenth clock transistor T14 and the sixteenth clock transistor T16 to be turned on.
Furthermore the TFT array substrate 100 further includes a first signal line RS, a first transistor RT1 and a second transistor RT2; each of the first shift register SR1, the third shift register SR3, the fifth shift register SR5 and the seventh shift register SR7 further includes a first terminal RST1; and each of the second shift register SR2, the fourth shift register SR4, the sixth shift register SR6 and the eighth shift register SR8 further includes a second terminal RST2.
In each level of first repeat unit A, the drain of the first transistor RT1 is electrically connected with the first signal line RS, the gate thereof is electrically connected with the first control line SW1, and the source S thereof is electrically connected with the first terminal RST1; and
In each level of second repeat unit B, the drain of the second transistor RT2 is electrically connected with the first signal line RS, the gate thereof is electrically connected with the second control line SW2, and the source S thereof is electrically connected with the second terminal RST2.
In 2D display, during the first period of time P1 and the second period of time P2, the first control line SW1 controls the first transistor RT1 to be turned on, and the second control line SW2 controls the second transistor RT2 to be turned on; and
In 3D display, during the first period of time P1, the first control line SW1 controls the first transistor RT1 to be turned on, and the second control line SW2 controls the second transistor RT2 to be turned off; and during the second period of time P2, the first control line SW1 controls the first transistor RT1 to be turned off, and the second control line SW2 controls the second transistor RT2 to be turned on.
The first signal line RS can output a pre-scan rest signal; or the first signal line RS can output a constant high level signal; or the first signal line RS can output a constant low level signal; or the first signal line RS can output a forward scan signal; or the first signal line RS can output a backward scan signal.
The invention further provides a twelfth embodiment as illustrated in
In the first level of first repeat unit A1, the first clock signal terminal CK1 of the first shift register SR1 is further electrically connected with the low level signal line VGL through the first clock switch CWT1, the third clock signal terminal CK3 of the first shift register SR1 is further electrically connected with the low level signal line VGL through the third clock switch CWT3, the fifth clock signal terminal CK5 of the third shift register SR3 is further electrically connected with the low level signal line VGL through the fifth clock switch CWT5, the seventh clock signal terminal CK7 of the third shift register SR3 is further electrically connected with the low level signal line VGL through the seventh clock switch CWT7, the ninth clock signal terminal CK9 of the fifth shift register SR5 is further electrically connected with the low level signal line VGL through the ninth clock switch CWT9, the eleventh clock signal terminal CK11 of the fifth shift register SR5 is further electrically connected with the low level signal line VGL through the eleventh clock switch CWT11, the thirteenth clock signal terminal CK13 of the seventh shift register SR7 is further electrically connected with the low level signal line VGL through the thirteenth clock switch CWT13, and the fifteenth clock signal terminal CK15 of the seventh shift register SR7 is further electrically connected with the low level signal line VGL through the fifteenth clock switch CWT15; and
In the first level of second repeat unit B1, the second clock signal terminal CK2 of the second shift register SR2 is further electrically connected with the low level signal line VGL through the second clock switch CWT2, the fourth clock signal terminal CK4 of the second shift register SR2 is further electrically connected with the low level signal line VGL through the fourth clock switch CWT4, the sixth clock signal terminal CK6 of the fourth shift register SR4 is further electrically connected with the low level signal line VGL through the sixth clock switch CWT6, the eighth clock signal terminal CK8 of the fourth shift register SR4 is further electrically connected with the low level signal line VGL through the eighth clock switch CWT8, the tenth clock signal terminal CK10 of the sixth shift register SR6 is further electrically connected with the low level signal line VGL through the tenth clock switch CWT10, the twelfth clock signal terminal CK12 of the sixth shift register SR6 is further electrically connected with the low level signal line VGL through the twelfth clock switch CWT12, the fourteenth clock signal terminal CK14 of the eighth shift register SR8 is further electrically connected with the low level signal line VGL through the fourteenth clock switch CWT14, and the sixteenth clock signal terminal CK16 of the eighth shift register SR8 is further electrically connected with the low level signal line VGL through the sixteenth clock switch CWT16.
In 2D display, during the first period of time P1 and the second period of time P2, the first to sixteenth clock switches CWT1 to CWT16 are all turned off; and
In 3D display, during the first period of time P1, the first clock switch CWT1, the third clock switch CWT3, the fifth clock switch CWT5, the seventh clock switch CWT7, the ninth clock switch CWT9, the eleventh clock switch CWT11, the thirteenth clock switch CWT13 and the fifteenth clock switch CWT15 are turned off, and the second clock switch CWT2, the fourth clock switch CWT4, the sixth clock switch CWT6, the eighth clock switch CWT8, the tenth clock switch CWT10, the twelfth clock switch CWT12, the fourteenth clock switch CWT14 and the sixteenth clock switch CWT16 are turned on; and during the second period of time P2, the first clock switch CWT1, the third clock switch CWT3, the fifth clock switch CWT5, the seventh clock switch CWT7, the ninth clock switch CWT9, the eleventh clock switch CWT11, the thirteenth clock switch CWT13 and the fifteenth clock switch CWT15 are turned on, and the second clock switch CWT2, the fourth clock switch CWT4, the sixth clock switch CWT6, the eighth clock switch CWT8, the tenth clock switch CWT10, the twelfth clock switch CWT12, the fourteenth clock switch CWT14 and the sixteenth clock switch CWT16 are turned off.
Furthermore the TFT array substrate 100 further includes a first signal switch RWT1 and a second signal switch RWT2.
The first terminal RST1 of the first shift register SR1 in the first level of first repeat unit A1 is further electrically connected with the low level signal line VGL through the first signal switch RWT1; and
The second terminal RST2 of the second shift register SR2 in the first level of second repeat unit B1 is further electrically connected with the low level signal line VGL through the second signal switch RWT2.
In 2D display, during the first period of time P1 and the second period of time P2, the first signal switch RWT1 and the second signal switch RWT2 are turned off; and
In 3D display, during the first period of time P1, the first signal switch RWT1 is turned off, and the second signal switch RWT2 is turned on; and during the second period of time P2, the first signal switch RWT1 is turned on, and the second signal switch RWT2 is turned off
In summary, with the TFT array substrate, the display panel and the display device according to the embodiments of the invention, in 2D display, during the first period of time and the second period of time, the first control line controls the first start transistor to be turned on, and the second control line controls the second start transistor to be turned on; and in 3D display, during the first period of time, the first control line controls the first start transistor to be turned on, and the second control line controls the second start transistor to be turned off, and during the second period of time, the first control line controls the first start transistor to be turned off, and the second control line controls the second start transistor to be turned on, so that the convenient and rapid conversion between the 2D display effect and the 3D display effect of the display device can be achieved.
In 2D display, during the first period of time P1 and the second period of time P2, the first start switch SWT1 and the second start switch SWT2 are turned off so that the adverse influence due to leakage current of the respective transistors can be prevented to improve the performance of the TFT array substrate.
In 3D display, during the first period of time P1, the first start switch SWT1 is turned off and the second start switch SWT2 is turned on so that the adverse influence due to leakage current of the respective transistors connected with the first start switch SWT1 can be prevented to improve the performance of the TFT array substrate; and during the second period of time P2, the first start switch SWT1 is turned on and the second start switch SWT2 is turned off so that the adverse influence due to leakage current of the respective transistors connected with the second start switch SWT2 can be prevented to improve the performance of the TFT array substrate.
The foregoing disclosure is merely illustrative of preferred embodiments of the invention but not intended to limit the invention, and it can be apparent to those skilled in the art that there can be various modifications and variations to the invention. Any modifications, equivalent substitutions, adaptations, etc., made without departing from the spirit and the principle of the invention shall be encompassed in the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201410309116.3 | Jun 2014 | CN | national |
