Patent Application
20080002090
Referring to
Referring to
The first detection areas 211 and the second detection area 213 are utilized as contact points for test pins of a test instrument during a process of testing the TFT master substrate 21. In particular, each of the first detection areas 211 includes a plurality of first detection ports 2111, and the second detection area 213 includes a plurality of second detection ports 2131. Further, the first detection ports 2111 are connected in parallel to the corresponding second detection ports 2131. In the illustrated embodiment, a first one of the first detection ports 2111 of each first detection area 211 is connected with a first one of the second detection ports 2131 of the second detection area 213, a second one of the first detection ports 2111 of each first detection area 211 is connected with a second one of the second detection ports 2131 of the second detection area 213, and a third one of the first detection ports 2111 of each first detection area 211 is connected with a third one of the second detection ports 2131 of the second detection area 213. Preferably, each of the first detection ports 2111 and each of the second detection ports 2131 includes a metal bump, so as to provide ready electrical contact with the test pins of the test instrument. A material of metal bumps can be chosen from copper, aluminum, tin, silver, gold, an alloy containing any suitable combination of the foregoing metals, etc.
The display areas 212 are used to display test images once the LCD panel set 2 is assembled but before the LCD panel set 2 is cut into individual LCD panels (see below). The display areas 212 are arranged in a matrix and spaced a predetermined distance one from another. Each display area 212 includes a driving circuit 2120. The driving circuit 2120 includes signal communication lines. In particular, the driving circuit 2120 includes a plurality of parallel address lines 2121 and a plurality of parallel data lines (not labeled), with the data lines being orthogonal to the address lines 2121. The intersecting address lines 2121 and data lines are typically made of metal, and form a grid pattern. Each driving circuit 2120 further includes a plurality of TFT array circuits 2122, each TFT array circuit 2122 being located in a respective cell of the grid pattern. Each of the first detection ports 2111 of the corresponding first detection area 211 are electrically connected to the address lines 2121 of the display area 212. The second detection ports 2131 of the second detection area 213 are electrically connected to the first detection ports 2111 of the first detection area 211 (see above).
Referring to
With the above-described configuration, testing signals can be transmitted to each of display areas 212 simultaneously through the second detection ports 2131. Hence, only one round of testing signals needs to be applied in order that all of the TFT substrate units of the TFT master substrate 21 are tested. Therefore the speed and efficiency of testing of all the TFT substrate units can be improved. Further, because the testing is performed before the cutting step, if a defect is found in one of the LCD panel units, information about the defect is promptly sent back to the corresponding workstation on the production line. Parameters of the manufacturing process can then be timely adjusted, so that the defect is eliminated or at least mitigated when subsequent LCD panel sets 2 are manufactured. Compared with conventional art, the time lag between detection of the defect and correction of the problem at the workstation is reduced. For at least the above reasons, the efficiency of testing of the LCD panel units can be improved.
A preferred manufacturing process for obtaining the individual LCD panels from the LCD panel set 2 is described in the following steps:
Step 1: the TFT master substrate 21 is provided, with the first detection areas 211 and the second detection area 212 arranged as described above.
Step 2: the plurality of sealants 27 are set around the respective plurality of display areas 212 on the TFT master substrate 21, so as to define a plurality of corresponding receiving spaces within respective center portions of the display areas 212.
Step 3: the plurality of liquid crystal (LC) layers 25 are formed separately in each of the receiving spaces. The preferred forming method is an ODF process.
Step 4: the plurality of color filter substrates 23 are combined with the TFT master substrate 21 and sealed with the sealants 27 respectively. The sealants are then cured. Thereby, the LCD panel set 2 is obtained.
Step 5: an inspection and/or testing process is carried out on the LCD panel set 2, including via the aforesaid detection areas 211 and 213.
Step 6: after the inspection and/or testing process is completed, the LCD panel set 2 is cut into individual LCD panels. Only the LCD panel units which have passed the inspection and/or testing process are cut off and obtained.
Unlike in the above-described conventional technique, the present embodiments provide for inspection and/or testing of LCD panel units before the cutting step is performed. Therefore unsatisfactory LCD panel units can be detected promptly, and are not needlessly cut off from the LCD panel set 2. Hence, the time and cost of the cutting step can be reduced, and the efficiency of cutting of the LCD panel sets 2 can be improved.
As would be understood by a person skilled in the art, the foregoing preferred and exemplary embodiments are provided in order to illustrate principles of the present invention rather than limit the present invention. The above descriptions are intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which scope should be accorded the broadest interpretation so as to encompass all such modifications and similar structures and methods.
| Number | Date | Country | Kind |
|---|---|---|---|
| 95123818 | Jun 2006 | TW | national |
