Patent Application
20080283841
1. Field of the Invention
The present invention relates to an active-matrix thin-film-transistor substrate formed with thin film transistors and storage-capacitance elements, and to a structure of and a manufacturing method of a display device using the substrate.
2. Description of the Prior Art
Usually, pixels are formed in the display area of a display device, and displaying is performed by applying a signal voltage to a designated pixel. The designation is performed by a thin-film-transistor (hereinafter abbreviated as TFT) connected to each pixel with an auxiliary capacitor being added in order to keep the signal voltage constant during a designating period. To be more specific, the signal voltage applied to each pixel in the display device in synchronism with a given scan timing needs to be sufficiently held until the next scan timing. Holding the signal voltage for the pixel is fulfilled by charging a storage-capacitance element having a desired capacity.
A TFT is composed of a semiconductor layer such as a silicon film formed on an insulation substrate, a gate electrode, source drain wiring, an electrically conductive film such as a transparent conductive film, and an insulation film. In manufacturing a TFT substrate, while a TFT and a storage-capacitance element may be formed individually, it is advantageous to form them simultaneously from a viewpoint of production efficiency. That is, the storage-capacitance element may be sometimes formed concurrently using the same materials as those for the semiconductor layer, the conductive film, and the insulation film with which the TFT is constituted. For example, a technology has been disclosed in which a lower electrode, a dielectric insulation layer, and an upper electrode of a storage-capacitance element are formed using the same materials as those for a semiconductor layer, a gate insulation film, and a gate electrode of a TFT, respectively, (refer to FIG. 5 in Japanese Patent Laid-Open No. 2001-296550, and FIG. 1 in Japanese Patent laid-Open No. H06-235939). Furthermore, another technology has also been disclosed in which a lower electrode, a dielectric insulation layer, and an upper electrode of a storage-capacitance element are formed using the same materials as those for a gate electrode, an interlayer insulation film that covers the gate electrode, and a source electrode of a TFT, respectively, (refer to FIG. 1 in Japanese Patent Laid-Open No. 2004-241750).
On the other hand, another technology has also been disclosed in which layers different from a conductive layer and an insulation layer, which are main components of a TFT, are additionally formed as layers constituting a dielectric insulation layer and an upper electrode of a storage-capacitance element (refer to FIG. 4 in Japanese Patent Laid-Open No. 2001-305581).
Recent years have seen the development of display devices for high definition. For that reason, efforts have been made to enlarge the aperture ratio by narrowing the light-shield area of each pixel, which is an area unable to display. However, in TFT substrates also, the electrode area of a storage-capacitance element occupies most of the light-shield area, so that reduction of the electrode area has now become an important problem. On the other hand, the storage-capacitance element is required to have a desired capacity as explained above. Accordingly, there is a limit to reducing the electrode area based on the premise that the same layer is used for both the storage-capacitance element and the TFT, which is explained below.
In order to reduce the capacitor electrode area, it is required to form a dielectric layer either using a material having a high relative permittivity or making the layer as thin as possible to secure a desired capacity. While a silicon nitride (SiNx) film is used as a material of a relatively high relative-permittivity, the film has a problem with warpage due to an increase in the film stress. Making thin the film thickness of the dielectric layer of the storage-capacitance element enables its capacitance to increase; however, it may result in decrease in withstand voltage and increase in stray capacitance due to the small film thickness, in a case of the dielectric layer being shared with an interlayer insulation film in other portions such as TFTs and areas between wiring. These phenomena also give rise to problems such as of increase in short circuit failure and deterioration in electric characteristics.
On the premise that the dielectric layer of the storage-capacitance element is formed of the same material and with the same thickness as those of interlayer insulation films of TFTs, which is advantageous for production efficiency, the storage-capacitance element area, however, is difficult to be reduced. Accordingly, improvement of the aperture ratio is limited. Moreover, forming an additional layer having a thickness and a material most suited to the storage-capacitance element, as a matter of course, causes reduction in production efficiency. The root cause of these problems is resulted from reduction of flexibility in the design by the fact that the same material is used in forming both the TFT and the storage-capacitance element, which although improves their production efficiency, as described above. Hence, a method has been needed that eliminates these adverse effects without reducing production efficiency.
A TFT substrate provided with TFTs and storage-capacitance elements according to the present invention is characterized in that the storage-capacitance elements include an electrically conductive film and an insulation film that are different from those used for the TFTs.
According to the present invention, a TFT substrate can be obtained that is provided with storage-capacitance elements having an optimum material and an optimum film thickness without restricting efficiency in production and flexibility in design.
First of all, an explanation is made with reference to
The display device according to the invention is provided with a TFT substrate 110. The TFT substrate 110, which is, for example, a TFT array substrate, has a display area 111 and a peripheral area 112 that surrounds the display area 111. In the display area 111, a plurality of parallel gate wirings (scanning signal lines) 121 and a plurality of parallel source wirings (displaying signal lines) 122 are formed so as to cross over each other orthogonally, so that areas enclosed by adjacent two of the gate wirings 121 and adjacent two of the source wirings 122 become pixels 117. Accordingly, the pixels 117 are arranged in a matrix form in the TFT substrate 111. Moreover, storage-capacitor wirings 123 are formed across the pixels 117 in parallel to the gate wirings 121.
Furthermore, a scanning-signal drive circuit 115 and a display-signal drive circuit 116 are provided in the peripheral area 112 of the TFT substrate 110. The gate wirings 121 are extended from the display area 111 to the peripheral area 112, to be connected with the scanning-signal drive circuit 115 at the edge of the TFT substrate 110. The source wirings 122 are also extended from the display area 111 to the peripheral area 112, to be connected with the display-signal drive circuit 116 at the edge of the TFT substrate 110. External wirings 118 and 119, which are wiring boards such as flexible printed circuit (FPC) boards, are connected with the scanning-signal drive circuit 115 and display-signal drive circuit 116, respectively, in the vicinities of the respective circuits.
Various signals are externally supplied to the scanning-signal drive circuit 115 and the display-signal drive circuit 116 through the external wirings 118 and 119. The scanning-signal drive circuit 115 supplies a gate signal (a scanning signal) to the gate wirings 121 based on a control signal from outside. By the gate signal, the gate wirings 121 are sequentially activated. The display-signal drive circuit 116 supplies display signals to the source wirings 122, based on display data and a control signal from outside. Thereby, the pixels 117 can be supplied with respective display voltages in accordance with the display data.
In each of the pixels 117, at least one thin film transistor (hereinafter, abbreviated as TFT) 120 and a storage-capacitance element 130 connected with the TFT 120 are formed. The TFT 120 is arranged in the vicinity of each cross-point of the source wirings 122 and the gate wirings 121. When the TFT 120, which is a switching element, turns on by the gate signal from one of the gate wirings 121, the TFT 120 thereby supplies a display voltage from one of the source wirings 122 to a pixel electrode connected to its drain electrode. An electric field in accordance with the display voltage is resultantly produced between the pixel electrode and its counter electrode. On the other hand, the storage-capacitance element 130 is electrically connected not only to the TFT 120 but also to the counter electrode through one of the storage-capacitor wirings 123. As a result, the storage-capacitance element 130 is connected in parallel between the pixel electrode and the counter electrode.
Moreover, an orientation film (not shown) is formed on the surface of the TFT substrate 110. Furthermore, a counter substrate, which is, for example, a color filter substrate, is disposed opposing the TFT substrate 110 on the viewing side. On the counter substrate, a color filter, a black matrix (BM), a counter electrode, an orientation film and the like are formed. There may be a case in which the counter electrode is disposed on the TFT substrate 110 side. A liquid crystal layer is held between the TFT substrate 110 and the counter substrate, that is, a liquid crystal is injected into therebetween. On the outer surfaces of the TFT substrate 110 and the counter substrate, polarization plates, a phase difference plate, and the like are provided. Moreover, a backlight unit is disposed behind the liquid crystal display panel opposite from the viewing side.
The liquid crystal is driven by the electric field between the pixel electrode and the counter electrode, that is, the alignment direction of the liquid crystal between the substrates is varied. Light passing through the liquid crystal layer is thereby changed in its polarization state. To be more specific, light from the backlight unit is linearly polarized by being passed through the polarization plate on the array substrate side, and the linearly polarized light is varied in its polarization state by being passed through the liquid crystal layer.
The amount of the light passing through the polarization plate on the counter substrate resultantly varies according to the polarization state. That is, the transmitted light passed through the liquid-crystal display panel from the backlight unit is varied in amount by passing through the polarization plate on the view side. Accordingly, by varying the display voltage, the amount of the light having been passed through the polarization plate on the view side, that is, by varying on a pixel basis the display voltage, a desired image can be displayed. In the series of these operations, the storage-capacitance element 130 serves to hold the display voltages by producing the electric field parallel to that between the pixel electrode and the counter electrode.
Next, an explanation will be made below with reference to
An interlayer insulation film 7 is formed so as to cover the gate electrode 4b and the storage-capacitance element 130. A source drain wiring 8 is formed on the interlayer insulation film 7, and an insulation film 9 is formed so as to cover the source drain wiring 8 and the interlayer insulation film 7. Furthermore, contact-holes 10 are opened: first contact-holes 10a that reach the surface of the semiconductor layer 2 are formed penetrating the insulation film 9, the interlayer insulation film 7, and the gate insulation film 3; a second contact-hole 10b that reaches the surface of the second capacitor electrode 6a is formed penetrating the insulation film 9 and the interlayer insulation film 7; and a third contact-hole 10c that reaches the source drain wiring 8 is formed penetrating the insulation film 9.
A transparent conductive film 11b that is a connection electrode is formed on the insulation film 9 to connect the semiconductor layer 2 with the source drain wiring 8 through one of the first contact-holes 10a and the third contact-hole 10c, and a transparent conductive film 11a that is the pixel electrode is also formed on the insulation film 9 to connect the semiconductor layer 2 with the second capacitor electrode 6a through the other of the first contact-holes 10a and the second contact-hole 10b.
In this embodiment, the second capacitor electrode 6a of the storage-capacitance element 130 is formed as another layer that is different from those of the source drain wiring 8 and the pixel electrode 11a; and the dielectric layer 5a of the storage-capacitance element 130 is also formed as another layer that is different from insulation layers such as the interlayer insulation film 7 that is a constituent of the TFT 120. Moreover, the second capacitor electrode 6a and the dielectric layer 5a are not formed in the TFT 120 because they are in the same pattern for the storage-capacitance element 130. Therefore, materials, thicknesses, and the likes necessary for the second capacitor electrode 6a and the dielectric layer 5a from the design standpoint, can be freely determined independently of requirements of a conductive film and an insulation film for the TFT. Moreover, according to the embodiment, no increase in the number of photolithography processes is needed in forming such a structure, which does not reduce the production efficiency at all. As for this point, it will be disclosed in detail in the following explanation on a method of manufacturing the TFT substrate.
An explanation is made with reference to
While the semiconductor film is formed directly on the substrate 1 in the embodiment, a semiconductor film may be formed after an inorganic insulation film of SiO2, SiN, or the like has been formed. That is, after the inorganic insulation film and the semiconductor film are successively formed on the substrate 1, only the semiconductor film may be patterned as described above. In this case, an effect is brought about that can prevent contaminants from migrating from the substrate into the semiconductor film due to the existence of the inorganic insulation film therebetween.
After that, the gate insulation film 3 is formed so as to be in contact with the semiconductor layer 2 as shown in
Next, after a first metal layer 4, an insulation layer 5, and a second metal layer 6 are formed by a well-known method, a resist-mask 12 is formed by the second photolithography. A top plane view and a cross-sectional view of the pixel at this stage are shown in
The first metal layer 4 is a conductive layer composed of a mono-layer or a laminated structure with base materials of Mo, Cr, W, or Al formed by a vapor deposition method or a spattering method, for forming the gate electrode 4b, the first capacitor electrode 4a, gate wirings that are not shown, and the like. For forming the first capacitor electrode 4a, there is no particular limitation on the first metal layer 4 as long as it is a conductive layer. However, since the first metal layer 4 is also used for the gate electrode 4b, the gate wirings, and the like that are formed later on the semiconductor layer 2 in the thin film transistor 120, the metal layer is limited to such a material that etching workability, electrical conductivity, and the like are taken into account.
The insulation layer 5 is an insulation layer to become the dielectric layer 5a of the storage-capacitance element 130 and is made of SiO2 or SiN formed by a CVD method or the like. The material and the thickness of the insulation layer 5 are determined so that a desired capacitance Cs is obtained by optimizing the relative permittivity e of the dielectric layer 5a, the required film thickness d thereof, and the required capacitor electrode area A taking into account the aperture ratio of the pixel and the like. Specifically, the capacitance Cs is calculated by the following formula:
Cs=ε*A/d.
While SiO2 and SiN given above have relative permittivities of 3.9 and 6.7, respectively, a material for the insulation layer 5 is not limited to these. For example, if there is no problem with etching workability, an extremely thin oxide insulation film of 10 through 50 nm may be formed as the insulation layer 5 on the surface of the first metal layer 4 by an anodic oxidation method, to form the second metal layer 6 thereafter. Alumina may be used as the oxide insulation film.
The second metal layer 6 is a conductive layer that is a metal film formed by a spattering method or a vapor deposition method, for forming the second capacitor electrode 6a of the storage-capacitance element 130. A material of Mo or Cr is desirable for the metal film due to easiness of etching. While the film thickness is desirably as thin as possible from the viewpoint of etching selectivity for the gate insulation film 3, which is described later, the thickness is appropriately determined because the film thickness is needed at least to serve as an ion-implantation mask. In the embodiment, a Mo film is formed so as to be 100 nm in thickness.
Next, an explanation is made on resist-masks 12a and 12b shown in
In order to thus vary the film thickness of the resist from area to area, a well-known manufacturing method called “gray-tone” or “half-tone” can be employed. In a case of a positive-type resist, it has a tendency that its residual film thickness increases with decreasing the amount of irradiation light in a photolithography. Accordingly, reducing the amount of light irradiating the area corresponding to the gate electrode 4b than that irradiating the area corresponding to the second capacitor electrode 6a, allows to form the resist-masks 12a and 12b as shown in
After that, the areas not covered with the resist-masks 12a and 12b are etched continuously layer by layer in the order of the second metal layer 6, the insulation layer 5, and the first metal layer 4. These three layers may be etched together at once.
Next, an ion implantation is performed, which is not shown in the figures, using an electrically conductive contaminant such as boron. While the boron reaches the semiconductor layer 2 through the gate insulation film 3, to form a source drain region in the semiconductor layer 2, the region beneath the gate electrode 4b is not implanted with the boron because the gate electrode 4b serves as a mask. Thus, a channel region is formed in the semiconductor layer 2 beneath the gate electrode 4b. Incidentally, implantation of boron as described above forms a P-MOS TFT, whereas implantation of phosphorus forms an N-MOS TFT.
Next, the resist-masks 12a and 12b are uniformly thinned by ashing using oxygen, and then the ashing is stopped when the resist-mask 12b on the gate electrode 4b has disappeared. Regarding ashing, depending on apparatus, an ashing rate is preferably not so large in order to perform ashing as uniform as possible and to easily control the ashing amount. The ashing in the embodiment is performed at a rate of 600 nm/min. under the condition of an oxygen flow rate of 150 standard-cc/min.. Incidentally, while oxygen alone is used as an ashing gas in the embodiment, nitrogen or a fluorinated gas may be added thereto.
After that, an exposed part of the second metal layer 6 other than the second capacitor electrode 6a, that is, part of the second metal layer 6 remaining on the gate electrode 4b is removed by etching. Furthermore, part of the insulation layer 5 is also removed by etching. A state at this stage is shown in
Next, the interlayer insulation film 7 is formed. A SiO2 film or SiN film formed by a CVD method is excellently suitable for the interlayer insulation film 7. An annealing process may be performed thereafter in order to activate the conductive contaminant such as boron having been implanted into the semiconductor layer 2.
A third metal layer is further formed on the interlayer insulation film 7 by a spattering method or the like. Then, a resist-mask 12c coated thereon is formed by the third photolithography. After that, the source drain wiring 8 is formed by etching the third metal layer. A top plane view and a cross-sectional view of the structure at this stage are shown in
After that, the insulation film 9 is formed so as to cover the source drain wiring 8 and the interlayer insulation film 7. Then, the resist-mask 12d coated on the insulation film 9 is formed by the fourth photolithography. The contact-holes 10a, 10b, and 10c are formed thereafter. A top plane view and a cross-sectional view of the pixel at this stage are shown in
A SiN film formed by a CVD method is used for the insulation film 9. The contact-holes 10 are formed by dry-etching using a fluorinated gas such as carbon tetrafluoride (CF4) with an etching rate of 70 nm/min. after the resist-mask 12d having openings as shown in
After that, the transparent conductive film 11 is formed. The resist-mask 12e coated thereon is formed thereafter by the fifth photolithography, and then the transparent conductive film 11 is etched. A top plane view and a cross-sectional view of the pixel at this stage are shown in
The resist-mask 12e has a pattern such as to connect the pixel electrode with the contact-holes corresponding thereto, and to connect the connection electrode with the contact-holes corresponding thereto. Thereby, as shown in
In the embodiment, after the second photolithography, two processes are performed: the resist-masks 12a and 12b are uniformly thinned by the ashing process; and then the etching process is performed in the state of only the resist-mask 12a remaining. By this method, the insulation film different from that of the TFT 120 can be formed in the storage-capacitance element 130 without adding any photolithography processes. That is, the dielectric layer 5a made of a suitable material for and having an optimum film thickness for the storage-capacitance element 130 can be formed without sacrificing production efficiency and flexibility in design. Moreover, the second capacitor electrode 6a of the storage-capacitance element 130 is also different from the electrode wiring used for the TFT 120, which allows a suitable material and an optimum thickness to be selected for the storage-capacitance element 130.
The manufacturing method disclosed in the present embodiment is not limited to that as described, but may be altered within the scope of the effect being brought about. While, in the embodiment, the explanations have been made on the manufacturing method in which not only the second metal layer 6 but also the insulation layer 5 on the gate electrode 4b are removed as shown in
Whereas the insulation layer 5 shown in
Moreover, the manufacturing method disclosed in the embodiment is not limited to that as described, but may be appropriately added within the scope of the effect being brought about. For example, when the second metal layer 6 has been etched to be removed as shown in
Furthermore, by adding one more process of a photolithography, a TFT may be formed that has a complementary metal-oxide semiconductor (CMOS) structure. That is, the CMOS structure can be formed in the second photolithography process in the embodiment by forming first a positive-channel metal-oxide semiconductor (PMOS), and then by forming a negative-channel metal-oxide semiconductor (NMOS) in a state of the PMOS being fully covered with a resist.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-283731 | Oct 2006 | JP | national |
