Claims
- 1. A thin film transistor comprising:
- a gate electrode;
- a source electrode;
- a drain electrode;
- wherein one of said source and drain electrodes includes first and second conductive layers offset with respect to one another; and
- wherein a thin film transistor channel length L.sub.T of the transistor is defined by the equation:
- L.sub.T =L.sub.1,2 -.DELTA.L
- where L.sub.1,2 is the length defined between said first conductive layer and the similar layer of the other of said source and drain electrodes, and .DELTA.L is the lateral offset between said first and second conductive layers.
- 2. The thin film transistor of claim 1, wherein said first and second conductive layers are of different metals adapted to be etched by different etchants.
- 3. The thin film transistor of claim 2, wherein both of said source and drain electrodes include first and second metal layers offset laterally from one another.
- 4. The thin film transistor of claim 1, wherein the transistor has a linear channel of length L.sub.T and is a pixel switching device in an active matrix liquid crystal display (AMLCD).
- 5. The transistor of claim 1, wherein the reduced channel length L.sub.T is no greater than about 10 .mu.m.
Parent Case Info
This is a division of application Ser. No. 08/519,920, filed Aug. 28, 1995, now U.S. Pat. No. 5,650,358, which is incorporated herein by reference.
US Referenced Citations (23)
Foreign Referenced Citations (2)
Number |
Date |
Country |
63-77159 |
Apr 1988 |
JPX |
283941 |
Mar 1990 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
519920 |
Aug 1995 |
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