Thermal isolation techniques

Information

  • Patent Grant
  • 9348377
  • Patent Number
    9,348,377
  • Date Filed
    Thursday, April 3, 2014
    10 years ago
  • Date Issued
    Tuesday, May 24, 2016
    8 years ago
Abstract
Various embodiments described herein include systems, methods and/or devices used to dissipate heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board with one or more heat generating components coupled thereto. The electronic assembly further includes a second circuit board with one or more heat sensitive components coupled thereto. The electronic assembly also includes a thermal barrier interconnect. The thermal barrier interconnect electrically couples the first circuit board to the second circuit board. In some embodiments, thermal barrier interconnect is a flexible interconnect with a lower thermal conductivity than the first circuit board and the second circuit board. The thermal barrier interconnect forms a thermal barrier between the first and second circuit boards which protects the heat sensitive components from the heat generating components.
Description
TECHNICAL FIELD

The disclosed embodiments relate generally to heat management, and in particular, to dissipating heat generated by electronic components in electronic systems.


BACKGROUND

Electronics, such as processors or memory, generate heat during operation. If left unchecked, this heat can reduce system performance and even lead to partial or complete system failure. As such, many existing technologies attempt to remove or dissipate heat through the use of heat sinks, cooling fans, etc.


While these technologies may be effective for cooling a single electronic component that is not located near other sources of heat, these technologies fall short when it comes to more complex systems and higher density systems, such as solid state drives (SSDs), dual in-line memory modules (DIMMs), and small outline-DIMMs, all of which utilize memory cells to store data as an electrical charge or voltage.


Existing cooling systems for such systems typically include multiple heat sinks and high-speed fans. These cooling systems are noisy; add significant expense to the system; increase the overall energy consumption of these systems; and decrease system efficiency. Moreover, existing cooling systems do not always alleviate localized hot-spots that form within the systems, which in turn shortens the life of the individual components within the system.


In the absence of efficient heat dissipation mechanisms, the increased heat can ultimately lead to reduced performance or failure of either individual memory cells of a memory module or the entire memory module.


Some systems include circuitry that is also sensitive to high temperatures. For example, Solid State Disk (SSD) drives typically contain support circuitry that during normal operation generates a large amount of heat. However, the NAND flash memory used in these designs has a temperature sensitivity that reduces the life of the drive.


A common technique for removing heat from the NAND in an SSD is to integrate a heat sink design in the case design for the drive. However, this presents a problem when the form factor for the SSD does not include a case, e.g., PCIe or embedded SSDs that use a PCBA (printed circuit board assembly) and no case. In other words, many of the heat sinks used for SSDs are an integral part of the case design, and when there is no case, the heat removal is handled by passing large volumes of air over the heat generating components. However, as mentioned above, these cooling systems are noisy; add significant expense to the system; increase the overall energy consumption of these systems; decrease system efficiency, and do not always alleviate localized hot-spots that form within the systems.


In light of these and other issues, it would be desirable to provide a system and method for more effectively cooling electronic components, especially those found in systems that contain multiple heat generating components.


SUMMARY

According to some embodiments there is provided an electronic assembly for dissipating heat. The electronic assembly includes a first circuit board with one or more heat generating components coupled thereto. The electronic assembly further includes a second circuit board with one or more heat sensitive components coupled thereto. The electronic assembly also includes a thermal barrier interconnect. The thermal barrier interconnect electrically couples the first circuit board to the second circuit board. In some embodiments, thermal barrier interconnect is a flexible interconnect with a lower thermal conductivity than the first circuit board and the second circuit board. The thermal barrier interconnect forms a thermal barrier between the first and second circuit boards which protects the heat sensitive components from the heat generating components.


Other embodiments include a method of manufacturing an electronic assembly for dissipating heat. A first circuit board with one or more heat generating components coupled thereto is provides. A second circuit board with one or more heat sensitive components coupled thereto is also provides. A thermal barrier interconnect is provided and it is coupled to the first circuit board to the second circuit board such that the first and second circuit board are electrically coupled to one another.


Some advantages of the embodiments describe herein are as follows. These electronic assemblies provide a means of differential temperature control at design time. They also help to reduce thermal issues on selected device in a single assembly. The flexible interconnect allows for variable form factors, shapes, designs, and/or assemblies. These electronic assemblies allow for segregation of devices or components that have different temperature sensitivities. They increase the life of a solid state drive by increasing data retention from lower device temperatures. For instance, a NAND flash running at a lower temperature will have better data retention and therefore require less recycling of data and lengthen the drive's life. These electronic assemblies are also better at compensating for thermal expansion and contractions over a wide temperature range.


Other embodiments and advantages may be apparent to those skilled in the art in light of the descriptions and drawings in this specification.





BRIEF DESCRIPTION OF THE DRAWINGS

So that the present disclosure can be understood in greater detail, a more particular description may be had by reference to the features of various embodiments, some of which are illustrated in the appended drawings. The appended drawings, however, merely illustrate the more pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features.



FIG. 1 is a block diagram of an exemplary system module in a typical computational device in accordance with some embodiments.



FIG. 2 is a side view of an exemplary electronic assembly, in accordance with some embodiments.



FIG. 3A is a side view of another exemplary electronic assembly, in accordance with some embodiments.



FIG. 3B is an oblique view of the exemplary electronic assembly of FIG. 3A, in accordance with some embodiments.



FIG. 4 is a side view of another exemplary electronic assembly, in accordance with some embodiments.



FIG. 5 illustrates an exemplary flow chart of a method for assembling and using an electronic assembly, in accordance with some embodiments.





In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.


DETAILED DESCRIPTION

The various embodiments described herein include systems, methods and/or devices used by, or integrated into, electronic assemblies. In particular, the electronic systems, the heat sinks, and the heat dissipation method described herein facilitate dissipation of heat generated by electronic components in the electronic systems.


The embodiments described herein allow for the isolation of heat sensitive devices from heat generating devices on a PCBA (printed circuit board assembly). In some embodiments, by using a thermal barrier interconnect such as a flexible circuit board between two rigid printed circuit boards, a thermal barrier is formed. This thermal barrier is used to allow one board to operate at a reduced temperature in relation to the other board. For instance, a board with NAND flash can operate at a reduced temperature in relation to the board which contains the NAND flash controller and power supply electronics. The difference in temperatures between the boards can be as much as 20 degrees C. This means the NAND flash running at a lower temperature will have better data retention and therefore require less recycling of data (which is Write Amplification), thereby lengthening the drive life.


A thin flexible board which carries the signals does not contain the thermal mass of the rigid FR4 (or other types) board material. As such, the thin flexible board produces in a thermal barrier. In some embodiments, the thermal barrier is further enhanced from the reduction in copper planes, which are found in the rigid boards to supply power and grounds. In some embodiments, the flexible material is made from a kapton or other polyimide materials which has a lower thermal conductivity.


One example of such an electronic system is a memory system that is commonly integrated in many computers and consumer electronic devices. Memory systems frequently include closely placed memory modules that require efficient heat dissipation in order to ensure proper function and life span. Some embodiments are described herein in the context of generic electronic systems. However, one of skill in the art will recognize that the embodiments described herein are suitable for use in a memory system as well as any other appropriate electronic system that includes two or more electronic modules integrated in a limited space and which requires efficient dissipation of generated heat.


More specifically, according to some embodiments, an electronic assembly for dissipating heat is provided. The electronic assembly includes a first circuit board with one or more heat generating components coupled thereto. The electronic assembly further includes a second circuit board with one or more heat sensitive components coupled thereto. The electronic assembly also includes a thermal barrier interconnect. The thermal barrier interconnect electrically couples the first circuit board to the second circuit board.


In some embodiments, the thermal barrier interconnect has a lower thermal conductivity than the first circuit board and the second circuit board.


In some embodiments, the thermal barrier interconnect is a flexible interconnect. In some embodiments, the flexible interconnect is made from a kapton material. In some embodiments, the flexible interconnect is made from a polyimide material.


In some embodiments, the thermal barrier interconnect has a lower thermal mass than the first and circuit boards.


In some embodiments, the thermal barrier interconnect includes power planes for CORE voltage and the I/O voltage.


In some embodiments, the thermal barrier interconnect does not include a plurality of power planes found in the first and second circuit boards.


In some embodiments, the one or more heat generating components include one or more power supply electronic components.


In some embodiments, the one or more heat generating components include a NAND flash controller.


In some embodiments, the one or more heat sensitive components include NAND flash memory.


In some embodiments, the first circuit board, the second circuit board are next to one another in a substantially common plane.


In some embodiments, first circuit board is on a first plane and the second circuit board is on a second plane substantially parallel to the first plane and separated by a space.


Some embodiments also include a fastener configured to couple the first circuit board to the second circuit board. The fastener, first circuit board, second circuit board, and thermal barrier interconnect surround the space and form an air flow channel.


In some embodiments, in operation the first circuit board has a first temperature and the second circuit board has a second temperature lower than the first temperature. In some embodiments, in operation, the second temperature is up to 20 degrees Celsius lower than the first temperature.


In some embodiments, the electronic assembly is a solid state disk drive.


In some embodiments, the electronic assembly does not include a case.


In some embodiments, the electronic assembly does not include a heat sink.


Another aspect of the invention includes a method of manufacturing an electronic assembly for dissipating heat. A first circuit board with one or more heat generating components coupled thereto is provided. A second circuit board with one or more heat sensitive components coupled thereto is also provided. A thermal barrier interconnect is provided and it is coupled to the first circuit board to the second circuit board such that the first and second circuit board are electrically coupled to one another.


Numerous details are described herein in order to provide a thorough understanding of the exemplary embodiments illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known methods, components, and circuits have not been described in exhaustive detail so as not to unnecessarily obscure more pertinent aspects of the embodiments described herein.



FIG. 1 is a block diagram of an exemplary system module 100 in a typical computational device in accordance with some embodiments. The system module 100 in this computational device includes at least a central processing unit (CPU) 102, memory modules 104 for storing programs, instructions and data, an input/output (I/O) controller 106, one or more communication interfaces such as network interfaces 108, and one or more communication buses 150 for interconnecting these components. In some embodiments, the I/O controller 106 allows the CPU 102 to communicate with an I/O device (e.g., a keyboard, a mouse, a track-pad, etc.) via a universal serial bus interface (or any other suitable wired or wireless interface). In some embodiments, the network interfaces 108 include one or more interfaces for Wi-Fi, Ethernet, and/or Bluetooth networks, each allowing the computational device 100 to exchange data with an external source, such as a server or another computational device. In some embodiments, the communication buses 150 include circuitry (sometimes called a chipset) that interconnects and controls communications among various system components included in the system module.


In some embodiments, the memory modules 104 include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Furthermore, each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.


The memory devices can be formed from passive elements, active elements, or both. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles or a charge storage dielectric material.


Multiple memory elements may be configured so that they are connected in series or such that each element is individually accessible. By way of non-limiting example, NAND devices contain memory elements (e.g., devices containing a charge storage region) connected in series. For example, a NAND memory array may be configured so that the array is composed of multiple strings of memory in which each string is composed of multiple memory elements sharing a single bit line and accessed as a group. In contrast, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. One of skill in the art will recognize that the NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.


The semiconductor memory elements included in a single device, such as memory elements located within and/or over the same substrate or in a single die, may be distributed in a two- or three-dimensional manner (such as a two dimensional (2D) memory array structure or a three dimensional (3D) memory array structure).


In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or single memory device level. Typically, in a two dimensional memory structure, memory elements are located in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer on which the material layers of the memory elements are deposited and/or in which memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed.


The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arranged in non-regular or non-orthogonal configurations as understood by one of skill in the art. The memory elements may each have two or more electrodes or contact lines, including a bit line and a word line.


A three dimensional memory array is organized so that memory elements occupy multiple planes or multiple device levels, forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).


As a non-limiting example, each plane in a three dimensional memory array structure may be physically located in two dimensions (one memory level) with multiple two dimensional memory levels to form a three dimensional memory array structure. As another non-limiting example, a three dimensional memory array may be physically structured as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate in the y direction) having multiple elements in each column and therefore having elements spanning several vertically stacked planes of memory devices. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, thereby resulting in a three dimensional arrangement of memory elements. One of skill in the art will understand that other configurations of memory elements in three dimensions will also constitute a three dimensional memory array.


By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be connected together to form a NAND string within a single plane, sometimes called a horizontal (e.g., x-z) plane for ease of discussion. Alternatively, the memory elements may be connected together to extend through multiple parallel planes. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single plane of memory elements (sometimes called a memory level) while other strings contain memory elements which extend through multiple parallel planes (sometimes called parallel memory levels). Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.


A monolithic three dimensional memory array is one in which multiple planes of memory elements (also called multiple memory levels) are formed above and/or within a single substrate, such as a semiconductor wafer, according to a sequence of manufacturing operations. In a monolithic 3D memory array, the material layers forming a respective memory level, such as the topmost memory level, are located on top of the material layers forming an underlying memory level, but on the same single substrate. In some embodiments, adjacent memory levels of a monolithic 3D memory array optionally share at least one material layer, while in other embodiments adjacent memory levels have intervening material layers separating them.


In contrast, two dimensional memory arrays may be formed separately and then integrated together to form a non-monolithic 3D memory device in a hybrid manner. For example, stacked memories have been constructed by forming 2D memory levels on separate substrates and integrating the formed 2D memory levels atop each other. The substrate of each 2D memory level may be thinned or removed prior to integrating it into a 3D memory device. As the individual memory levels are formed on separate substrates, the resulting 3D memory arrays are not monolithic three dimensional memory arrays.


Further, more than one memory array selected from 2D memory arrays and 3D memory arrays (monolithic or hybrid) may be formed separately and then packaged together to form a stacked-chip memory device. A stacked-chip memory device includes multiple planes or layers of memory devices, sometimes called memory levels.


The term “three-dimensional memory device” (or 3D memory device) is herein defined to mean a memory device having multiple layers or multiple levels (e.g., sometimes called multiple memory levels) of memory elements, including any of the following: a memory device having a monolithic or non-monolithic 3D memory array, some non-limiting examples of which are described above; or two or more 2D and/or 3D memory devices, packaged together to form a stacked-chip memory device, some non-limiting examples of which are described above.


A person skilled in the art will recognize that the invention or inventions descried and claimed herein are not limited to the two dimensional and three dimensional exemplary structures described here, and instead cover all relevant memory structures suitable for implementing the invention or inventions as described herein and as understood by one skilled in the art.


In some embodiments, the memory modules 104 include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. In some embodiments, the memory modules 104, or alternatively the non-volatile memory device(s) within memory modules 104, include a non-transitory computer readable storage medium. In some embodiments, memory slots are reserved on the system module 100 for receiving the memory modules 104. Once inserted into the memory slots, the memory modules 104 are integrated into the system module 100.


In many embodiments, the system module 100 further includes one or more components selected from:

    • a memory controller 110 that controls communication between the CPU 102 and memory components, including the memory modules 104, in the computational device;
    • solid state drives (SSDs) 112 that apply integrated circuit assemblies to store data in the computational device, and in some embodiments, are based on NAND or NOR memory configurations;
    • a hard drive 114 that is a conventional data storage device used for storing and retrieving digital information based on electromechanical magnetic disks;
    • a power supply connector 116 that is electrically coupled to receive an external power supply;
    • power management integrated circuit (PMIC) 118 that modulates the received external power supply to other desired DC voltage levels, e.g., 5V, 3.3V or 1.8V, as required by various components or circuits within the computational device;
    • a graphics card 120 that generates a feed of output images to one or more display devices according to their desirable image/video formats; and
    • a sound card 122 that facilitates the input and output of audio signals to and from the computational device under control of computer programs.


It is noted that the one or more communication buses 150 also interconnect and control communications among various system components, including components 110-122 (as well as other components not listed).


Further, one of skill in the art will understand that other non-transitory computer readable storage media can be used. In particular, as new data storage technologies are developed, those new data storage technologies may be used in the memory modules described herein. These new non-transitory computer readable storage media include, but are not limited to, those manufactured from biological materials, nanowires, carbon nanotubes, and individual molecules, even though the respective data storage technologies are currently under development and are yet to be commercialized.


Some of the aforementioned components (or other components not mentioned) generate heat during normal operation. In some instances, they may be integrated with heat sinks in order to reduce the temperatures of the corresponding components. For example, the solid state drives 112 used in a blade server may have heat sinks mounted on the top of each individual dual in-line memory module (DIMM) or on an electronic assembly containing the DIMMs. Heat generated from electronic components in the DIMMs is conducted to the heat sinks, and dissipated by airflow generated by fans. However, as the data workload in these blade servers increases and the form factor of the DIMMs decreases (e.g., closely placed memory slots in the memory modules 104), it becomes more difficult for conventional heat sinks and high-speed fans to conduct and dissipate the heat effectively. More generally, as the size of electronic components decreases, and more and more electronic components are being placed in close proximity to one another on circuit boards, it becomes more difficult to keep the electronic components sufficiently cool. Furthermore, some form factors of solid state disk drives to not include a case and thus heat skinks cannot be integrated into the design of the case.


To address this issue, the various embodiments described herein describe electronic assemblies that separate heat generating components from heat sensitive components by using a thermal barrier interconnect. In some embodiments, by using a thermal barrier interconnect such as a flexible circuit board between two rigid printed circuit boards, a thermal barrier is formed. This thermal barrier is used to allow one board to operate at a reduced temperature in relation to the other board. For instance, a board with NAND flash can be at a reduced temperature in relation to the board which contains the NAND flash controller and power supply electronics. The difference can be as much as 20 degrees C. This means the NAND flash running at a lower temperature will have better data retention and therefore require less recycling of data (which is Write Amplification) and lengthen the drive life.


Furthermore, in some embodiments, electronic assemblies form a self-supporting tube or channel for directing airflow over electronic components of the assembly. In particular, a channel structure helps confine air flow to the space within the channel. Thus, by passing air through the channel (e.g., either by convection, fans, or any other technique), heat can be effectively removed from components that are within the channel, or that are otherwise thermally coupled to the channel (e.g., components that are mounted outside the channel but are thermally coupled to a heat sink within the channel). Because the channel structures confine the airflow to the space within the channel, better cooling performance can be achieved for a given amount of airflow than would otherwise be possible.



FIG. 2 is a side view of an exemplary electronic assembly, in accordance with some embodiments. FIG. 2 illustrates an embodiment of an electronic assembly 200 (“assembly 200”). In particular, the assembly 200 comprises a first circuit board 202 and a second circuit board 204. (Circuit boards are sometimes referred to herein simply as “boards.”)


The first circuit board 202 includes with one or more heat generating components 206 coupled to it. The second circuit board 204 includes one or more heat sensitive components 210 coupled to it. In some embodiments, one or more heat sensitive components 210 are, or include, memory modules. In some embodiments, the one or more heat generating components 206 are, or include, processors, power supply electronics, and/or flash controllers.


In some embodiments, at least one of the first circuit board 202 and second circuit board 204 include one or more solid state drives (SSDs). In some embodiments, at least one of first circuit board 202 and second circuit board 204 include one or more three-dimensional (3D) memory devices.


The first board 202 and second board 204 are mechanically and/or electrically coupled via a thermal barrier interconnect 211. The thermal barrier interconnect 211 can carry electrical signals between two boards (e.g., the first board 202 and the second board 204), or between other electronic components or sub-assemblies. For example, the assembly 200 includes a thermal barrier interconnect 211 that mechanically and/or electrically couples the first board 202 to the second board 204.


In various embodiments, the thermal barrier interconnect 211 is a flexible board, flexible wire array, flexible PCB, flexible flat cable, ribbon cable (e.g., a flexible flat ribbon cable), or a combination thereof. In some embodiments, the flexible material is made from a kapton or other polyimide materials which has a lower thermal conductivity.


The thermal barrier interconnect 211 does not contain the thermal mass of the rigid FR4 (or other types) board material. As such, thermal barrier interconnect 211 produces in a thermal barrier. In some embodiments, the thermal barrier is further enhanced from the reduction in copper planes which are found in the rigid boards to supply power and grounds.


It will be understood that more or fewer flexible interconnects can be used to couple the boards of an electronic assembly in accordance with the ideas described in the instant application. For example, an electronic assembly may also include a fastener interconnect. One example of such an assembly is described herein with reference to FIG. 4.


Specifically, FIG. 2 shows an solid state disk constructed in such a way as to thermally isolate the heat generating components 206 such as power supply and NAND controller electronics (temperature zone 1) from the more temperature sensitive components 210, such as NAND flash (temperature zone 2). The thermal barrier interconnect 211 such as a flexible circuit board which connects the two boards provides an electrical connection between them, such that for instance it supplies the NAND power and data and controller signals (from the first board 202) for the NAND (on the second board 204).


It is further noted, that typically the NAND uses only two power supply connections, one for the CORE voltage and one for the I/O voltage. This means other power planes used by the NAND flash controller and support circuitry from the NAND PCBA are not needed in the thermal barrier interconnect 211. By removing the unused power planes from the NAND printed circuit board assembly you in turn remove some amount of thermal conduction to the main controller boards.



FIGS. 3A and 3B show a solid state disk drive form factor. In some embodiments, this form factor is used as a daughter board assembly on a larger SSD integration platform. In some embodiments, all of the NAND flash is on the outer board (e.g. the second board 204. This allows better exposure to airflow for lower temperature on the NAND in comparison to the main controller board.


This configuration along with the proper airflow has been shown to be 20 degree C. lower than the NAND temperature from the main controller board. Because a flexible circuit board is a standard impedance controlled PCB, there is no loss in signal strength of speed to the NAND flash board when a flexible circuit board is employed as the thermal barrier interconnect. From an electrical standpoint, this assembly is all one board with no schematic restrictions.



FIGS. 3A and 3B illustrate another embodiment of an electronic assembly 200 (“assembly 200”). In particular, the assembly 200 comprises a first circuit board 202 and a second circuit board 204.


The first circuit board 202 includes one or more heat generating components 206 coupled to it. The second circuit board 204 includes one or more heat sensitive components 210 coupled to it. In some embodiments, one or more heat sensitive components 210 are, or include, memory modules. In some embodiments, the one or more heat generating components 206 are, or include processors, power supply electronics, and/or flash controllers. In this embodiment, the first board is on a first plane and the second board is on a second plane substantially parallel to the fit first plane and is separated by a space 214.


In some embodiments, the assembly 200 is configured to be mechanically and/or electrically coupled to a base board (e.g., base board 208). In some embodiments, the base board is a mother board of a computer. In some embodiments, the base board is any circuit board to which the assembly 200 is configured to be coupled. In some embodiments, the assembly 200 is a daughter board assembly.


The first board 202 and second board 204 are mechanically and/or electrically coupled via a thermal barrier interconnect 211. For example, the assembly 200 includes a thermal barrier interconnect 211 that mechanically and/or electrically couples the first board 202 to the second board 204. In various embodiments, the thermal barrier interconnect 211 is a flexible board, flexible wire array, flexible PCB, flexible flat cable, ribbon cable (e.g., a flexible flat ribbon cable), or a combination thereof. The thermal barrier interconnect 211 can carry electrical signals between two boards (e.g., the first board 202 and the second board 204), or between other electronic components or sub-assemblies.


It will be understood that more or fewer flexible interconnects can be used to couple the boards of an electronic assembly in accordance with the ideas described in the instant application. For example, an electronic assembly may also include a fastener interconnect. One example of such an assembly is described herein with reference to FIG. 4.


Returning to FIGS. 3A and 3B, the boards 202, 204 have been configured such that a space 214 is formed between the first board 202, the second board 204. Furthermore, the second board 204 is located further away from the base board 208. Both of these features allow for better exposure to airflow and thus for lower temperature on the second board 204 in comparison to the first board 202.



FIG. 4 is side view of another exemplary electronic assembly, in accordance with some embodiments. FIG. 4 is similar to the embodiment of FIGS. 3A and 3B and includes the same elements described therein. It additionally includes at least one fastener 224. The fastener(s) are configured to couple the first circuit board 202 to the second circuit board 204, such that the fastener 224, first circuit board 202, second circuit board 204, and thermal barrier interconnect 211 surround the space 214 and form an air flow channel 216.


Air can then pass through this channel 216 (e.g., with a fan, compressed air, convection, etc.) in order to remove heat from the electronic components (such as the one or more heat generating components 206 and the one or more heat sensitive components 210). The one or more fastener(s) 224 include any structure(s), component(s), or device(s) that mechanically and/or electrically couple the first board 202 and the second board 204. For example, the one or more fastener(s) 224 can be any of the group consisting of: a clip, a screw, a bolt, a nut, a solder tab and/or soldered connection, adhesive, a slot, a hole, a peg, a protrusion, or the like (or any combination of the foregoing items). In some embodiments, the fastener(s) have low or no thermal conductivity. For instance, they may be made of an electrostatic (ESD) discharge plastic, a static dissipative plastic, a composite material, or the like.


It is noted that, in some embodiments the channel 216 is formed without the need for external supports, rails, brackets, or other hardware, reducing the cost and complexity of the assembly 200 while still providing the increased cooling capacity that is made possible by such a channel. In particular, because the channel 216 can be formed simply by joining the first board 202 and the second board 204, the assembly 200 can be more easily manufactured than structures that require more complicated mounting hardware. Moreover, because the entire assembly 200 can be soldered together the resulting assembly is more robust than an assembly that uses less secure mounting or attachment techniques. Specifically, the soldered connections may be more resistant to separation or loosening caused by the heating and cooling cycles that are frequently present in computer hardware.


As shown in FIG. 4, the channel 216 is supported on one side by the thermal barrier interconnect 211 (typically a flexible interconnect such as a flexible circuit board). For example, the thermal barrier interconnect 211 joins the first board 202 and the second board 204, and, when the assembly is formed into a channel 216, the thermal barrier interconnect 211 provides structural support to keep the first board 202 separate from the second board 204. Although the thermal barrier interconnect 211 is rigid enough to maintain separation of the first board 202 and the second board 204 when the assembly is completed, it is flexible enough to provide a pliable joint so that the boards can be moved with respect to one another without damaging the connections. This allows the boards to be manipulated with respect to one another for ease of installation and assembly. For example, the assembly 200 may be mounted to a base board (e.g., base board 208, FIG. 3A). Then the second board 204 is coupled to the first board 202 by means of one or more fasteners 224 to form the channel 216. Thus, in some embodiments, the thermal barrier interconnect 211 is flexible enough to allow the boards to be moved relative to one another, but are rigid enough to support the channel 216 under normal operating conditions and orientations (e.g., so that the channel 216 does not collapse).


In some embodiments, multiple assemblies 200 are combined to form a substantially continuous channel 216. For example, in some embodiments, several assemblies 200 are coupled to one or more base boards such that the respective channels 216 are substantially aligned, thus allowing air to pass through the respective channels. In some embodiments, where multiple assemblies 200 form a single channel, the assemblies 200 are coupled to one another so as to form a substantially continuous channel. For example, in some embodiments, gaskets, seals, rails, or any other appropriate components, are positioned between two adjacent assemblies in order to prevent air from escaping the channel.



FIG. 5 illustrates an exemplary flow chart of a method 500 for manufacturing and using an electronic assembly for dissipating heat, according to some embodiments. A first electronic assembly is provided (502). The electronic assembly includes a first circuit board (e.g., the first circuit board 202), a second circuit board (e.g., the second circuit board 204), and a thermal barrier interconnect (e.g., thermal barrier interconnect 211). In some embodiments, the electronic assembly also includes one or more fasteners (e.g., the one or more fastener(s) 224) (504).


Then the first circuit board is coupled to the second circuit board with the thermal barrier interconnect (506). In some embodiments, the first circuit board, the second circuit board, and the thermal barrier interconnect are next to one another in a substantially common plane as illustrated in FIG. 2.


In some embodiments, the second circuit board is coupled to a base circuit board (e.g., base board 208) (508).


In some embodiments, the electronic assembly (e.g., the second circuit board) is then manipulated (e.g., by machine or by hand) so as to cause the second circuit board to be positioned in a separate plane substantially parallel to the first circuit board (510). Manipulating the second circuit board so as to cause the second circuit board to be positioned substantially parallel to the first circuit board causes at least a portion of the thermal barrier interconnect 211 coupling the first circuit board to the second circuit board to be deformed as illustrated in FIGS. 3A and 3B.


In some embodiments, the first circuit board is coupled to the second circuit board with a fastener (e.g., the one or more fastener(s) 224), such that the first circuit board and the second circuit board are substantially parallel and are separated by a space 214, wherein the space forms at least part of a channel (e.g., channel 216) that is configured to direct airflow through the space between the first and second circuit boards as illustrated in FIG. 4 (512).


Thereafter, airflow is passed or directed (514) through the channel to dissipate heat, as described above.


It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, which changing the meaning of the description, so long as all occurrences of the “first contact” are renamed consistently and all occurrences of the second contact are renamed consistently. The first contact and the second contact are both contacts, but they are not the same contact.


The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof


As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting,” that a stated condition precedent is true, depending on the context. Similarly, the phrase “if it is determined [that a stated condition precedent is true]” or “if [a stated condition precedent is true]” or “when [a stated condition precedent is true]” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.


The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain principles of operation and practical applications, to thereby enable others skilled in the art.

Claims
  • 1. An electronic assembly for dissipating heat, comprising: a first rigid circuit board having a first predefined thermal conductivity, with one or more heat generating components coupled thereto;a second rigid circuit board having a second predefined thermal conductivity, with one or more heat sensitive components coupled thereto, wherein the one or more heat sensitive components are more sensitive to heat than the one or more heat generating components; anda flexible circuit board having a third predefined thermal conductivity, wherein the third predefined thermal conductivity is less than the first and second predefined thermal conductivities, the flexible circuit board electrically coupling the first rigid circuit board to the second rigid circuit board and forming, with the first and second rigid circuit boards, an airflow channel that directs airflow to dissipate heat generated by the one or more heat generating components.
  • 2. The electronic assembly of claim 1, wherein the flexible circuit board is made from a kapton material.
  • 3. The electronic assembly of claim 1, wherein the flexible circuit board is made from a polyimide material.
  • 4. The electronic assembly of claim 1, wherein the flexible circuit board has a lower thermal mass than the first and second rigid circuit boards.
  • 5. The electronic assembly of claim 1, wherein the flexible circuit board includes power planes for CORE voltage and the I/O voltage.
  • 6. The electronic assembly of claim 5, wherein the flexible circuit board does not include a plurality of power planes found in the first and second rigid circuit boards.
  • 7. The electronic assembly of claim 1, wherein the one or more heat generating components include one or more power supply electronic components.
  • 8. The electronic assembly of claim 1, wherein the one or more heat generating components include a NAND flash controller.
  • 9. The electronic assembly of claim 1, wherein the one or more heat sensitive components include NAND flash memory.
  • 10. The electronic assembly of claim 1, wherein the first rigid circuit board, the second rigid circuit board are disposed next to one another in a substantially common plane.
  • 11. The electronic assembly of claim 1, wherein the first rigid circuit board is on a first plane and the second rigid circuit board is on a second plane substantially parallel to the first plane and the first and second rigid circuit boards are separated by a space.
  • 12. The electronic assembly of claim 11, further comprising a fastener configured to couple the first rigid circuit board to the second rigid circuit board, wherein the fastener, first rigid circuit board, second rigid circuit board, and flexible circuit board surround the space and form the air flow channel.
  • 13. The electronic assembly of claim 1, wherein, in operation: the first rigid circuit board has a first temperature; andthe second rigid circuit board has a second temperature lower than the first temperature.
  • 14. The electronic assembly of claim 13, wherein, in operation, the second temperature is 5 to 20 degrees Celsius lower than the first temperature.
  • 15. The electronic assembly of claim 1, wherein the electronic assembly is a solid state disk drive.
  • 16. The electronic assembly of claim 1, wherein the electronic assembly does not include a case or a heat sink.
  • 17. The electronic assembly of claim 1, wherein at least one of the first rigid circuit board and second rigid circuit board comprises one or more solid state drives (SSDs) or one or more three-dimensional (3D) memory devices.
  • 18. A method of manufacturing an electronic assembly for dissipating heat, comprising: providing an electronic assembly, comprising: a first rigid circuit board having a first predefined thermal conductivity, with one or more heat generating components coupled thereto;a second rigid circuit board having a second predefined thermal conductivity, with one or more heat sensitive components coupled thereto, wherein the one or more heat sensitive components are more sensitive to heat than the one or more heat generating components; anda flexible circuit board having a third predefined thermal conductivity, wherein the third predefined thermal conductivity is less than the first and second predefined thermal conductivities;coupling the first rigid circuit board to the second rigid circuit board with the flexible circuit board; andforming, with the first and second rigid circuit boards and the flexible circuit board, an airflow channel that directs airflow to dissipate heat generated by the one or more heat generating components.
  • 19. The method of claim 18, wherein the electronic assembly is configured to operate so that the second rigid circuit board operates at a temperature that is 5 to 20 degrees Celsius lower than the temperature of the first rigid circuit board in a steady state operation.
  • 20. The method of claim 19, wherein at least one of the first rigid circuit board and the second rigid circuit board comprises one or more solid state drives (SSDs) or one or more three-dimensional (3D) memory devices.
  • 21. A method of dissipating heat from an electronic assembly, comprising: providing an electronic assembly, comprising: a first rigid circuit board having a first predefined thermal conductivity, with one or more heat generating components coupled thereto;a second rigid circuit board having a second predefined thermal conductivity, with one or more heat sensitive components coupled thereto, wherein the one or more heat sensitive components are more sensitive to heat than the one or more heat generating components; anda flexible circuit board having a third predefined thermal conductivity, wherein the third predefined thermal conductivity is less than the first and second predefined thermal conductivities, wherein the first rigid circuit board is coupled to the second rigid circuit board with the flexible circuit board; anddirecting airflow through a space formed between the first rigid circuit board and the second rigid circuit board to dissipate heat.
  • 22. The electronic assembly of claim 1, wherein the one or more heat generating components are coupled to one side of the first rigid circuit board, and the heat sensitive components are coupled to both sides of the second rigid circuit board.
  • 23. The electronic assembly of claim 22, wherein the first rigid circuit board is coupled to a base board.
RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent Application Ser. No. 61/953,691, filed Mar. 14, 2014, and titled “Thermal Isolation Techniques,” which is incorporated herein by reference in its entirety

US Referenced Citations (317)
Number Name Date Kind
4839587 Flatley et al. Jun 1989 A
4916652 Schwarz et al. Apr 1990 A
5210680 Scheibler May 1993 A
5489805 Hackitt et al. Feb 1996 A
5519847 Fandrich et al. May 1996 A
5530705 Malone Jun 1996 A
5537555 Landry Jul 1996 A
5551003 Mattson et al. Aug 1996 A
5628031 Kikinis et al. May 1997 A
5657332 Auclair et al. Aug 1997 A
5666114 Brodie et al. Sep 1997 A
5705850 Ashiwake et al. Jan 1998 A
5708849 Coke et al. Jan 1998 A
5763950 Fujisaki et al. Jun 1998 A
5828549 Gandre et al. Oct 1998 A
5923532 Nedved Jul 1999 A
5943692 Marberg et al. Aug 1999 A
5946190 Patel et al. Aug 1999 A
5973920 Altic et al. Oct 1999 A
5982664 Watanabe Nov 1999 A
6000006 Bruce et al. Dec 1999 A
6008987 Gale et al. Dec 1999 A
6009938 Smith et al. Jan 2000 A
6016560 Wada et al. Jan 2000 A
6018304 Bessios Jan 2000 A
6031730 Kroske Feb 2000 A
6058012 Cooper et al. May 2000 A
6061245 Ingraham et al. May 2000 A
6070074 Perahia et al. May 2000 A
6084773 Nelson et al. Jul 2000 A
6138261 Wilcoxson et al. Oct 2000 A
6182264 Ott Jan 2001 B1
6192092 Dizon et al. Feb 2001 B1
6295592 Jeddeloh et al. Sep 2001 B1
6311263 Barlow et al. Oct 2001 B1
6335862 Koya Jan 2002 B1
6411511 Chen Jun 2002 B1
6442076 Roohparvar Aug 2002 B1
6449625 Wang Sep 2002 B1
6484224 Robins et al. Nov 2002 B1
6507101 Morris Jan 2003 B1
6516437 Van Stralen et al. Feb 2003 B1
6528878 Daikoku et al. Mar 2003 B1
6541310 Lo et al. Apr 2003 B1
6570762 Cross et al. May 2003 B2
6618249 Fairchild Sep 2003 B2
6621705 Ballenger et al. Sep 2003 B1
6678788 O'Connell Jan 2004 B1
6757768 Potter et al. Jun 2004 B1
6762942 Smith Jul 2004 B1
6775792 Ulrich et al. Aug 2004 B2
6810440 Micalizzi, Jr. et al. Oct 2004 B2
6836808 Bunce et al. Dec 2004 B2
6836815 Purcell et al. Dec 2004 B1
6842436 Moeller Jan 2005 B2
6871257 Conley et al. Mar 2005 B2
6892801 Kim May 2005 B1
6895464 Chow et al. May 2005 B2
6934152 Barrow Aug 2005 B1
6978343 Ichiriu Dec 2005 B1
6980985 Amer-Yahia et al. Dec 2005 B1
6981205 Fukushima et al. Dec 2005 B2
6988171 Beardsley et al. Jan 2006 B2
6997720 Perret Feb 2006 B2
7020017 Chen et al. Mar 2006 B2
7030482 Haines Apr 2006 B2
7032123 Kane et al. Apr 2006 B2
7043505 Teague et al. May 2006 B1
7075788 Larson et al. Jul 2006 B2
7079972 Wood et al. Jul 2006 B1
7100002 Shrader et al. Aug 2006 B2
7111293 Hersh et al. Sep 2006 B1
7162678 Saliba Jan 2007 B2
7173852 Gorobets et al. Feb 2007 B2
7184446 Rashid et al. Feb 2007 B2
7233501 Ingalz Jun 2007 B1
7280364 Harris et al. Oct 2007 B2
7328377 Lewis et al. Feb 2008 B1
7474528 Olesiewicz Jan 2009 B1
7480147 Hoss et al. Jan 2009 B2
7516292 Kimura et al. Apr 2009 B2
7523157 Aguilar, Jr. et al. Apr 2009 B2
7527466 Simmons May 2009 B2
7529466 Takahashi May 2009 B2
7571277 Mizushima Aug 2009 B2
7574554 Tanaka et al. Aug 2009 B2
7595994 Sun Sep 2009 B1
7596643 Merry et al. Sep 2009 B2
7599182 Sun Oct 2009 B2
7623343 Chen Nov 2009 B2
7681106 Jarrar et al. Mar 2010 B2
7685494 Varnica et al. Mar 2010 B1
7707481 Kirschner et al. Apr 2010 B2
7761655 Mizushima et al. Jul 2010 B2
7774390 Shin Aug 2010 B2
7840762 Oh et al. Nov 2010 B2
7870326 Shin et al. Jan 2011 B2
7890818 Kong et al. Feb 2011 B2
7913022 Baxter Mar 2011 B1
7925960 Ho et al. Apr 2011 B2
7934052 Prins et al. Apr 2011 B2
7954041 Hong et al. May 2011 B2
7959445 Daily et al. Jun 2011 B1
7961462 Hernon Jun 2011 B2
7971112 Murata Jun 2011 B2
7974368 Shieh et al. Jul 2011 B2
7978516 Olbrich Jul 2011 B2
7980863 Holec Jul 2011 B1
7989709 Tsao Aug 2011 B2
7996642 Smith Aug 2011 B1
8000096 Nemoz Aug 2011 B2
8006161 Lestable et al. Aug 2011 B2
8032724 Smith Oct 2011 B1
8069390 Lin Nov 2011 B2
8190967 Hong et al. May 2012 B2
8198539 Otoshi et al. Jun 2012 B2
8208252 Tolliver Jun 2012 B2
8254181 Hwang et al. Aug 2012 B2
8305103 Kang et al. Nov 2012 B2
8312349 Reche et al. Nov 2012 B2
8373986 Sun Feb 2013 B2
8405985 Reynov et al. Mar 2013 B1
8412985 Bowers et al. Apr 2013 B1
8472183 Ross et al. Jun 2013 B1
8477495 Sun Jul 2013 B2
8570740 Cong et al. Oct 2013 B2
8599560 Wu Dec 2013 B2
9089073 Reynov et al. Jul 2015 B2
20020008963 DiBene, II et al. Jan 2002 A1
20020024846 Kawahara et al. Feb 2002 A1
20020076951 Roy Jun 2002 A1
20020083299 Van Huben et al. Jun 2002 A1
20020123259 Yatskov Sep 2002 A1
20020152305 Jackson et al. Oct 2002 A1
20020162075 Talagala et al. Oct 2002 A1
20020165896 Kim Nov 2002 A1
20030041299 Kanazawa et al. Feb 2003 A1
20030043829 Rashid Mar 2003 A1
20030088805 Majni et al. May 2003 A1
20030093628 Matter et al. May 2003 A1
20030184970 Bosch et al. Oct 2003 A1
20030188045 Jacobson Oct 2003 A1
20030189856 Cho et al. Oct 2003 A1
20030198100 Matsushita et al. Oct 2003 A1
20030212719 Yasuda et al. Nov 2003 A1
20040024957 Lin et al. Feb 2004 A1
20040024963 Talagala et al. Feb 2004 A1
20040073829 Olarig Apr 2004 A1
20040153902 Machado et al. Aug 2004 A1
20040181734 Saliba Sep 2004 A1
20040199714 Estakhri et al. Oct 2004 A1
20040218367 Lin et al. Nov 2004 A1
20040237018 Riley Nov 2004 A1
20050009382 Burmeister Jan 2005 A1
20050013120 Liu Jan 2005 A1
20050060456 Shrader et al. Mar 2005 A1
20050060501 Shrader Mar 2005 A1
20050082663 Wakiyama et al. Apr 2005 A1
20050114587 Chou et al. May 2005 A1
20050152112 Holmes et al. Jul 2005 A1
20050172065 Keays Aug 2005 A1
20050172207 Radke et al. Aug 2005 A1
20050193161 Lee et al. Sep 2005 A1
20050201148 Chen et al. Sep 2005 A1
20050231765 So et al. Oct 2005 A1
20050257120 Gorobets et al. Nov 2005 A1
20050273560 Hulbert et al. Dec 2005 A1
20050289314 Adusumilli et al. Dec 2005 A1
20060039196 Gorobets et al. Feb 2006 A1
20060042291 Petroski Mar 2006 A1
20060053246 Lee Mar 2006 A1
20060067066 Meier et al. Mar 2006 A1
20060085671 Majni et al. Apr 2006 A1
20060133041 Belady et al. Jun 2006 A1
20060136570 Pandya Jun 2006 A1
20060156177 Kottapalli et al. Jul 2006 A1
20060195650 Su et al. Aug 2006 A1
20060259528 Dussud et al. Nov 2006 A1
20070001282 Kang et al. Jan 2007 A1
20070011413 Nonaka et al. Jan 2007 A1
20070057686 Suga et al. Mar 2007 A1
20070058446 Hwang et al. Mar 2007 A1
20070061597 Holtzman et al. Mar 2007 A1
20070074850 Peschl Apr 2007 A1
20070076479 Kim et al. Apr 2007 A1
20070081408 Kwon et al. Apr 2007 A1
20070083697 Birrell et al. Apr 2007 A1
20070097653 Gilliland et al. May 2007 A1
20070113019 Beukema May 2007 A1
20070121297 Uchizono et al. May 2007 A1
20070133312 Roohparvar Jun 2007 A1
20070147113 Mokhlesi et al. Jun 2007 A1
20070150790 Gross et al. Jun 2007 A1
20070157064 Falik et al. Jul 2007 A1
20070174579 Shin Jul 2007 A1
20070180188 Fujibayashi et al. Aug 2007 A1
20070208901 Purcell et al. Sep 2007 A1
20070211426 Clayton et al. Sep 2007 A1
20070211436 Robinson et al. Sep 2007 A1
20070216005 Yim et al. Sep 2007 A1
20070216009 Ng Sep 2007 A1
20070230111 Starr et al. Oct 2007 A1
20070234143 Kim Oct 2007 A1
20070245061 Harriman Oct 2007 A1
20070246189 Lin et al. Oct 2007 A1
20070247805 Fujie et al. Oct 2007 A1
20070277036 Chamberlain et al. Nov 2007 A1
20070291556 Kamei Dec 2007 A1
20070294496 Goss et al. Dec 2007 A1
20070300130 Gorobets Dec 2007 A1
20080019095 Liu Jan 2008 A1
20080019182 Yanagidaira et al. Jan 2008 A1
20080022163 Tanaka et al. Jan 2008 A1
20080026637 Minich Jan 2008 A1
20080043435 Yip et al. Feb 2008 A1
20080052435 Norwood et al. Feb 2008 A1
20080052446 Lasser et al. Feb 2008 A1
20080068796 Pav et al. Mar 2008 A1
20080077841 Gonzalez et al. Mar 2008 A1
20080077937 Shin et al. Mar 2008 A1
20080086677 Yang et al. Apr 2008 A1
20080144371 Yeh et al. Jun 2008 A1
20080147964 Chow et al. Jun 2008 A1
20080147998 Jeong Jun 2008 A1
20080148124 Zhang et al. Jun 2008 A1
20080158818 Clidaras et al. Jul 2008 A1
20080163030 Lee Jul 2008 A1
20080168191 Biran et al. Jul 2008 A1
20080168319 Lee et al. Jul 2008 A1
20080170460 Oh et al. Jul 2008 A1
20080229000 Kim Sep 2008 A1
20080229003 Mizushima et al. Sep 2008 A1
20080229176 Arnez et al. Sep 2008 A1
20080236791 Wayman Oct 2008 A1
20080252324 Barabi et al. Oct 2008 A1
20080254573 Sir et al. Oct 2008 A1
20080266807 Lakin et al. Oct 2008 A1
20080270680 Chang Oct 2008 A1
20080282128 Lee et al. Nov 2008 A1
20080285351 Shlick et al. Nov 2008 A1
20080291636 Mori et al. Nov 2008 A1
20090003058 Kang Jan 2009 A1
20090037652 Yu et al. Feb 2009 A1
20090144598 Yoon et al. Jun 2009 A1
20090168525 Olbrich et al. Jul 2009 A1
20090172258 Olbrich et al. Jul 2009 A1
20090172259 Prins et al. Jul 2009 A1
20090172260 Olbrich et al. Jul 2009 A1
20090172261 Prins et al. Jul 2009 A1
20090172262 Olbrich et al. Jul 2009 A1
20090172308 Prins et al. Jul 2009 A1
20090172335 Kulkarni et al. Jul 2009 A1
20090172499 Olbrich et al. Jul 2009 A1
20090190308 Bhattacharya et al. Jul 2009 A1
20090193058 Reid Jul 2009 A1
20090207660 Hwang et al. Aug 2009 A1
20090222708 Yamaga Sep 2009 A1
20090228761 Perlmutter et al. Sep 2009 A1
20090273898 Imsand Nov 2009 A1
20090296466 Kim et al. Dec 2009 A1
20090296486 Kim et al. Dec 2009 A1
20090302458 Kubo et al. Dec 2009 A1
20090309214 Szewerenko et al. Dec 2009 A1
20090319864 Shrader Dec 2009 A1
20100008034 Hinkle Jan 2010 A1
20100061151 Miwa et al. Mar 2010 A1
20100073860 Moriai Mar 2010 A1
20100073880 Liu Mar 2010 A1
20100091463 Buresch et al. Apr 2010 A1
20100103737 Park Apr 2010 A1
20100118496 Lo May 2010 A1
20100161936 Royer et al. Jun 2010 A1
20100164525 Han et al. Jul 2010 A1
20100199125 Reche Aug 2010 A1
20100202196 Lee et al. Aug 2010 A1
20100208521 Kim et al. Aug 2010 A1
20100224985 Michael et al. Sep 2010 A1
20100262889 Bains Oct 2010 A1
20100281207 Miller et al. Nov 2010 A1
20100281342 Chang et al. Nov 2010 A1
20100296255 Maloney Nov 2010 A1
20100319986 Bleau et al. Dec 2010 A1
20100328887 Refai-Ahmed et al. Dec 2010 A1
20110083060 Sakurada et al. Apr 2011 A1
20110113281 Zhang et al. May 2011 A1
20110131444 Buch et al. Jun 2011 A1
20110132000 Deane et al. Jun 2011 A1
20110173378 Filor et al. Jul 2011 A1
20110182035 Yajima Jul 2011 A1
20110188205 MacManus et al. Aug 2011 A1
20110205823 Hemink et al. Aug 2011 A1
20110213920 Frost et al. Sep 2011 A1
20110228601 Olbrich et al. Sep 2011 A1
20110231600 Tanaka et al. Sep 2011 A1
20110299244 Dede et al. Dec 2011 A1
20110317359 Wei et al. Dec 2011 A1
20120014067 Siracki Jan 2012 A1
20120064781 Krishnan Mar 2012 A1
20120096217 Son et al. Apr 2012 A1
20120110250 Sabbag et al. May 2012 A1
20120151253 Horn Jun 2012 A1
20120170224 Fowler et al. Jul 2012 A1
20120195126 Roohparvar Aug 2012 A1
20120201007 Yeh et al. Aug 2012 A1
20120239976 Cometti et al. Sep 2012 A1
20120284587 Yu et al. Nov 2012 A1
20120293962 McCluskey et al. Nov 2012 A1
20120327598 Nakayama Dec 2012 A1
20130155800 Shim Jun 2013 A1
20130181733 Kikuchi et al. Jul 2013 A1
20130285686 Malik et al. Oct 2013 A1
20130294028 Lafont et al. Nov 2013 A1
20130307060 Wang et al. Nov 2013 A1
20140055944 McCabe et al. Feb 2014 A1
20140071614 Kaldani Mar 2014 A1
20140153181 Peng et al. Jun 2014 A1
20140182814 Lin Jul 2014 A1
Foreign Referenced Citations (29)
Number Date Country
201 655 782 Nov 2010 CN
102 446 873 May 2012 CN
199 10 500 Oct 2000 DE
2005 063281 Jul 2007 DE
0 600 590 Jun 1994 EP
0 989 794 Mar 2000 EP
1 465 203 Oct 2004 EP
1 990 921 Nov 2008 EP
2 066 158 Jun 2009 EP
2 395 827 Dec 2011 EP
2 600 700 Jun 2013 EP
2560731 Sep 1985 FR
06006064 Jan 1994 JP
2002-532806 Oct 2002 JP
2003 188565 Jul 2003 JP
WO 88 07193 Mar 1988 WO
WO 03094586 Nov 2003 WO
WO 2004086827 Oct 2004 WO
WO 2007036834 Apr 2007 WO
WO 2007080586 Jul 2007 WO
WO 2008013850 Jan 2008 WO
WO 2008121553 Oct 2008 WO
WO 2008121577 Oct 2008 WO
WO 2009028281 Mar 2009 WO
WO 2009032945 Mar 2009 WO
WO 2009058140 May 2009 WO
WO 2009084724 Jul 2009 WO
WO 2009134576 Nov 2009 WO
WO 2013080341 Jun 2013 WO
Non-Patent Literature Citations (48)
Entry
International Search Report and Written Opinion dated Dec. 16, 2014, received in International Patent Application No. PCT/US2014/059114, which corresponds to U.S. Appl. No. 14/135,223, 9 pages (Dean).
International Search Report and Written Opinion dated Nov. 20, 2014, received in International Patent Application No. PCT/US2014/020290, which corresponds to U.S. Appl. No. 13/791,797, 21 pages (Dean).
International Search Report and Written Opinion dated Dec. 23, 2014, received in International Patent Application No. PCT/US2014/042772, which corresponds to U.S. Appl. No. 13/922,105, 10 pages (Dean).
Barr, “Introduction to Watchdog Timers,” Oct. 2001, 3 pgs.
Canim, “Buffered Bloom Filters on Solid State Storage,” ADMS*10, Singapore Sep. 13-17, 2010, 8 pgs.
Kang, “A Multi-Channel Architecture for High-Performance NAND Flash-Based Storage System,” J. Syst. Archit, vol. 53, issue 9, Sep. 2007, 15 pgs.
Kim, “A Space-Efficient Flash Translation Layer for CompactFlash Systems,” May 2002, IEEE Vol. 48, No. 2, 10 pgs.
Lu, “A Forest-structured Bloom Filter with Flash Memory,” MSST 2011. Denver, CO, May 23-27, 2011, article, 6 pgs.
Lu, “A Forest-structured Bloom Filter with Flash Memory,” MSST 2011, Denver, CO, May 23-27, 2011, presentation slides, 25 pgs.
McLean, “Information Technology-AT Attachment with Packet Interface Extension,” Aug. 19, 1998, 339 pgs.
Microchip Technology. “Section 10, Watchdog Timer and Power-Saving Modes,” 2005, 14 pages.
Park et al., “A High Performance Controller for NAND Flash-Based Solid State Disk (NSSD),” Proceedings of Non-Volatile Semiconductor Memory Workshop, Feb. 2006. 4 pgs.
Zeidman, “Verilog Designer's Library,” 1999, 9 pgs.
International Search Report and Written Opinion, dated Mar. 19, 2009 received in International Patent Appiication No. PCT/US08/88133, which corresponds to U.S. Appl. No. 12/082,202, 7 pgs (Prins).
International Search Report and Written Opinion, dated Mar. 19, 2009, received in International Patent Application No. PCT/US08/88136, which corresponds to U.S. Appl. No. 12/082,205, 7 pgs (Oibrich).
International Search Report and Written Opinion dated Feb. 26, 2009, received in International Patent Application No. PCT/US08/88146, which corresponds to U.S. Appl. No. 12/082,221, 10 pgs (Prins).
International Search Report and Written Opinion dated Feb. 27, 2009, received in International Patent Application No. PCT/US2008/088154, which corresponds to U.S. Appl. No. 12/082,207, 8 pgs (Prins).
International Search Report and Written Opinion dated Feb. 13, 2009, received in International Patent Application No. PCT/US08/88164, which corresponds to U.S. Appl. No. 12/082,220, 6 pgs (Olbrich).
International Search Report and Written Opinion dated Feb. 18, 2009, received in International Patent Application No. PCT/US08/88206, which corresponds to U.S. Appl. No. 12/082,206, 8 pgs (Prins).
International Search Report and Written Opinion dated Feb. 19, 2009, received in International Patent Application No. PCT/US08/88217, which corresponds to U.S. Appl. No. 12/082,204, 7 pgs (Olbrich).
International Search Report and Written Opinion dated Feb. 13, 2009, received in International Patent Application No. PCT/US08/88229, which corresponds to U.S. Appl. No. 12/082,223, 7 pgs (Olbrich).
International Search Report and Written Opinion dated Feb. 19, 2009, received in International Patent Application No. PCT/US08/88232, which corresponds to U.S. Appl. No. 12/082,222, 8 pgs (Olbrich).
International Search Report and Written Opinion dated Feb. 19, 2009, received in International Patent Application No. PCT/US08/88236, which corresponds to U.S. Appl. No. 12/082,203, 7 pgs (Olbrich).
International Search Report and Written Opinion dated Oct. 27, 2011, received in International Patent Application No. PCT/US2011/028637, which corresponds to U.S. Appl. No. 12/726,200, 11 pgs (Olbrich).
European Search Report dated Feb. 23, 2012, received in European Patent Application No. 08866997.3, which corresponds to U.S. Appl. No. 12/082,207, 6 pgs. (Prins).
Office Action dated Apr. 18, 2012, received in Chinese Patent Application No. 200880127623.8, which cirresponds to U.S. Appl. No. 12/082,207, 12 pgs. (Prins).
Office Action dated Dec. 31, 2012, received in Chinese Patent Application No. 200880127623.8, which correspods to U.S. Appl. No. 12/082,207, 9 pgs (Prins).
Notification of the Decision to Grant a Patent Right for Patent for Invention dated Jul. 4, 2013, received in Chinese Patent Application No. 200880127623.8, which corresponds to U.S. Appl. No. 12/082,207, 1 pg (Prins).
Office Action dated Jul. 24, 2012, received in Japanese Patent Application No. JP 2010-540863, 3 pgs (Prins).
International Search Report and Written Opinion dated Mar. 7, 2014, received in International Patent Application No. PCT/US2013/074772, which corresponds to U.S. Appl. No. 13/831,218, 10 pages (George).
International Search Report and Written Opinion dated Mar. 24, 2014, received in International Patent Application No. PCT/US2013/074777, which corresponds to U.S. Appl. No. 13/831,308, 10 pages (George).
International Search Report and Written Opinion dated Mar. 7, 2014, received in International Patent Application No. PCT/US2013/074779, which corresponds to U.S. Appl. No. 13/831,374, 8 pages (George).
International Search Report and Written Opinion dated Aug. 31, 2012, received in International Patent Application PCT/US2012/042764, which corresponds to U.S. Appl. No. 13/285,873, 12 pgs (Frayer).
International Search Report and Written Opinion dated Mar. 4, 2013, received in PCT/US2012/042771, which corresponds to U.S. Appl. No. 13/286,012, 14 pgs (Stonelake).
International Search Report and Written Opinion dated Sep. 26, 2012, received in International Patent Application No. PCT/US2012/042775, which corresponds to U.S. Appl. No. 13/285,892, 8 pgs (Weston-Lewis et al.).
International Search Report and Written Opinion dated Jun. 6, 2013, received in International Patent Application No. PCT/US2012/059447, which corresponds to U.S. Appl. No. 13/602,031, 12 pgs (Tai).
International Search Report and Written Opinon dated Jun. 6, 2013, received in International Patent Application No. PCT/US2012/059453, which corresponds to U.S. Appl. No. 13/602,039, 12 pgs (Frayer).
International Search Report and Written Opinion dated Feb. 14, 2013, received in International Patent Application No. PCT/US2012/059459, which corresponds to U.S. Appl. No. 13/602,047, 9 pgs (Tai).
International Search Report and Written Opinion dated May 23, 2013, received in International Patent Application No. PCT/US2012/065914, which corresponds to U.S. Appl. No. 13/679,963, 7 pgs (Frayer).
International Search Report and Written Opinion dated Apr. 5, 2013, received in International Patent Application No. PCT/US2012/065916, which corresponds to U.S. Appl. No. 13/679,969, 7 pgs (Frayer).
International Search Report and Written Opinion dated Jun. 17, 2013, received in International Patent Application No. PCT/US2012/065919, which corresponds to U.S. Appl. No. 13/679,970, 8 pgs (Frayer).
International Search Report and Written Opinion dated May 18, 2015, received in International Patent Application No. PCT/US2015/016656, which corresponds to U.S. Appl. No. 14/275,690, 14 pages (Wright).
International Search Report and Written Opinion dated May 28, 2015, received in International Patent Application No. PCT/US2015/017729, which corresponds to U.S. Appl. No. 14/244,745, 14 pages (Ellis).
International Search Report and Written Opinion dated Apr. 28, 2015 received in International Patent Application No. PCT/US2015/014563, which corresponds to U.S. Appl. No. 14/179,247, 9 pages (Ellis).
International Search Report and Written Opinion dated May 8, 2015, received in International Patent Application No. PCT/US2015/017722, which corresponds to U.S. Appl. No. 14/277,716, 9 pages (Dean).
International Search Report and Written Opinion dated May 13, 2015, received in International Patent Application No. PCT/US2015/017724, which corresponds to U.S. Appl. No. 14/244,734 12 pages, (Dean).
Invitation to Pay Additional Fees dated Jul. 25, 2014, received in International Patent Application No. PCT/US2014/021290, which corresponds to U.S. Appl. No. 13/791,797, 8 pages (Dean).
International Search Report and Written Opinion dated Sep. 12, 2014, received in International Patent Application No. PCT/US2014/043146.
Related Publications (1)
Number Date Country
20150261266 A1 Sep 2015 US
Provisional Applications (1)
Number Date Country
61953691 Mar 2014 US