1. Field of the Invention
The present invention relates to a thermal print head.
2. Description of the Related Art
A conventionally known thermal print head includes a substrate, a resistor layer, and a wiring layer. Such a thermal print head is disclosed in JP-A-2012-51319, for example. In the thermal print head disclosed in this patent publication, the resistor layer and the wiring layer are formed on the substrate. The resistor layer has a plurality of heat generating portions arranged in the main scanning direction.
In use, a thermal print head is arranged in proximity to a platen roller configured to press a printing medium (on which printing is to be performed) against the heat generating portions. If interference occurs between such an external element and the thermal print head, it may cause problems such as an undesired interruption of the printing process.
The present invention has been proposed under the above circumstances, and an object thereof is to provide a thermal print head capable of avoiding interference with external elements.
According to an aspect of the present invention, there is provided a thermal print head including: a semiconductor substrate; a resistor layer formed on the semiconductor substrate and including a plurality of heat generating portions arranged in a main scanning direction; a wiring layer formed on the semiconductor substrate and included in a conduction path for energizing the plurality of heat generating portions; and an insulating protective layer covering the wiring layer and the resistor layer. The semiconductor substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. A projection is formed to project from the obverse surface of the substrate in the thickness direction, where the projection is elongated in the main scanning direction. The projection includes a top surface, a first inclined side surface, and a second inclined side surface, where the top surface is parallel to the obverse surface of the substrate and spaced apart from the same obverse surface in the thickness direction. The first inclined side surface and the second inclined side surface are spaced apart from each other in a sub-scanning direction, with the top surface intervening therebetween. Each of the first and the second inclined side surfaces is inclined relative to the obverse surface of the substrate. The plurality of heat generating portions are arranged to overlap with the first inclined side surface as viewed in the thickness direction.
Further features and advantages of the present invention will become apparent from the following detailed description with reference to the attached drawings.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
The semiconductor substrate 1 is made of a semiconductor material having a resistivity that allows for conduction. Examples of such a semiconductor substrate include Si doped with a metallic element. The semiconductor substrate 1 has an obverse surface 11, a reverse surface 12, and a projection 13.
The obverse surface 11 and the reverse surface 12 face away from each other in a thickness direction z. The projection 13 projects from the obverse surface 11 in the thickness direction z. The projection 13 is elongated in a main scanning direction x.
The obverse surface 11 has a first region 111 and a second region 112, which are spaced apart from each other in a sub-scanning direction with the projection 13 therebetween.
The projection 13 has a top surface 130, a first inclined side surface 131, and a second inclined side surface 132. The top surface 130 is parallel to the obverse surface 11, and is spaced apart from the obverse surface 11 in the thickness direction. The first inclined side surface 131 is located between the top surface 130 and the first region 111, and is inclined relative to the obverse surface 11. The second inclined side surface 132 is located between the top surface 130 and the second region 112, and is inclined relative to the obverse surface 11.
In the present embodiment, a (100) surface is selected as the obverse surface 11. In addition, the first inclined side surface 131 and the second inclined side surface 132 form the same angle with the top surface 130 and the obverse surface 11, such as an angle of 54.7°.
The obverse surface 11 has the first region 111 and the second region 112. The first region 111 and the second region 112 are partitioned by the projection 13. In the present embodiment, the second region 112 is larger than the first region 111 in dimension in the sub-scanning direction y and area.
The semiconductor substrate 1 is not particularly limited in terms of dimensions, and may have dimensions of approximately 2.0 mm to 3.0 mm in the sub-scanning direction y and approximately 100 mm to 150 mm in the direction x. The distance between the obverse surface 11 and the reverse surface 12 in the thickness direction z is approximately 400 μm to 500 μm, and the height of the projection 13 in the thickness direction z is approximately 250 μm to 400 μm.
The insulation layer 2 is arranged between a group of the obverse surface 11 and projection 13 of the semiconductor substrate 1 and a group of the wiring layer 3 and the resistor layer 4. The insulation layer 2 is made of an insulation material, such as SiO2 or SiN. The insulation layer 2 is not particularly limited in terms of thickness, and may have a thickness of approximately 5 μm to 10 μm, for example.
The insulation layer 2 has a common-electrode first opening 21 and a common-electrode second opening 22. The common-electrode first opening 21 extends through the insulation layer 2 in the thickness direction z. In the present embodiment, the common-electrode first opening 21 overlaps with the first region 111 as viewed in the thickness direction z. The common-electrode first opening 21 is elongated in the main scanning direction x, and may be a slit, for example.
The common-electrode second opening 22 extends through the insulation layer 2 in the thickness direction z. In the present embodiment, the common-electrode second opening 22 overlaps with the second region 112 as viewed in the thickness direction z.
The resistor layer 4 is supported by the semiconductor substrate 1, and is formed on the insulation layer 2 in the present embodiment. The resistor layer 4 has a plurality of heat generating portions 41. The heat generating portions 41 are individually and selectively energized and thereby heat the printing medium 992 locally. The heat generating portions 41 are arranged along the main scanning direction x. In the present embodiment, the heat generating portions 41 overlap with the projection 13 as viewed in the thickness direction z. More specifically, the heat generating portions 41 overlap entirely with the first inclined side surface 131. The resistor layer 4 is made of TaN, for example.
The heat generating portions 41 are not particularly limited in terms of shape. In one example shown in
In the present embodiment, the resistor layer 4 has a resistor-side first through-conductive portion 421 and a resistor-side second through-conductive portion 422. The resistor-side first through-conductive portion 421 is in contact with the first region 111 of the obverse surface 11 of the semiconductor substrate 1, via the common-electrode first opening 21. The resistor-side second through-conductive portion 422 is in contact with the second region 112 of the obverse surface 11 of the semiconductor substrate 1, via the common-electrode second opening 22.
The wiring layer 3 forms a conduction path for energizing the heat generating portions 41. The wiring layer 3 is supported by the semiconductor substrate 1, and is stacked on the resistor layer 4 in the present embodiment. Note that the wiring layer 3 may be arranged between the semiconductor substrate 1 and the resistor layer 4. The wiring layer 3 is made of a metallic material having a lower resistance than the resistor layer 4, such as Cu. The wiring layer 3 may have a Cu layer and a Ti layer, where the Ti layer is disposed between the Cu layer and the resistor layer 4.
The wiring layer 3 has a plurality of individual electrodes 31 and a common electrode 32. The plurality of individual electrodes 31 are connected one-to-one to the plurality of heat generating portions 41. In the present embodiment, the plurality of individual electrodes 31 are positioned closer to the second region 112 than the heat generating portions 41 are in the sub-scanning direction y. The plurality of individual electrodes 31 partially overlap with the first inclined side surface 131 as viewed in the thickness direction z.
The common electrode 32 has a portion located opposite to the plurality of individual electrodes 31 with the heat generating portions 41 therebetween in the sub-scanning direction y. In addition, the common electrode 32 in the present embodiment has a portion located closer to the second region 112 (i.e., in the left side of
As can be understood from
In the present embodiment, the common electrode 32 has a wiring-side first through-conductive portion 321 and a wiring-side second through-conductive portion 322. The wiring-side first through-conductive portion 321 is in contact with the resistor-side first through-conductive portion 421 of the resistor layer 4. The wiring-side second through-conductive portion 322 is in contact with the resistor-side second through-conductive portion 422 of the resistor layer 4. With such a structure, a portion of the common electrode 32 of the wiring layer 3 that overlaps with the first region 111 as viewed in the thickness direction z is electrically connected to the semiconductor substrate 1 via the resistor-side first through-conductive portion 421 in the common-electrode first opening 21 of the insulation layer 2. Also, a portion of the common electrode 32 that overlaps with the second region 112 is electrically connected to the semiconductor substrate 1 via the resistor-side second through-conductive portion 422 in the common-electrode second opening 22 of the insulation layer 2. Accordingly, in the present embodiment, the conduction path for energizing the heat generating portions 41 includes the wiring layer 3 and the semiconductor substrate 1. More specifically, the current flowing through the common electrode 32 passes through the semiconductor substrate 1.
The insulating protective layer 5 covers the wiring layer 3 and the resistor layer 4. The insulating protective layer 5 is made of an insulating material, and protects the wiring layer 3 and the resistor layer 4. The insulating protective layer 5 is made of SiO2, for example.
The insulating protective layer 5 has a conductive-protective-layer opening 51, a plurality of control element openings 52, and a plurality of wiring member openings 53. The conductive-protective-layer opening 51 overlaps with the first region 111 as viewed in the thickness direction z, allowing the common electrode 32 to be exposed. The conductive-protective-layer opening 51 is elongated in the main scanning direction x, for example. In the illustrative example, the conductive-protective-layer opening 51 overlaps with the common-electrode first opening 21 as viewed in the thickness direction z. The control element openings 52 overlap with the second region 112 as viewed in the thickness direction z, allowing the plurality of individual electrodes 31 and the common electrode 32 to be exposed.
The plurality of wiring member openings 53 are arranged opposite to the heat generating portions 41 relative to the control element openings 52 in the sub-scanning direction y. The plurality of wiring member openings 53 allow the common electrode 32 of the wiring layer 3 and other portions of the wiring layer 3 to be exposed. Specifically, the other portions of the wiring layer 3 are arranged at positions different from the position of the common electrode 32, and are insulated from the common electrode 32.
The conductive protective layer 6 overlaps with the plurality of heat generating portions 41 as viewed in the thickness direction z and is stack on the insulating protective layer 5. The conductive protective layer 6 is made of a conductive material, such as AlN. The conductive protective layer 6 has a portion overlapping with the first region 111 as viewed in the thickness direction z, and has a protective layer through-conductive portion 61. The protective layer through-conductive portion 61 is in contact with the common electrode 32 via the conductive-protective-layer opening 51.
The plurality of control elements 7 are electrically connected to the wiring layer 3 and individually energize the heat generating portions 41. The plurality of control elements 7 are arranged in the main scanning direction x. The plurality of control elements 7 overlap with the common-electrode second opening 22 as viewed in the thickness direction z.
In the present embodiment, the thermal print head A1 has control element pads 381. The control element pads 381 are made of metal such as Cu or Ni, and are formed in the control element openings 52. The control elements 7 each have a plurality of control element electrodes 71. The control element electrodes 71 are conductively bonded to the control element pads 381 with a conductive bonding material 79. The conductive bonding material 79 is solder, for example.
In the present embodiment, the control elements 7 are located closer to the semiconductor substrate 1 in the thickness direction z than a conductive protective layer surface S6 which is an upper surface of the conductive protective layer 6 in the thickness direction z. In addition, the control elements 7 are located closer to the semiconductor substrate 1 in the thickness direction z than a resistor layer surface S4 which is an upper surface of the resistor layer 4 in the thickness direction z.
The wiring member 92 electrically connects the wiring layer 3 to, for example, a power supply unit (not shown) of a printer. The wiring member 92 is a printed wiring board, for example. The wiring member 92 as described above has a resin layer 921, a wiring layer 922, and a protective layer 923, for example. The resin layer 921 is made of a flexible resin. The wiring layer 922 is stacked on one surface of the resin layer 921, and is made of metal such as Cu. The protective layer 923 is stacked on another surface of the resin layer that is located opposite to the surface on which the wiring layer 922 is stacked. The protective layer 923 protects the resin layer 921 and the wiring layer 922.
The thermal print head A1 has a wiring member pad 382. The wiring member pad 382 is formed in one of the wiring member openings 53 of the insulating protective layer 5, and is made of metal such as Cu or Ni. The wiring layer 922 of the wiring member 92 is conductively bonded to the wiring member pad 382. Note that the thermal print head A1 has more than one wiring member pad 382. The wiring member pad 382 shown in
The supporting member 91 supports the semiconductor substrate 1. The supporting member 91 is made of metal such as Al. The supporting member 91 has a recess 911. The recess 911 accommodates and supports the semiconductor substrate 1. The semiconductor substrate 1 is bonded to the recess 911 with a bonding layer 919, for example. It is preferable that the bonding layer 919 conduct the heat from the semiconductor substrate 1 to the supporting member 91 and insulate the semiconductor substrate 1 from the supporting member 91. Examples of such a bonding layer 919 include resin adhesive.
The supporting member 91 is not particularly limited in terms of dimensions, and may have dimensions of approximately 5.0 mm to 8.0 mm in the sub-scanning direction y, approximately 100 mm to 150 mm in the direction x, and approximately 2.0 mm to 4.0 mm in the thickness direction z.
The protective resin 8 protects the control elements 7, and is made of an insulating resin, for example. In addition, the protective resin 8 overlaps the second inclined side surface 132 of the projection 13 as viewed in the thickness direction z, allowing the top surface 130 to be exposed. In the present embodiment, the protective resin 8 covers portions of the wiring members 92.
The following describes an example of a method for manufacturing the thermal print head A1, with reference to
First, a semiconductor substrate material is prepared. The semiconductor substrate material is made of a low resistant semiconductor material, such as Si doped with a metallic element. The semiconductor substrate material has a (100) surface. After the (100) surface is covered with a predetermined mask layer, anisotropic etching with KOH is performed. This yields the semiconductor substrate 1 shown in
Next, the insulation layer 2 is formed as shown in
Next, the resistor layer 4 is formed as shown in
Next, the wiring layer 3 is formed to cover the resistor layer 4 as shown in
Next, the insulating protective layer 5 is formed as shown in
Next, the conductive protective layer 6 is formed as shown in
Next, the advantages of the thermal print head A1 will be described.
According to the present embodiment, the heat generating portions 41 overlap with the first inclined side surface 131 as viewed in the thickness direction z. Consequently, as shown in
Since the plurality of control elements 7 are arranged in the second region 112, the platen roller 991 and the printing medium 992 can be arranged opposite to the plurality of control elements 7 with the projection 13 therebetween. Such an arrangement is suitable in preventing the aforementioned interference. Also, the control elements 7 are positioned closer to the obverse surface 11 in the thickness direction z than the conductive protective layer surface S6 is. This is suitable in preventing the interference. Furthermore, the control elements 7 are positioned closer to the obverse surface 11 in the thickness direction z than the resistor layer surface S4 is. This is suitable in preventing the control elements 7 from interfering with the platen roller 991 and the printing medium 992.
In addition, the conduction path for energizing the heat generating portions 41 includes the semiconductor substrate 1. Energization by means of the semiconductor substrate 1 eliminates the need to form an equivalent energizing portion in the wiring layer 3. This makes it possible to reduce the area of the wiring layer 3 disposed over the obverse surface 11. This provides a sufficient area for forming the wiring layer 3, which facilitates the forming of the wiring layer 3 in response to the downsizing and pitch-narrowing of the heat generating portions 41. As such, fine printing is achieved.
The semiconductor substrate 1 is electrically connected to the common electrode 32. The common electrode 32 is electrically connected to all of the heat generating portions 41. This eliminates needs such as to divide the semiconductor substrate 1 into a plurality of portions that are insulated from each other.
The semiconductor substrate 1 is in contact with the wiring-side first through-conductive portion 321 and the wiring-side second through-conductive portion 322 via the common-electrode first opening 21 and the common-electrode second opening 22. The common-electrode first opening 21 and the common-electrode second opening 22 sandwich the heat generating portions 41 in the sub-scanning direction y. Similarly, the wiring-side first through-conductive portion 321 and the wiring-side second through-conductive portion 322 sandwich the heat generating portions 41 in the sub-scanning direction y. With such an arrangement, a portion of the conduction path formed by the semiconductor substrate 1 bypasses the heat generating portions 41 in the thickness direction z. This is suitable in downsizing and pitch-narrowing of the heat generating portions 41.
Furthermore, the portion of the conduction path formed by the semiconductor substrate 1 overlaps with the plurality of control elements 7 as viewed in the thickness direction z. This suppresses interference between the wiring layer 3 and the plurality of control elements 7.
The common-electrode first opening 21 is elongated in the main scanning direction x. This reduces contact resistance between the wiring layer 3 and the semiconductor substrate 1.
The insulating protective layer 5 is electrically connected to the common electrode 32 of the wiring layer 3 via the protective layer through-conductive portion 61. The insulating protective layer 5 rubs against the printing medium 992, and therefore is likely to build up static charges. These static charges can be appropriately released to the common electrode 32 of the wiring layer 3.
Regarding a thermal print head A2 in
In the present embodiment, the common-electrode first opening 21 of the insulation layer 2, the wiring-side first through-conductive portion 321 of the wiring layer 3, the resistor-side first through-conductive portion 421 of the resistor layer 4, the conductive-protective-layer opening 51 of the insulating protective layer 5, and the protective layer through-conductive portion 61 of the conductive protective layer 6 overlap with the first inclined side surface 131 as viewed in the thickness direction z.
Such an embodiment can also prevent interference with external elements. In particular, since the first inclined side surface 131 is positioned at the end of the semiconductor substrate 1 in the sub-scanning direction y, interference with external elements can be more reliably prevented.
The thermal print head of the present invention is not limited to those described in the above embodiments. Various design changes can be made to the specific configurations of the elements of the thermal print head according to the present invention.
Number | Date | Country | Kind |
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2015-253733 | Dec 2015 | JP | national |
Number | Name | Date | Kind |
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5791793 | Nagahata | Aug 1998 | A |
6753893 | Kitazawa | Jun 2004 | B1 |
7502044 | Shintani | Mar 2009 | B2 |
7990405 | Fukumoto | Aug 2011 | B2 |
Number | Date | Country |
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2012051319 | Mar 2012 | JP |
Number | Date | Country | |
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20170182795 A1 | Jun 2017 | US |