Patent Application
20250006776
Disclosed implementations relate generally to the field of semiconductor devices and fabrication. More particularly, but not exclusively, the disclosed implementations relate to an IC device having an integrated thermistor and a bias resistor in a voltage divider configuration.
Thermistors are temperature sensing components that have resistance configured to change with temperature, e.g., having a high temperature coefficient of resistance (TCR) over a suitable range. Thermistors are sometimes used in voltage divider circuits with a bias reference resistor that does not change the resistance (or changes very little) with respect to temperature in an operational range, thereby exhibiting a low or zero TCR. Thermistors and reference resistors are often fabricated as blocks of ceramic material or blocks of silicon that are provided as separate, discrete components on a circuit board, thereby requiring additional space for purchase and mounting of two separate products.
The following presents a simplified summary in order to provide a basic understanding of some examples of the present disclosure. This summary is not an extensive overview of the examples, and is neither intended to identify key or critical elements of the examples, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the present disclosure in a simplified form as a prelude to a more detailed description that is presented in subsequent sections further below.
In one example, an electronic device comprises a thermistor including a well region having a first conductivity type extending into a semiconductor substrate layer (e.g., a single-crystal silicon layer) having an opposite second conductivity type, and first and second terminals connected to the well region a separated by a resistive portion of the well region; and a thin-film bias resistor conductively connected to the first terminal, wherein the bias resistor is formed in a region of the substrate isolated from the n-well region.
In one example, a method of fabricating an electronic device is disclosed. The method comprises forming a thermistor over a semiconductor substrate, the thermistor including a well region having a first conductivity type and extending into a substrate layer having a different second conductivity type; and forming a thin-film bias resistor over a dielectric layer over the substrate, the bias resistor conductively connected to a terminal of the thermistor. In one implementation, the thermistor has a first TCR of at least 6000 ppm/° C. and the bias resistor has a second TCR no greater than ±100 ppm/° C. In one implementation, the thermistor terminal may include a first metal silicide and the bias resistor may comprise a different second metal silicide. In one implementation, the bias resistor may be formed such that it is located directly on a shallow trench isolation (STI) structure. In one implementation, the bias resistor is formed such that it is vertically located directly over the well region. In one implementation, the bias resistor includes a silicon-chromium (SiCr) film having a thickness of ranging from about 3 nm to about 4 nm.
In one example, an electronic device including a thermistor and a bias reference resistor in a voltage divider configuration integrated into a single semiconductor die is disclosed. In one implementation, the electronic device may comprise a substrate including an n-well region, a thermistor formed in the n-well region, and a bias reference resistor connected in series to the thermistor, wherein the bias reference resistor is formed in a region of the substrate isolated from the n-well region, e.g., either laterally, horizontally, and/or vertically. In one arrangement, the thermistor may comprise a well resistor in the n-well region doped with appropriate dopants for providing a high TCR. In one arrangement, the bias reference resistor may comprise a thin-film bias resistor having a resistor body formed from a SiCr film, e.g., with a thickness of about 3 nm to about 4 nm, that is annealed to provide a low or zero TCR. In one arrangement, the series-coupled thermistor and bias reference resistor may be disposed between a first reference voltage rail and a second reference voltage rail. In another example, a method of fabricating an integrated thermistor and a bias reference resistor in the same process flow is disclosed, wherein the thermistor and/or the bias reference resistor may be independently tuned to achieve appropriate respective target resistances.
Implementations of the present disclosure are illustrated by way of example, and not by way of limitation, in the Figures of the accompanying drawings. It should be noted that different references to “an” or “one” implementation in this disclosure are not necessarily to the same implementation, and such references may mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an implementation, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other implementations whether or not explicitly described.
The accompanying drawings are incorporated into and form a part of the specification to illustrate one or more example implementations of the present disclosure. Various advantages and features of the disclosure will be understood from the following Detailed Description taken in connection with the appended claims and with reference to the attached drawing Figures in which:
Examples of the disclosure are described with reference to the attached Figures wherein like reference numerals are generally utilized to refer to like elements. The Figures are not drawn to scale and they are provided merely to illustrate examples. Numerous specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, it should be understood that some examples may be practiced without such specific details. In other instances, well-known subsystems, components, structures and techniques have not been shown in detail in order not to obscure the understanding of the examples. Accordingly, it will be appreciated by one skilled in the art that the examples of the present disclosure may be practiced without such specific components.
Additionally, terms such as “coupled” and “connected,” along with their derivatives, may be used in the following description, claims, or both. It should be understood that these terms are not necessarily intended as synonyms for each other. “Coupled” may be used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other. “Connected” may be used to indicate the establishment of communication, i.e., a communicative relationship, between two or more elements that are coupled with each other. “Directly connected” may be used to convey that two or more physical features touch, or share an interface between each other.
Various examples are directed to integration of a reference resistor and a thermistor over a same semiconductor substrate, or die. Such integration has been elusive until now, due at least to the disparate materials needed for the resistor and thermistor, and their different processing requirements, e.g. conflicting thermal budget limits. While such examples provide materials and processes that advantageously allow such integration, no particular result is a requirement unless explicitly recited in a particular claim.
In one arrangement, the thermistor 102 may comprise a high TCR component having a positive coefficient of resistance around 6000 ppm/° C. with a 0.2% tolerance across a suitable temperature range, −40° C. to +150° C., for example, where a nominal resistance of around 10 kΩ at room temperature (˜25° C.) may be provided via trimming, if necessary, during fabrication as will be set forth below. In one arrangement, the bias resistor 104 may comprise a TFR component with low TCR, sometimes referred to herein as a TFR bias resistor, which may have a coefficient of resistance within a range of ±100 ppm/° C. In some example arrangements, the TFR bias resistor 104 may have a same resistance as the nominal resistance of the thermistor 102, e.g., 10 kΩ at room temperature. In an example implementation where the thermistor 102 and bias resistor 104 may each comprise a resistive component having a target resistance of 10 kΩ at room temperature, the resistive components may be fabricated as rectangular structures having a width of about 20-25 μm and a length of about 65-75 μm, although other dimensions, sizes, shapes or form factors may be used in additional and/or alternative arrangements without limitation. Further, the thermistor 102 and bias resistor 104 may be oriented relative to each other and/or to an orientation of the electronic device 100 in a variety of configurations.
In an example implementation, the tunable thermistor 102 may be provided with a first terminal region 103A having a first plurality of contact lines 105A, each having a respective one of the fuse links 107A, e.g., disposed in a fuse bank, for facilitating selective coupling with a pad, e.g., pad 106-2. Likewise, a second terminal region 103B of the tunable thermistor 102 may also be provided with a second plurality of contact lines 105B that each have a respective one of the fuse links 107B, e.g., disposed in a fuse bank, for facilitating selective coupling with another pad, e.g., pad 106-3. In some arrangements, the first plurality of contact lines 105A and second plurality of contact lines 105B may comprise a same number of lines although it is not a requirement. Further, in some arrangements, either the first terminal region 103A or second terminal region 103B may comprise only a single contact line operable to be connected to a respective pad, e.g., without a fuse link disposed therebetween. As will be seen further below, the individual contact lines of respective pluralities of contact lines 105A and/or 105B may be positioned apart from each other with predetermined spacings disposed therebetween during fabrication in order to facilitate a potentiometer-like resistance ladder sequence between the terminal regions 103A/103B of the thermistor 102. In some arrangements, the resistance ladder sequence associated with the thermistor 102 may be trimmed at either terminal region 103A/103B for effectuating fine- and/or coarse-tuning operations with respect to setting and/or achieving a target resistance value of the thermistor 102 by selectively enabling and disabling appropriate fuse links relative to respective terminal regions 103A/103B.
In the illustrated example of
In the example integrated thermistor-resistor configuration shown in
In an example implementation, thermistor 102/202 may be formed as a well resistor in an n-well region of a suitable semiconductor substrate and bias resistor 104/204 may be formed as a TFR component disposed in a region of the substrate electrically isolated from the n-well region.
In
It will be appreciated, however, that an SPWELL-based isolation may be optionally provided even in a single-segment thermistor application in some process flows although that may involve an additional masking step, thereby potentially increasing the production cost. Regardless of whether multi-segment or single-segment thermistor application is implemented, if an SPWELL isolation is provided, the DNWELL anneal process is implemented before the SPWELL formation, wherein the anneal process may be performed at around 1150° C. for about 4 to 5 hours or so. Skilled artisans will recognize upon reference hereto that a DNWELL region, e.g., DNWELL region 309 having appropriate dopants, may be suitably annealed in order to provide appropriate junction profile(s) for supporting a resistor body operative as a thermistor with a target resistance, which may be tuned according to the examples herein.
In
A field dielectric layer 312 (e.g., STI layer) may be formed over the single-crystal layer 304 of the substrate 306 as set forth in
In some arrangements, the contact posts 311-1 to 311-3 and 319-1 to 319-3 formed in the head regions 317A and 317B, respectively, may be implanted by an additional n-type dopant. For example, an implant process 324 illustrated in
After implanting the contact posts of the respective head regions 317A/317B, a dopant activation anneal process may be effectuated as set forth at block 510 (not specifically shown in the cross-sectional views of fabrication stages). In an example arrangement, the dopant activation anneal process may comprise a rapid thermal anneal (RTA) process at around 1000° C. for about 10 to 15 seconds, which allows the dopants in the thermistor contact posts 311-1 to 311-3 and 319-1 to 319-3 to be activated with minimal risk of significantly altering the diffusion profiles in the DNWELL region.
Subsequently, a silicidation loop may be performed, thereby forming metal-silicide regions in exposed regions of the contact posts of the thermistor body comprising DNWELL 309, as set forth in
After silicidation of the contact posts, a TFR layer 314 may be formed, e.g., using silicon chromium (SiCr), nickel-chromium alloy of silicon (SiNiCr), or some other suitable metal alloy of silicon or metal silicide, over the field dielectric layer 312, as set forth at block 514 and in
As will be set forth further below, in additional and/or alternative arrangements, the TFR bias resistor body 316 may be patterned such that it may form an overlying structure disposed over the STI portion that electrically isolates the underlying DNWELL 309 region, e.g., where the TFR bias resistor body 316 has a shape and/or area that does not block the thermistor head regions 317A and 317B and complies with applicable minimum geometry design rules associated therewith.
Because the contact post silicidation process (e.g., involving a first type of metal silicide) may precede the formation of a TFR layer (e.g., involving a metal-silicon alloy, which may be considered a second type of metal silicide) in some implementations, the TFR deposition process may be manipulated appropriately so as to not disturb the conductivity characteristics of the thermistor contact posts achieved during the silicidation. Further, some additional and/or alternative arrangements may involve a combined process wherein the contact post silicidation and TFR layer formation using suitable metal-silicon alloy material may be performed in a single stage. By way of example, as set forth in
After patterning the TFR bias resistor 316, a pre-metal dielectric (PMD) stack 332 may be formed over the semiconductor device 301, which may comprise one or more layers and/or liners, e.g., using known or heretofore unknown processes, materials and compositions, as set forth at block 518 and shown in the fabrication stage of
As illustrated in
After the formation of contact holes, the semiconductor device 301 may undergo a contact liner and plug process to fill the contact vias with suitable metal compositions, liners or posts, which may be connected to a patterned metal layer formed over the PMD stack 332 in a metallization process following the opening of pads and metal-based fuse links (not specifically shown in
A contact via metallization stage set forth in
A first metallization stage of the backend of line (BEOL) flow may involve depositing, patterning and etching a metallic material (e.g., aluminum, copper, etc.) for forming a metal interconnect layer that interconnects the bias resistor 316, the thermistor body 309 as well the die pads (and any optional ESD protection devices where provided), via respective metal fuse links, which may be configured for trimming as previously set forth (block 524). Further, respective fuse code settings for achieving appropriate resistances with respect to the bias resistor and/or thermistor may be obtained as will be set forth below. As illustrated in
Continuing to refer to
In an example implementation of the binary ladder potentiometer architecture set forth above, the unit resistors may be provided as identical structures disposed at the respective head regions in order to ensure good matching and predictability of the properties. By using fuses to determine which legs are opened and which legs remain shorted, the resistance can be adjusted between the two end cases as set forth above. In some examples, a plurality of metal laser fuse links may be laid out in the metal layer and a post-metallization process may be implemented to program a specific fuse pattern (e.g., a fuse code) for achieving a target resistance based on appropriate trimming. For example, after a protective overcoat (PO) deposition, a pattern may be etched to open the probe pads and to uncover the fuses. The resistance may be measured using a prober that may be configured to allow for temperature correction, e.g., with respect to a thermistor tuning. Using the measured resistance, a trim algorithm may be implemented to determine which fuses to open (e.g., according to the fuse code) to attain the desired resistance target. After the resistance measurement, an oxide film may be deposited to cover the pads and unselected fuses and a laser trim tool may be used to expose the selected fuses, which damages the oxide layer and locally melts the exposed metal. A wet “slag” etch may then be performed to chemically remove metal that may remain where the fuses are intended to be open. A final PO SiON layer may be deposited and etched to open the pads while leaving the fuses covered.
Based on the foregoing, it should be appreciated that examples of the present disclosure provide an integrated thermistor and a bias reference resistor on a single die, thereby obviating the need to procure two discrete components, potentially from separate manufacturers, for a product application. Because the voltage divider circuit according to the examples herein is formed as an integrated component rather than two separate devices, circuit board space—and cost—may be minimized, which may allow product miniaturization in an application, e.g., in a sensor application. Die size savings may be particularly significant especially in a vertically oriented thermistor-bias resistor configuration. Further, whereas conventional bias reference resistors are fabricated in process flows requiring tighter process controls in order to achieve required precision, which thwarts integration of the device in an IC having other components that are typically manufactured in less stringent flows (and relatively simpler flows having only a small number of mask layers) such as, e.g., thermistor flows, examples herein provide an integrated process flow that can advantageously accommodate the fabrication of a low/zero TCR component, e.g., a bias resistor, in a flow including the thermistor flow wherein the bias resistor can be fine-tuned to meet the specifications of a particular application. Whereas example arrangements set forth herein may therefore be expected to provide a combination of various tangible improvements, no particular result is a requirement unless explicitly recited in a particular claim.
While various examples of the present disclosure have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed examples can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described examples. Rather, the scope of the disclosure should be defined in accordance with the claims appended hereto and their equivalents.
For example, in this disclosure and the claims that follow, unless stated otherwise and/or specified to the contrary, any one or more of the layers set forth herein can be formed in any number of suitable ways, such as with spin-on techniques, sputtering techniques (e.g., Magnetron and/or ion beam sputtering), (thermal) growth techniques or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD), etc. As another example, silicon nitride may be a silicon-rich silicon nitride or an oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the materials dielectric constant is substantially different from that of high purity silicon nitride.
Further, in at least some additional or alternative implementations, the functions/acts described in the blocks may occur out of the order shown in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Also, some blocks in the flowcharts may be optionally omitted. Furthermore, although some of the diagrams include arrows on communication paths to show a primary direction of communication, it is to be understood that communication may occur in the opposite direction relative to the depicted arrows. Finally, other blocks may be added/inserted between the blocks that are illustrated.
It should therefore be clearly understood that the order or sequence of the acts, steps, functions, components or blocks illustrated in any of the flowcharts and/or block diagrams depicted in the drawing Figures of the present disclosure may be modified, altered, replaced, customized or otherwise rearranged within a particular flowchart or block diagram, including deletion or omission of a particular act, step, function, component or block. Moreover, the acts, steps, functions, components or blocks illustrated in a particular flowchart may be inter-mixed or otherwise inter-arranged or rearranged with the acts, steps, functions, components or blocks illustrated in another flowchart in order to effectuate additional variations, modifications and configurations with respect to one or more processes for purposes of practicing the teachings of the present disclosure.
At least some portions of the foregoing description may include certain directional terminology, such as, e.g., “upper”, “lower”, “top”, “bottom”, “left-hand”, “right-hand”, “front side”, “backside”, “vertical”, “horizontal”, etc., which may be used with reference to the orientation of some of the Figures or illustrative elements thereof being described. Because components of some examples can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Likewise, references to features referred to as “first”, “second”, etc., are not indicative of any specific order, importance, and the like, and such references may be interchanged mutatis mutandis, depending on the context, implementation, etc. Further, the features of examples described herein may be combined with each other unless specifically noted otherwise.
Although various implementations have been shown and described in detail, the claims are not limited to any particular implementation or example. None of the above Detailed Description should be read as implying that any particular component, element, step, act, or function is essential such that it must be included in the scope of the claims. Where the phrases such as “at least one of A and B” or phrases of similar import are recited or described, such a phrase should be understood to mean “only A, only B, or both A and B.” Reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described implementations that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims appended below.
