Claims
- 1. A method of forming wafers, comprising:
providing slabs of P-type material and slabs of N-type material; alternately stacking the slabs of P-type material and slabs of N-type material; forming a P/N-type ingot from the slabs of P-type and N-type material; and slicing the P/N-type ingot into P/N-type wafers.
- 2. The method of claim 1, wherein each P/N-type wafer is large enough to support multiple thermoelectric circuits.
- 3. The method of claim 1, wherein the slabs of P-type material and the slabs of N-type material are sliced from blocks of P-type material and blocks of N-type material; respectively.
- 4. The method of claim 1, wherein the slabs of P-type material and slabs of N-type material are formed to respective thicknesses to support stacking.
- 5. The method of claim 1, further comprising applying a passivating agent between a plurality of the slabs of P-type material and a plurality of the slabs of N-type material.
- 6. The method of claim 1, further comprising applying a separating material between a plurality of the slabs of P-type material and a plurality of the slabs of N-type material.
- 7. The method of claim 6, further comprising removing the separating material such that spaces are formed between P-type material and N-type material of at least one of the P/N-type wafers.
- 8. The method of claim 6, wherein the separating material comprises an electrically insulating material.
- 9. The method of claim 1, wherein the P/N-type ingot is formed by a hot pressing process.
- 10. The method of claim 1, wherein the P/N-type ingot is formed by a hot forging process.
- 11. The method of claim 1, wherein the P/N-type ingot is formed by a hot extrusion process.
- 12. The method of claim 11, wherein the hot extrusion process comprises an area reduction extrusion process.
- 13. The method of claim 11, wherein the hot extrusion process comprises an angular extrusion process.
- 14. The method of claim 1, wherein the P/N-type ingot is formed by a hot-rolling process.
- 15. A method of forming wafers, comprising:
loading P-type material powder and N-type material powder into a tool, alternatingly; consolidating the P-type material powder and the N-type material powder using pressure and high temperature, to form a P/N-type ingot; and slicing the P/N-type ingot into P/N-type wafers.
- 16. The method of claim 15, further comprising separating the P-type material from the N-type material using a separating layer.
- 17. The method of claim 15, further comprising hot forging the P/N-type ingot to decrease a thickness of the P/N-type ingot.
- 18. The method of claim 15, further comprising hot rolling the P-type material powder and the N-type material powder.
- 19. The method of claim 15, further comprising hot extruding the P/N-type ingot to decrease a thickness of the P/N-type ingot.
- 20. The method of claim 15, wherein each of the P/N-type wafers is large enough in cross section to support multiple thermoelectric circuits.
- 21. A method of forming a thermoelectric device, comprising:
extruding a P/N-type billet to form a P/N-type extrusion; slicing the P/N-type extrusion into a plurality of P/N-type wafers, each having a first plurality of P-type regions and a first plurality of N-type regions; applying diffusion barrier metallization to at least a subset of the P-type regions and N-type regions; attaching one side of at least one P/N-type wafer to a temporary substrate, using a bonding media; coupling the at least one P/N-type wafer to a first plate having a first patterned metallization to form a thermoelectric circuit, wherein the subset of P-type regions and N-type regions are arranged electrically in series and thermally in parallel; detaching the temporary substrate and bonding media from the at least one P/N-type wafer; and coupling the at least one P/N-type wafer to a second plate having a second patterned metallization.
- 22. The method of claim 21, wherein the P/N-type billet includes P-type regions and N-type regions, and separating layers disposed between the P-type regions and adjacent N-type regions.
- 23. The method of claim 21, further comprising separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type and N-type elements while the wafer is attached to the temporary substrate.
- 24. The method of claim 23, wherein separating the P/N-type regions of the wafer into an array of isolated P-type and N-type elements comprises dicing the P/N-type regions of the P/N-type wafer.
- 25. The method of claim 23, wherein separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type and N-type elements comprises abrading the P/N-type regions of the P/N-type wafer.
- 26. The method of claim 23, wherein separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type and N-type elements comprises wet etching the P/N-type regions of the P/N-type wafer.
- 27. The method of claim 23, wherein separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type and N-type elements comprises dry etching the P/N-type regions of the P/N-type wafer.
- 28. The method of claim 23, wherein separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type elements and N-type elements comprises electrostatic discharge machining.
- 29. The method of claim 23, wherein separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type elements and N-type elements comprises laser cutting.
- 30. A method of forming a thermoelectric device, comprising:
providing a P/N-type ingot having a first plurality of P-type regions and a first plurality of N-type regions; slicing the P/N-type ingot into a plurality of P/N-type wafers; applying a diffusion barrier metallization to at least a first subset of the P-type regions and N-type regions; applying a first patterned current-carrying metallization to a first side of the P/N-type wafer to form a thermoelectric circuit; coupling the first side of at least one of the P/N-type wafers to a temporary substrate using a bonding media; thinning the P/N-type wafer to a desired height while the wafer is mounted on the temporary substrate; applying a second diffusion barrier metallization to at least a second subset of the P-type regions and N-type regions on a second side of the P/N-type wafer, while the wafer is mounted to the temporary substrate; applying a second patterned current-carrying metallization to the second side of the P/N-type wafer to form a thermoelectric circuit; separating at least a portion of the P/N-type regions of the wafer while the wafer is attached to the temporary substrate; and decoupling the thermoelectric device from the temporary substrate and the bonding media.
- 31. The method of claim 30, further comprising thermally coupling the thermoelectric device to one or more permanent substrates to provide electrical isolation.
- 32. The method of claim 30, further comprising extruding a P/N-type billet to form the P/N-type ingot.
- 33. The method of claim 30, further comprising hot rolling a P/N-type billet to form the P/N-type ingot.
- 34. The method of claim 30, further comprising hot forging a P/N-type billet to form the P/N-type ingot
- 35. The method of claim 30, wherein separating the P/N-type regions of the wafer into an array of isolated P-type and N-type elements comprises dicing the P/N-type regions of the P/N-type wafer.
- 36. The method of claim 30, wherein separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type and N-type elements comprises electrostatic discharge machining.
- 37. The method of claim 30, wherein separating the P/N-type regions of the wafer into an array of isolated P-type and N-type elements comprises laser cutting.
- 38. The method of claim 30, wherein separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type and N-type elements comprises abrading the P/N-type regions of the P/N-type wafer.
- 39. The method of claim 30, wherein separating the P/N-type regions of the P/N-type wafer into an array of isolated P-type and N-type elements comprises wet etching the P/N-type regions of the P/N-type wafer.
- 40. The method of claim 30, wherein separating the P/N-type regions of the P/N-type wafer in to an array of isolated P-type and N-type elements comprises dry etching the P/N-type regions of the P/N-type wafer.
- 41. The method of claim 30, further comprising applying a thermally and electrically insulating material between the separated P/N-type regions of the thermoelectric device.
- 42. The method of claim 30, further comprising applying an electrically insulative, thermally conductive layer over the second side of the P/N-type wafer.
- 43. The method of claim 42, further comprising applying a metallization layer over the electrically insulative, thermally-conductive layer.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part of U.S. application Ser. No. 10/729,610 filed Dec. 5, 2003 and entitled “THERMOELECTRIC DEVICE HAVING CO-EXTRUDED P-TYPE AND N-TYPE MATERIALS,” which is a divisional of U.S. patent application Ser. No. 09/872,394 filed Jun. 1, 2001 and entitled “THERMOELECTRIC DEVICE HAVING CO-EXTRUDED P-TYPE AND N-TYPE MATERIALS,” now U.S. Pat. No. 6,660,925, issued Dec. 9, 2003.
Divisions (1)
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Number |
Date |
Country |
Parent |
09872394 |
Jun 2001 |
US |
Child |
10729610 |
Dec 2003 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
10729610 |
Dec 2003 |
US |
Child |
10897871 |
Jul 2004 |
US |