Embodiments of the present disclosure relate to power management solutions, and in particular to methods and apparatuses that include embedded magnetic sheaths for use in co-axial inductors.
Efficient power management is crucial for many integrated circuit (IC) technologies, especially for high end server devices. Currently, voltage regulation in some ICs may be implemented with imbedded voltage regulators. Such embedded voltage regulators often use air coil inductors (ACIs) formed by plating through hole walls with copper. However, ACIs may not provide the desired inductance. In order to increase the inductance, more ACIs may be formed in series. This increases the overall footprint of the voltage regulators. Additional solutions for increasing the inductances of ACIs have been proposed. For example, a magnetic sheath material may be positioned inside and around the coil.
However, the introduction of magnetic materials results in disruptions to currently used manufacturing processes. The magnetic materials leach and negatively affect chemistries used in the processing of IC substrates. For example, exposed magnetic materials may result in bath contamination during desmear, electroless copper plating, and subtractive etching processes.
Described herein are systems with fully embedded magnetic materials on IC substrates and methods of forming such systems. More particularly, embodiments include co-axial inductors with fully embedded magnetic sheath and methods of forming such devices. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
As noted above, the inclusion of magnetic materials in the manufacture of IC devices is currently problematic due to the leaching of magnetic materials (e.g., iron, alloys containing iron, and other ferromagnetic particles or elements) into processing baths. Accordingly, it is presently not feasible to integrate components, such as inductors, that include magnetic materials into IC substrates. However, embodiments described herein provide processing methods that allow for the integration of magnetic materials with currently available processing techniques. Particularly, embodiments include fully embedding magnetic materials so that the magnetic materials are not exposed to processing environments where the leaching of magnetic materials is detrimental. For example, embodiments include embedding the magnetic materials so that the magnetic materials are not exposed to processing environments that have chemistries that may be negatively altered by leached magnetic materials, such as one or more of desmear baths, electroless baths, and subtractive etching baths. Since the magnetic material is isolated from such environments, there is no need to redesign the chemistries of processing baths or provide dedicated processing baths to handle the magnetic materials. Furthermore, isolating the magnetic material allows for subsequent changes to the magnetic material to be made without needing to adjust the chemistries of processing environments. This allows for quicker design times and reduces the cost of development. In embodiments, the magnetic material interfaces with the substrate core and a barrier layer. This provides better reliability in terms of interface delamination and blistering. Additionally, the barrier layer may function as an electromigration barrier between through-holes. This is particularly beneficial since the magnetic fillers (e.g., conductive ferrites) of the magnetic material may pose a higher risk for through-hole to through-hole leakage.
In accordance with an embodiment, the fully embedded magnetic material may be used to form a co-axial inductor. In the co-axial inductors described herein, the magnetic material may be a sheath that surrounds a plated through-hole. The magnetic sheath may be separated from the plated through-hole by a barrier layer. Additionally, a top surface and a bottom surface of the magnetic sheath may be covered by the barrier layer and an outer sidewall surface of the magnetic sheath may be covered by the substrate core. Fully embedding the magnetic sheath simplifies the processing as described above.
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In order to increase the inductance of the inductor 100, a magnetic sheath 115 is formed around the plated through-holes 112. In an embodiment, the magnetic sheath 115 is fully embedded. In an embodiment, a first surface 117A of the magnetic sheath 115 is in direct contact with a barrier layer 180, a second surface 117E of the magnetic sheath 115 is in direct contact with the barrier layer 180, a third (outer) surface 117c is in direct contact with the substrate core 105, and a fourth (inner) surface 117D is in direct contact with the barrier layer 180. In an embodiment, the barrier layer 180 may be any suitably material that may be deposited with a dry deposition process, such as sputtering, plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). Embodiments may include a barrier layer 180 that includes one or more of Ti, TiN, Ta, TaN, SiN, Ru and Cu. In some embodiments, the barrier layer 180 may also function as a seed layer for subsequently deposited conductive layers, such as the conductive layer used for the plated through-holes 112. In an embodiment, the barrier layer 180 may have a thickness T that is less than 1 μm thick. It is to be appreciated that the thickness T does not need to be uniform. Deposition processes may provide a barrier layer 180 with a thickness T that is greater over the surfaces 117A and 117E than the thickness T along surface 117. Furthermore, the thickness T may not be uniform along surface 117. The differences in the thickness T may be attributed to the aspect ratio of the through-hole via, the shape (e.g., tapered surface) of the through-hole via, or the like.
As shown, the magnetic sheath 115 is not in contact with any conducting surface, including the lid 119 and the plated through-hole 112. As such, the magnetic sheath 115 is not exposed to processing environments that are used to form the plated through-hole 112 or lid 119, such as electroless plating environments. Accordingly, currently used processing chemistries may be used without magnetic materials leaching into processing baths.
In an embodiment, the magnetic sheath 115 may pass entirely through the substrate core 105. Surfaces 117A and 117E of the magnetic sheath 115 may be substantially coplanar with surfaces 106 and 107 of the substrate core 105. As used herein, “substantially coplanar” may refer to surfaces that are within +/−2 μm of being coplanar with each other. In an embodiment, the outer surface 117c and inner surface 117D of the magnetic sheath 115 may be substantially vertical. As used herein, “substantially vertical” may refer to surfaces that are within +/−5° from 90°. Additional embodiments may include an outer surface 117c and an inner surface 117D that are tapered surfaces.
The magnetic sheath 115 may be any suitable magnetic material. In an embodiment, the magnetic sheath 115 may be a dielectric material that includes magnetic particles. In one embodiment, the magnetic particles may include iron, alloys including iron, or any other elements or alloys that have magnetic properties. In an embodiment, the magnetic sheath 115 may have a relative permeability greater than 10. In an embodiment, the magnetic sheath 115 may have a relative permeability greater than 20.
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In an embodiment, the magnetic material 215 may have a first surface 217A that is substantially coplanar with a first surface 206 of the substrate core 205, and the magnetic material 215 may have a second surface 217E that is substantially coplanar with a second surface 207 of the substrate core 205. Embodiments may also include an outer sidewall surface 217c that is in direct contact with the substrate core 205. The outer surface 217c may conform to the surfaces of the opening 250. As such, the profile of the outer surface 217c may match the profile of the opening 250 (e.g., vertical sidewalls, tapered sidewalls, etc.).
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Embodiments may include disposing the barrier layer 280 over the surfaces with a dry deposition processes, such as sputtering, PECVD, or ALD. Embodiments may include a barrier layer 280 that includes one or more of Ti, TiN, Ta, TaN, SiN, Ru and Cu. In some embodiments, the barrier layer 280 may also function as a seed layer for subsequently deposited conductive layers. In an embodiment, the barrier layer 280 may have a thickness that is less than 1 μm thick. It is to be appreciated that the thickness of the barrier layer 280 may not be uniform. Deposition processes may provide a barrier layer 280 with a thickness T3 over the surfaces 217A and 217E that is greater than the thicknesses T1 and T2 along surface 217. Furthermore, the thicknesses T1 may not be the same as thickness T2. The differences in the thicknesses T1 and T2 may be attributed to the aspect ratio of the through-hole via, the shape (e.g., tapered surface) of the through-hole via, or the like. For example, the thickness T1 may be greater than the thickness T2. As illustrated, the magnetic sheath 215 is now fully embedded by the substrate core 205 and the barrier layer 280, (i.e., the outer surface 217c by the substrate core 205, and the inner surface 217, the first surface 217A, and the second surface 217E by the barrier layer 280).
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Accordingly, the first surface 317A and the second surface 317E of the magnetic material 315 may be substantially coplanar with surfaces of the film layers 341. In such embodiments, a portion of the magnetic material 315 may contact the film layers 341, which may be conductive materials, such as copper. However, it is to be appreciated that the film layers 341 are disposed over the substrate core 305 prior to the magnetic material 315 being plugged into the opening through the substrate core 305. As such, the magnetic material 315 is not exposed to the processing environments used to form the film layers 341. Embodiments may also include an outer sidewall surface 317c that is in direct contact with the substrate core 305. The outer surface 317c may conform to the surfaces of the opening 350. As such, the profile of the outer surface 317c may match the profile of the opening 350 (e.g., vertical sidewalls, tapered sidewalls, etc.). In an embodiment, the magnetic material used to form the magnetic material 315 may be cured after it is planarized.
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Embodiments may include disposing the barrier layer 380 over the surfaces with a dry deposition processes, such as sputtering, PECVD, or ALD. Embodiments may include a barrier layer 380 that includes one or more of Ti, TiN, Ta, TaN, SiN, Ru and Cu. In some embodiments, the barrier layer 380 may also function as a seed layer for subsequently deposited conductive layers. In an embodiment, the barrier layer 380 may have a thickness that is less than 1 μm thick. It is to be appreciated that the thickness of the barrier layer 380 may not be uniform. Deposition processes may provide a barrier layer 380 with a thickness T3 over the surfaces 317A and 317E that is greater than the thicknesses T1 and T2 along surface 317. Furthermore, the thicknesses T1 may not be the same as thickness T2. The differences in the thicknesses T1 and T2 may be attributed to the aspect ratio of the through-hole via, the shape (e.g., tapered surface) of the through-hole via, or the like. For example, the thickness T1 may be greater than the thickness T2. As illustrated, the magnetic sheath 315 is now fully embedded by the substrate core 305 and the barrier layer 380, (i.e., the outer surface 317c by the substrate core 305, and the inner surface 317, the first surface 317A, and the second surface 317E by the barrier layer 380).
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Subsequently, the barrier layer 380 may be removed with a second subtractive etching process. In an embodiment, the etching chemistry may selectively etch the barrier layer 380 in order to expose portions of the surfaces of the film layer 341. A third etching process may then be implemented to remove exposed portions of the film layer 341.
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In an embodiment, an inductor 410 similar to embodiments described above may be integrated into the package substrate 470 or the board 480, or the package substrate 470 and the board 480. Embodiments include any number of inductors 410 formed into the package substrate 470 and the board 480. For example, a plurality of inductors 410 may be integrated into the circuitry of the package substrate 470 or the board 480, or the package substrate 470 and the board 480 for power management, filtering, or any other desired use.
These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 506 enables wireless communications for the transfer of data to and from the computing device 500. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 504 of the computing device 500 includes an integrated circuit die packaged within the processor 504. In some implementations of the invention, the integrated circuit die of the processor may include an inductor with a fully embedded magnetic sheath, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 506 also includes an integrated circuit die packaged within the communication chip 506. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices that include an inductor with a fully embedded magnetic sheath, in accordance with embodiments described herein.
The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Example 1 may include an inductor, comprising; a substrate core; a conductive through-hole through the substrate core; and a magnetic sheath around the conductive through hole, wherein the magnetic sheath is separated from the plated through hole by a barrier layer that is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.
Example 2 may include the inductor of Example 1, wherein the first surface of the magnetic sheath is substantially coplanar with a first surface of the substrate core and wherein the second surface of the magnetic sheath is substantially coplanar with a second surface of the substrate core.
Example 3 may include the inductor of Example 1 or Example 2, wherein the barrier layer is in contact with and over the first surface of the substrate core and the second surface of the substrate core.
Example 4 may include the inductor of Examples 1-3, wherein the magnetic sheath is fully embedded, wherein an outer surface of the magnetic sheath is in direct contact with the substrate core.
Example 5 may include the inductor of Examples 1-4, wherein a thickness of the barrier layer is 1 μm or less.
Example 6 may include the inductor of Examples 1-5, wherein a thickness of the magnetic sheath is 50 μm or greater.
Example 7 may include the inductor of Examples 1-6, wherein the first surface of the magnetic sheath is not substantially coplanar with a first surface of the substrate core and wherein the second surface of the magnetic sheath is not substantially coplanar with a second surface of the substrate core.
Example 8 may include the inductor of Examples 1-7, wherein a first film layer is formed over the first surface and a second film layer is formed over the second surface of the substrate core, and wherein the first and second conductive layers are in direct contact with the magnetic sheath.
Example 9 may include the inductor of Examples 1-8, wherein the first surface of the magnetic sheath is substantially coplanar with a top surface of the first film layer, and wherein a second surface of the magnetic sheath is substantially coplanar with a surface of the second film layer.
Example 10 may include the inductor of Examples 1-9, wherein a permeability of the magnetic sheath is greater than 10.
Example 11 may include the inductor of Examples 1-10, further comprising a plugging layer filling the conductive through-hole, wherein the plugging layer comprises a dielectric material.
Example 12 may include a method of forming an inductor, comprising: forming a first opening through a substrate core; filling the first opening with a magnetic material; forming a second opening through the magnetic material to define a magnetic sheath, wherein the magnetic sheath comprises a first surface, a second surface, an outer surface, and an inner surface, and wherein the outer surface is in direct contact with the substrate core; disposing a barrier layer over the inner surface of the magnetic sheath, the first surface of the magnetic sheath, and the second surface of the magnetic sheath; and disposing conductive layers over the barrier layer to form a conductive through-hole via.
Example 13 may include the method of Example 12, wherein the first surface of the magnetic sheath is substantially coplanar with a first surface of the substrate core, and wherein the second surface of the magnetic sheath is substantially coplanar with a second surface of the substrate core.
Example 14 may include the method of Example 12 or Example 13, wherein the magnetic sheath is fully embedded by the substrate core and the barrier layer.
Example 15 may include the method of Examples 12-14, wherein one or both of the first opening and the second opening are formed with a mechanical drilling process.
Example 16 may include the method of Examples 12-15, wherein one or both of the first opening and the second opening, and the third opening are formed with a laser drilling process.
Example 17 may include the method of Examples 12-16, wherein the first surface of the magnetic sheath is not substantially coplanar with a first surface of the substrate core, and wherein the second surface of the magnetic sheath is not substantially coplanar with a second surface of the substrate core.
Example 18 may include the method of Examples 12-17, wherein a first foil is disposed over the first surface of the substrate core and a second foil is formed over the second surface of the substrate core, and wherein a surface of the first foil is substantially coplanar with the first surface of the magnetic sheath, and a surface of the second foil is substantially coplanar with the second surface of the magnetic sheath.
Example 19 may include the method of Examples 12-18, further comprising: disposing a plugging layer comprising a dielectric material into the second opening to fill the conductive through hole, wherein the barrier layer is disposed with a dry deposition process.
Example 20 may include the method of Examples 12-19, wherein the dry deposition process is sputtering, plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).
Example 21 may include the method of Examples 12-20, wherein the barrier layer comprises on or more of Ti, TiN, Ta, TaN, SiN, Ru, and Cu, and wherein the barrier layer has a thickness less than 1 μm.
Example 22 may include an integrated circuit package comprising: an integrated circuit die; and a multi-phase voltage regulator electrically coupled to the integrated circuit die, wherein the multi-phase voltage regulator comprises: a substrate core; and a plurality of inductors, wherein the inductors comprise: a conductive through-hole through the substrate core; and a magnetic sheath around the conductive through hole; and a barrier layer, wherein the magnetic sheath is separated from the plated through hole by the barrier layer, wherein the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.
Example 24 may include the integrated circuit package of Example 23, wherein the magnetic sheath is fully embedded by the substrate core and the barrier layer.
Example 25 may include the integrated circuit package of Example 23 or Example 24, wherein the barrier layer is less than 1 μm and wherein the barrier layer comprises one or more of Ti, TiN, Ta, TaN, SiN, Ru, and Cu.