Patent Application
20200044621
Aspects of the present disclosure relate to thin film devices, and more particularly, to structures and manufacturing methods for thin film devices on high resistivity silicon substrate.
In some examples, a layer transfer process is used to transfer a top active device portion of a silicon-on-insulator (SOI) wafer to a handle wafer. In this process, the top portion of the SOI wafer is bonded to the handle wafer. The same process may be used for building a thin film device, such as a thin film surface acoustic wave (SAW), on a high-resistivity substrate. For example, a thin film piezoelectric wafer may be bonded with a high-resistivity silicon handle wafer. However, if two bonded wafers have different thermal expansion coefficients, fracture may happen when the bonded wafer pair is annealed or processed at higher temperatures. Accordingly, it would be beneficial to have structures and methods for thin film devices on a high resistivity substrate that can better tolerate thermal cycles during manufacturing.
The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key nor critical elements of all implementations nor delineate the scope of any or all implementations. The sole purpose of the summary is to present concepts relate to one or more implementations in a simplified form as a prelude to a more detailed description that is presented later.
In one aspect, a thin film surface acoustic wave (SAW) die comprises a high-resistivity substrate, a bonding layer on the high-resistivity substrate, and a thin film piezoelectric island on the bonding layer, wherein an edge of the thin film piezoelectric island is offset from an edge of the bonding layer.
In another aspect, an apparatus comprises a high-resistivity substrate, a bonding layer on the high resistive substrate, and a plurality of thin film piezoelectric islands on the bonding layer.
In another aspect, a method comprises providing a piezoelectric wafer having a front surface and a back surface; forming an exfoliation layer in the piezoelectric wafer from the front surface; forming a plurality of trenches on the piezoelectric wafer from the front surface to form a plurality of piezoelectric islands; bonding the piezoelectric wafer from the front surface to a high-resistivity wafer though a bonding layer; and removing a portion of the piezoelectric wafer between the back surface and the exfoliation layer.
To accomplish the foregoing and related ends, one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the described implementations are intended to include all such aspects and their equivalents.
The detailed description set forth below, in connection with the appended drawings, is intended as a description of various aspects and is not intended to represent the only aspects in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing an understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
A surface acoustic wave (SAW) is an acoustic wave traveling along the surface of a material exhibiting elasticity, with an amplitude that typically decays exponentially with depth into the substrate. SAW devices are used as filters, oscillators, transformers and sensors. SAW filters are now used in mobile telephones. They provide significant advantages in performance, cost, and size over other filter technologies such as quartz crystals (based on bulk waves), LC filters, and waveguide filters.
The function of a SAW device is based on the transduction of acoustic waves. There are two dimensional waves confined to the surface of the solid material, down to a depth of approximately two wavelengths. The transduction from electric energy to mechanical energy (in the form of SAWs) is often accomplished by the use of piezoelectric materials. The piezoelectric layer is usually thin and need to be placed on top of a carrier, such as a high-resistivity silicon handle wafer. However, if the thin piezoelectric layer and the carrier have different thermal expansion coefficients, the thin piezoelectric layer may be fractured during the thermal cycles, such as during an annealing process. Accordingly, it would be beneficial to have structures and methods for thin film devices on a high-resistivity substrate that can better tolerate thermal cycles during manufacturing.
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The plurality of trenches 106 in the piezoelectric wafer 102 serves as stress relief during subsequent thermal cycles. In the subsequent thermal cycles, such as high temperature processes or anneal processes, the effect of the thermal coefficient mismatch between the high-resistivity substrate 110 and the piezoelectric wafer 102 is localized, limited to each individual piezoelectric island 112, thus minimizing the damaging effect aggregation across the whole wafer.
In
The thermal dielectric material 114 provides support and protection to the plurality of piezoelectric islands in addition to providing a thermal buffer between two piezoelectric islands, resulting in better reliability and higher yield.
At 704, an exfoliation layer (e.g., the exfoliation layer 104) is formed closed to the front surface in the piezoelectric wafer. The exfoliation layer may be formed by performing high dose ion implantation from the front surface. The depth of the exfoliation layer defines the thickness of the thin film devices in the final products.
At 706, a plurality of trenches (e.g., the plurality of trenches 106) is formed from the front surface of the piezoelectric wafer. The depth of the plurality of the trenches may be larger than the depth of the exfoliation layer. The plurality of trenches may be formed by dry etch, wet etch, laser ablation, and/or other suitable methods. A plurality of piezoelectric islands (e.g., the plurality of piezoelectric islands 112) is formed among the plurality of trenches.
The plurality of trenches serves as stress relief during subsequent thermal cycles. In the subsequent thermal cycles, such as high temperature processes or anneal processes, the effect of the thermal coefficient mismatch between the high-resistivity substrate and the piezoelectric wafer is localized, limited to individual piezoelectric islands, thus minimizing the aggregation of the damaging effect across the whole wafer.
At 708, the piezoelectric wafer is bonded to a high-resistivity substrate (e.g., the high-resistivity substrate 110) through a bonding layer (e.g., the bonding layer 108). The high-resistivity substrate may be low doped or un-doped silicon, porous silicon, glass, sapphire, etc., with resistivity greater than or equal to 3 KΩ. The high-resistivity substrate serves as a handle wafer or carrier substrate in the final product. The bonding layer may be trap-rich layer. It could be oxide film if the high-resistivity substrate is a silicon wafer. The bonding layer may be SiCN for other types of high-resistivity substrate. Certain thermal cycle, such as an anneal process, is needed to facilitate the bonding.
Optionally, before 708, a plurality of thermal dielectric materials (e.g., the plurality of thermal dielectric materials 114) may fill the plurality of trenches. The plurality of thermal dielectric materials may be selected such that the average temperature coefficient of the plurality of dielectric materials and the plurality of piezoelectric islands substantially matches or is close to the temperature coefficient of the high-resistivity substrate and/or the bonding layer. Another good material could be porous dielectric material (Low K) to allow the piezoelectric wafer to expand relatively easily during the bonding annealing.
At 710, a portion of piezoelectric wafer may be removed through exfoliation process. The piezoelectric wafer may first be ground from the back surface to expose the plurality of trenches. Then the piezoelectric wafer may go through another thermal cycle, such as anneal at 100-450° C. temperature to exfoliate along the exfoliation layer. Chemical mechanical polishing (CMP) is further applied to remove the implant damage and to thin the piezoelectric wafer to a desire thickness. As a result, a wafer-level product (e.g., as shown in
At 712, the wafer-level product is diced to obtain a plurality of dies. Each die forms an individual SAW die (e.g., the individual SAW die 400a, 400b, 500a, or 500b).
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
