Claims
- 1. A method of fabricating an integrated circuit, comprising the steps of:
forming a first interlevel dielectric over a semiconductor body; forming a layer of resistor material over said first interlevel dielectric layer, said layer of resistor material having a TCR of 0+/−10 ppm/° C.; patterning an etching said layer of resistor material to form a thin film resistor.
- 2. The method of claim 1, wherein said layer of resistor material has a thickness in the range of 20-50 Å.
- 3. The method of claim 1, wherein said layer of resistor material comprises Nix Cr1−x.
- 4. The method of claim 3, wherein x equals 40.
- 5. The method of claim 1, wherein said layer of resistor material comprises SiCr.
- 6. The method of claim 1, wherein said layer of resistor material comprises TaN.
- 7. The method of claim 1, wherein said layer of resistor material has a sheet resistance on the order of 500 Ohms/sq.
- 8. The method of claim 1, wherein said step of forming said layer of resistor material comprises depositing NiCr for a deposition time in the range of 6-14 seconds.
- 9. The method of claim 1, wherein said step of forming said layer of resistor material comprises depositing NiCr for a deposition time of 7 seconds.
- 10. The method of claim 1, wherein a thickness of said layer of resistor material is selected using a process comprising the steps of:
depositing structures of said resistor material on a test wafer at a plurality of different thicknesses in the range of 20 Å-200 Å; measuring the TCR for each of said thicknesses; determining a relationship between TCR and sheet thickness; and selecting a thickness corresponding to the TCR of 0+/−10 ppm/° C.
- 11. The method of claim 10, wherein, said resistor material comprises Ni40Cr60, and said relationship is
- 12. The method of claim 11, wherein said thickness is 50 Å.
- 13. A method of fabricating an integrated circuit, comprising the steps of:
forming a first interlevel dielectric over a semiconductor body; forming a layer of resistor material over said first interlevel dielectric layer, said layer of resistor material having a thickness in the range of 20-50 Å; patterning an etching said layer of resistor material to form a thin film resistor.
- 14. The method of claim 13, wherein said layer of resistor material has a TCR of 0+/−10 ppm/° C.
- 15. The method of claim 13, wherein said layer of resistor material comprises Nix Cr1−x.
- 16. The method of claim 13, wherein said step of forming said layer of resistor material comprises depositing NiCr for a deposition time in the range of 6-14 seconds.
- 17. The method of claim 13, wherein said step of forming said layer of resistor material comprises depositing NiCr for a deposition time of 7 seconds.
- 18. An integrated circuit, comprising:
a thin film resistor having a thickness in the range of 20-50 Å.
- 19. The integrated circuit of claim 18, wherein said thin film resistor comprises a material selected from the group consisting of NiCr, SiCr, and TaN.
- 20. The integrated circuit of claim 18, wherein said thin film resistor is located between two metal interconnect levels.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The following co-pending applications assigned to Texas Instruments Incorporated are related:
[0002] U.S. Provisional Application Serial No.: 60/156,291, filed Sep. 23, 1999;
[0003] U.S. Provisional Application Serial No.: 60/156,292, filed Sep. 23, 1999;
[0004] U.S. Provisional Application Serial No.: _TI-29881_, filed Jun. 1, 2000;
[0005] U.S. application Ser. No.: 09/406,457, filed Sep. 27, 1999; and
[0006] U.S. application Ser. No.: 091452,694, filed Dec. 2, 1999.
Provisional Applications (3)
|
Number |
Date |
Country |
|
60214996 |
Jun 2000 |
US |
|
60156291 |
Sep 1999 |
US |
|
60156292 |
Sep 1999 |
US |