I. Field
The present invention relates to a system for classifying and recognizing shapes, objects, or signals using large sensor arrays and certain adaptive machine-learning classification algorithms.
II. Background
In present imaging systems, computationally-intensive tasks, such as classification, are achieved using high-performance electronics which take as input, large volumes of raw data from the sensor array. This requires thousands of costly interfaces to many electronic chips. The disclosed approach overcomes this by performing the learning tasks in the same technological platform as the sensors, allowing a reduction of the number of interfaces to subsequent computational blocks.
Typical sensor array implementations require the ability to manufacture the highest quality devices and sensors, posing strong requirements on fabrication. The disclosed approach allows for significant processing variability by using a machine learning algorithm that iteratively trains low performance classifier units (with faulty devices) and combines their ensemble outputs into a single learning decision.
The present invention addresses the issues discussed above by providing a sensing and classification system that addresses the increasingly large number of sensor outputs in detection technology by embedding low-computational-overhead classifier circuitry with large sensor arrays.
An exemplary embodiment of the invention provides a thin-film sensing and classification system, comprising: a plurality of thin-film image sensors; a plurality of thin-film weak classifier circuits, each said classifier circuit coupled to each of said thin-film image sensors; a plurality of threshold comparison circuits; a weighted voter circuit, said weighted voter circuit coupled to said weak classifier circuits via said plurality of threshold comparison circuits; and a summing circuit coupled to each of said weighted voter circuits, wherein said summing circuit is configured to generate a strong classifier decision output.
Another exemplary embodiment of the invention provides a thin-film image sensing and classification system, comprising a plurality of thin-film sensors; a backplane on which said thin-film sensors are mounted; a plurality of thin-film electronic classifier circuits embedded on said backplane and coupled to said plurality of thin-film sensors; and a computational unit coupled to said classifier circuits.
Another exemplary embodiment of the invention provides a sensing and classification system, comprising a plurality of sensors, each said sensor generating an output; a plurality of weak classifiers, wherein each said weak classifier is connected to said output of each sensor of said plurality of sensors; a weighted voter, wherein said weighted voter is connected to said plurality of weak classifiers; and a summing circuit coupled to said weighted voter, wherein said summing circuit is configured to generate a strong classifier decision output.
Additionally, some embodiments of the invention include linear weak classifiers comprising thin-film weak classifier circuits, each such thin-film weak classifier circuit comprising a plurality of subunits, each said subunit comprising a plurality of branches, and each said branch comprising two series connected thin-film transistors; and, wherein each said weak classifier generates differential outputs, and said weak classifier differential outputs are provided to said threshold comparison circuits. Other embodiments of the invention include a trainer circuit, wherein said trainer circuit is coupled to the output of a summing circuit, wherein said trainer circuit is configured to provide feedback to weak classifier circuits and to a weighted voter circuit. In some embodiments of the invention, there is at least one thin-film transistor in each branch of each subunit of each weak classifier, and said thin-film transistor is a variable strength thin-film transistor, wherein a trainer circuit is configured to provide feedback to each said weak classifier circuit via application of a programming voltage to each said variable strength thin-film transistor.
In some embodiments of the invention, the weak classifiers are implemented as decision-trees.
In some embodiments of the invention, a trainer circuit employs an Adaptive Boosting (AdaBoost) machine-learning algorithm to provide bias weights to weak classifier circuits.
For a further understanding of the nature and objects of the present invention, reference should be had to the following description taken in conjunction with the accompanying drawings in which like parts are given like reference numerals.
The images in the drawings are simplified for illustrative purposes and are not depicted to scale. Within the descriptions of the figures, similar elements are provided similar names and reference numerals as those of the previous figure(s). Where a later figure utilizes the same element or a similar element in a different context or with different functionality, the element is provided a different leading numeral representative of the figure number (e.g., 1xx for
The appended drawings illustrate exemplary configurations of the invention and, as such, should not be considered as limiting the scope of the invention that may admit to other equally effective configurations. It is contemplated that features of one configuration may be beneficially incorporated in other configurations without further recitation.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any configuration or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other configurations or designs.
Technological scaling and system-complexity scaling have dramatically increased the prevalence of hardware faults, to the point where traditional approaches based on design margining are becoming inviable. The challenges are exacerbated in embedded sensing applications due to the severe energy constraints. Given the importance of classification functions in such applications, this disclosure presents an architecture for overcoming faults within a classification processor. The approach exploits machine learning for modeling not only complex sensor signals but also error manifestations due to hardware faults. Adaptive boosting is exploited in the architecture for performing iterative data-driven training. This is used to enable the effects of faults in preceding iterations to be modeled and overcome during subsequent iterations.
Machine-learning algorithms are becoming increasingly important in embedded sensing applications. Machine learning enables efficient construction of data-driven models for analyzing signals that are too complex to otherwise model analytically. Given the prominence of recognition/detection functions, frameworks for classification and regression are of particular importance. Recently, studies have also begun to expose the potential that machine learning brings for overcoming non-idealities (technological faults, transistor variations, etc.) affecting the hardware platform itself. An approach known as data-driven hardware resilience (DDHR) enables very high levels of fault tolerance by utilizing a machine-learning stage to model the variances in embedded data caused not only due to the application signals but also due to hardware faults. However, in existing DDHR implementations, the machine-learning stage is explicitly required to be fault protected. For example, two system demonstrations showed that by protecting 7% to 30% of the hardware, performance essentially equivalent to a fault-free system could thus be achieved even with faults affecting 0.02% to 3% of the circuit nodes in the rest of the architecture (resulting in bit error rates of 20-50%). The problem is that the complexity of machine-learning kernels scales strongly with the models required, making their impact on a system substantial, particularly as the hardware platform and application signals both scale in complexity. The present invention is based on an architecture for the machine learning stage (classifier) that is itself allowed to be greatly affected by faults. The presented approach, termed error-adaptive classifier boosting (EACB), takes advantage of adaptive boosting (AdaBoost), which is an iterative training algorithm applied to weak classifiers.
The following is a discussion of DDHR, which is introduced to illustrate the powerful opportunities that machine learning enables for overcoming hardware faults via data-driven training. Then AdaBoost is introduced, which the present invention exploits in a machine-learning kernel that is itself allowed to be highly fault prone, substantially expanding the concept of DDHR.
Data Driven Hardware Resilience (DDHR).
The key to DDHR is utilizing data from an instance of fault affected hardware to construct a model for classification or regression. The resulting model is called an error-aware model; while, generally, faults occur randomly and cause unpredictable errors, the error-aware model represents the data statistics in the presence of the particular occurring faults.
An important characteristic of DDHR is that, thanks to data-driven training, system performance is not limited by the rate or magnitude of errors, but rather more fundamentally by the level of information retained in the error-affected data. A primary limitation of DDHR, however, is the need for substantial fault-protected hardware (machine-learning stages), whose impact increases with increasing system and application-data complexity due to the need for higher-order models. Accordingly, the present invention aims to extend the error-modeling capabilities within the classifier hardware itself. For this we leverage the AdaBoost algorithm, which uses multiple weak classifiers. We show that these enable an architecture wherein high-levels of faults can be overcome through iterative training.
Adaptive Boosting (AdaBoost).
AdaBoost is a machine-learning algorithm that aims to achieve a highly-accurate classifier through a combination of T weak classifiers. The output of a weak classifier is (arbitrarily) weakly correlated with the true class. The algorithm iteratively trains the weak classifiers, establishing both a decision rule and a weight for each iteration. The final hypothesis is then derived from weighted voting over the weak classifiers. So long as each weak classifier performs slightly better than random guessing, the performance is guaranteed to fit a training set perfectly, given enough iterations. However, an important consideration that remains is choosing a weak classifier that results in good generalization over testing data.
A common and effective weak classifier used with AdaBoost is the decision tree. Each node of the tree is a statement about the feature vector being classified, thus determining the next node to be considered, eventually yielding a classification result at the leaf nodes. In practical weak-classifier implementations, as in the case of a decision tree, performance is typically limited by an inadequate decision rule for fitting the training data. In the present invention, the concept is extended, with weak-classifier performance also being limited by errors due to hardware faults. We focus on decision trees, not only because they are empirically shown to be effective weak classifiers, but also because they can be mapped to an implementation that substantially mitigates the amount of control circuitry, thereby minimizing the fault-protected hardware required. As we discuss below, other classifiers may be used besides decision trees, such as linear classifiers.
Additionally, decision trees bring the benefit of comparatively simple training algorithms. Nonetheless, training remains substantially more complex than real time classification. To perform training at run time (with limited data), we develop an algorithm that leverages the idea of the FilterBoost algorithm, but while also substantially reducing the computations and embedded memory required. This thus minimizes the overhead of an embedded trainer.
Error-Adaptive Classifier Boosting.
The aims of EACB are as follows: (1) strong classification, with minimal hardware energy and complexity, based on scalable data driven training; (2) high classifier performance in the presence of very high fault rates; (3) need for minimal fault-protected hardware, both for classification and training. The following subsections describe the EACB architecture and implementation.
EACB Architecture.
EACB is based on the following recognition. A stage whose output function is determined by data-driven training over its set of inputs raises the possibility of overcoming faults in the preceding stages. The errors from faults in the preceding stages can be viewed simply as altering the statistics of the resulting data. EACB uses AdaBoost, wherein the hypotheses generated by preceding weak classifiers are taken as inputs during data-driven training of subsequent iterations. The architecture of EACB is shown in
Weak Classifiers for Maximizing Fault Tolerance.
The choice and implementation of the weak classifiers strongly influences overall performance (i.e., tradeoff between accuracy and diversity), training complexity, and achievable level of fault tolerance. Among the various classifiers that have been considered for boosting (support vector machines, neural networks, decision trees), decision trees enable reduced training complexity and, as described below, enable a specialized implementation that offers high fault tolerance within EACB. A critical aspect for fault tolerance is a circuit's control-path implementation. While data-path faults alter the output statistics, the probability of retaining some correlation with class information remains high, as required of weak learners in AdaBoost. However, control-path faults can result in degenerate outputs, inadequate for even a weak classifier.
Low-Overhead Embedded Trainer.
The challenge with embedded training is the need for a large training set (to address diversity), thus making memory requirements excessive. For example, a standard training algorithm in an exemplary system could require 5,000 feature vectors, corresponding to 420 kB of memory. We have developed a training algorithm that reduces the training data memory through two approaches: (1) feature selection based on a learner metric; and (2) iterative training with small but distinct training sets to mitigate generalization error. For feature selection, each feature is ranked based on its number of occurrences in the decision trees formed during an offline training phase (i.e., for the temporary classifier of
Test System.
To evaluate EACB, we performed hardware experiments using an FPGA. This permits error injection at desired rates and in a randomized manner, enabling controlled characterization. The experimentation details of the embodiment implementing a decision tree classifier are provided below.
Prototype Testing and Potential Application.
For experimental demonstration and evaluation, we applied EACB to a system for EEG-based detection of epileptic seizures. The system consists of a feature-extraction stage and a classifier (which employs EACB). The features correspond to the spectral-energy distribution of 2 EEG channels, across 7 frequency bins, over three 2-second epochs, giving a total of 42 features. The classifier consisted of the architecture in
Alternative Embodiment: Image Classification using TFT Classifier.
As an alternative to the embodiment described above, a different embodiment was also tested in connection with image classification. The following is a description of said alternative embodiment and configuration.
Large-area electronics (LAE) enables the formation of a large number of sensors capable of spanning dimensions on the order of square meters. An example is X-ray imagers, which have been scaling both in dimension and number of sensors, today reaching millions of pixels. However, processing of the sensor data requires interfacing thousands of signals to CMOS ICs, because implementation of complex functions in LAE has proven unviable due to the low electrical performance and inherent variability of the active devices available, namely amorphous silicon (a-Si) thin-film transistors (TFTs) on glass. Envisioning applications that perform sensing on even greater scales, this work presents an approach whereby high-quality image detection is performed directly in the LAE domain using TFTs. The high variability and number of process defects affecting both the TFTs and sensors are overcome using a machine-learning algorithm known as Error-Adaptive Classifier Boosting (EACB) to form an embedded classifier. Through EACB, we show that high-dimensional sensor data can be reduced to a small number of weak-classifier decisions, which can then be combined in the CMOS domain to generate a strong-classifier decision.
To demonstrate the concept, we developed the system in
The photoconductors 430 exhibit strong but non-uniform conductivity change in response to illumination, as shown in the measured I-V characteristic in
Each weak classifier 815 is comprised of a series of M (here thirty-six) subunits 830, where each subunit 830 is comprised of two branches 820, where said branches 820 in a given subunit 830 are configured to implement pseudo-differential outputs, enabling multiplication by positive and negative weighting biases, as required from training. The summation required within the dot product is implemented by combining the branch currents within a weak classifier through a load resistor RWC. The resulting differential weak-classifier outputs VO,1-N can be provided to a CMOS IC (such as weighted voter 850) for threshold comparison and weighted voting, which is found to be somewhat more sensitive to computational errors.
The programmable weighting biases VB, 1-36,1-N of classifier 800 can be implemented by a range of thin-film memory architectures/devices.
Graph 910 shows changes to TFT characteristics as programming voltages are applied for increasing amounts of time, where plot 912 shows the TFT's original state, plot 914 shows the TFT's state after 10 ms of application of programming voltage (e.g., 80 V), and plot 916 shows the TFT's state after 20 ms of application of programming voltage.
Graph 920 shows changes in TFT characteristics after first programing, and second erasure of said programming, where plot 922 shows the TFT's original state, plot 924 shows the TFT's state after 10 ms of application of programming voltage (e.g., 80 V), and plot 926 shows the TFT's state after 10 ms of application of erasure voltage (e.g., −80 V).
Graph 930 shows the changes in TFT threshold voltage as a function of programming time.
To demonstrate system functionality and performance, we performed image classification of five shapes (cross, tee, el, triangle, ring—examples of each are shown, for example, in
One source of error in training weak classifiers is the variation in the resulting weighting biases applied through programming threshold voltage shifts. We measured this variation to have a small standard deviation of approximately 1 V around the intended voltage shift.
As set forth above, one embodiment of the present invention is a thin-film sensing and classification system that can be used to perform, inter alia, classification and recognition of objects or images using large area-sensing arrays. Applications include imaging and other applications including image detection (x-ray, visible, IR), object detection on surfaces equipped with high density sensor planes, automatic sorting of objects (e.g. in a recycling plant) based on sensed physical properties (magnetic, absorption, shape . . . ), and other inferences over distributed sensors.
Said embodiment is able to perform high performance classification of images by using thin-film circuits embedded on the same backplane as a large number of (thin-film) sensors. This is achieved by leveraging a machine learning algorithm that helps to mitigate the effects of variability, failure and process defects common in thin-film technology.
Said embodiment comprises three main parts: a sensor array, thin-film electronic circuits, and a custom computational unit. An exemplary system was constructed with a photoconductor sensor array and thin-film circuits (fabricated using amorphous silicon thin-film transistors) in order to realize an image classification system, e.g., a shape classification system. Said exemplary system is capable of performing high performance classification, with performance close to that of a software-implemented strong classifier. This system can be used in commercial imaging applications that require the ability to discriminate between, for example, different object classes or other visual/physical features. The disclosed approach enables part of the computational classification process to be performed on the same substrate as the sensor array, reducing the interfacing complexity to high performance silicon-integrated circuits.
The present application claims priority from U.S. Provisional Application No. 62/118,118, filed Feb. 19, 2015, which is incorporated herein by reference as if set forth in full below.
This invention was made with government support under Grants No. ECCS1202168 and CCF1218206 awarded by the National Science Foundation and with support under Subaward #2013-01024-04 from the University of Illinois at Urbana-Champaign (Prime MARCO #2013-MA-2385) under Grant No. HR0011-13-0002 awarded by the Department of Defense—DARPA. The government has certain rights in the invention.
Number | Date | Country | |
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62118118 | Feb 2015 | US |