Patent Application
20150129017
This disclosure relates in general to the field of thin film semiconductor processing, and more particularly to lamination stacks for processing thin film solar cells.
Current crystalline silicon (or other semiconductor absorber material) solar cell structures and processing methods often suffer from fabrication complexity and disadvantages relating to etching processes and cell bow and cell cracking/breakage during and/or after cell processing. For high volume manufacturing, solar cell fabrication often includes wet etchant processing (e.g., immersion bath etch, single sided horizontal etch, etc.) throughout the fabrication process which may result in unintended exposure and etching of the solar cell absorber itself or solar cell components. As a result, solar cell fabrication may be limited to certain alternative etching methods which reduce cell exposure to etchant but may also increase fabrication costs and/or decrease manufacturing through-put.
Additionally, solar cell fabrication may also induce significant stresses (e.g., thermal and/or mechanical stresses) on a semiconductor substrate which may lead to thermally-induced warpage and crack generation and propagation (by thermal cycling or mechanical stresses). Bowed or non-planar solar cell substrates pose significant challenges and possible manufacturing yield degradation during solar cell processing (such as during processing of crystalline silicon solar cells), and may present requirements for clamping down the solar cell substrate and/or the substrate edges onto a supporting substrate carrier to flatten the cell substrate during manufacturing process. Flattening solutions may complicate the solar cell manufacturing process, resulting in increased manufacturing cost and/or some manufacturing throughput and yield compromises. Bowed or non-planar solar cell substrates may further result in cell microcracks and/or breakage problems during module lamination and also subsequently during the PV module operation in the field (resulting in PV module power degradation or loss). These problems may be further aggravated in larger area solar cells, such as the commonly used 156 mm×156 mm format (square or pseudo square) solar cells.
Currently, crystalline silicon (both multi-crystalline and mono-crystalline silicon) has the largest market share in the photovoltaics (PV) industry. Moving to thinner crystalline silicon solar cells is understood to be one of the most potent and effective methods for PV cost reduction (because of the relatively high material cost of crystalline silicon wafers used in solar cells as a fraction of the total PV module cost). However, utilizing thinner crystalline wafers is hampered by the problem that thin wafers are extremely fragile, may suffer mechanical breakage during wafer handling and cell processing, and may cause resulting yield production yield losses. Further, using known designs and manufacturing technologies it is often difficult to balance the requirement of high mechanical yield and reduced wafer breakage rate with high manufacturing yields in PV factories in a cost effective manner.
Relating to substrate (semiconductor absorber) thickness, for current crystalline silicon wafer solar cells, moving even slightly thinner than the current thickness range of 140 μm to 200 μm starts to severely compromise mechanical yield during cell and module manufacturing. This is particularly challenging for larger cell sizes such as 156 mm×156 mm and 210 mm×210 mm cells (compared to smaller 125 mm×125 mm cells). Thus, manufacturable solutions directed to process very thin solar cell structures, such as with cell semiconductor absorbers thinner than about 100 μm down to micron-size-scale and submicron thickness, often must utilize a cell process during which the cell is fully supported by a either a temporary and/or a permanent host carrier throughout the process flow.
Therefore a need has arisen for lamination structures which provide etchant protection and structural backplane support for thin film solar cells. In accordance with the disclosed subject matter, backplane lamination stack structures and methods are provided which substantially eliminate or reduces disadvantage and problems associated with previously developed solar cell processing.
According to one aspect of the disclosed subject matter, a lamination stack for etching solar cells is provided. At least two solar cell wafers are attached to corresponding backplane sheets which are larger than the solar cell wafers. Release layers larger than the solar cells and smaller than the backplane sheets are positioned on the backplane sheets on the opposite side of the attached solar cell wafers. The backplane sheets are bonded together along the exposed peripheral boundary formed by the release layers.
Technical advantages of the disclosed subject matter include low processing temperatures, improved surface passivation, and increased optical properties for silicon substrates.
These and other aspects of the disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the claimed subject matter, but rather to provide a short overview of some of the subject matter's functionality. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGUREs and detailed description. It is intended that all such additional systems, methods, features and advantages that are included within this description, be within the scope of any claims.
The features, natures, and advantages of the disclosed subject matter may become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference numerals indicate like features and wherein:
The following description is not to be taken in a limiting sense, but is made for the purpose of describing the general principles of the present disclosure. The scope of the present disclosure should be determined with reference to the claims. Exemplary embodiments of the present disclosure are illustrated in the drawings, like numbers being used to refer to like and corresponding parts of the various drawings.
Thin-film solar cell structures and fabrication process flows may utilize a permanent (and in some instances a temporary carrier) backplane which provides mechanical support, electrical interconnection, and other functionalities. Backplane supported back contact back junction structures may be particularly advantageous for low cost high efficiency solar cells using thin film absorbers. Further, the backplane lamination stacks provided herein may be used for etching silicon solar cells (e.g., monocrystalline or multicrystalline) or semiconductor materials such as compound materials (e.g., gallium arsenide).
After fabrication, this structure may then be processed through additional cell fabrication including etch back, texture, passivation, and metallization processes. During these steps, the laminated cell may be treated as a single 156×156 mm cell during processing, e.g., through wet benches with traditional cassettes. Thus, handling of the wafers (e.g., in and out of a wet bench cassette) requires precise automation or human loading since the thin cell may be slightly flexible. This increased wafer handling sensitivity adds fabrication complexity and may nevertheless result in damaged wafers, wafer surfaces, and wafer edges contacted during wafer handling (i.e., the wafer surfaces in handling contacted). Additionally, during batch wet etch processes (or singled sided horizontal etch for example) the laminate on the rear of the cell of the structure of
As a thin film support structure, a backplane may be laminated to a wafer at various points during solar cell processing (including both front and backside processing). In a particularly advantageous processing embodiment, back side processing in a back contact back junction solar cell structure (e.g., a combination of base and emitter region formation, backside passivation, on-cell metallization, etc.) may be performed prior to backplane lamination and certain frontside processing (e.g., a combination of saw damage removal, organic metal clean, front surface field formation, etch back, texture, passivation, anti-reflective coating, in some instances etch back wafer thinning, etc.) may be performed after backplane lamination. These and other frontside and backside post backplane lamination processes may utilize wet etch processes, such as immersion batch etch or single sided horizontal etch, during which the active backplane surfaces on the cell backside may be exposed to etchant. These backplane surfaces should be preserved (e.g. protected or otherwise resistant to the wet etching processing) and the solar cell and backplane interface protected to restrict etchant from entering into gaps in the solar cell and backplane interface.
The present application provides an innovative and elegant solution for the preservation of active backplane surfaces and the solar cell and backplane interface during wet etch processing. A symmetrical lamination stack having a center release sheet is utilized providing concurrent solar cell processing (e.g., solar cell sunnyside/frontside processing) for at least two solar cells. Among other advantages, the lamination stack disclosed herein: provides a symmetrical and stress balanced solar cell component during lamination and subsequent lamination steps which may mitigate cell bowing after processing; increases the rigidity of the backplane for subsequent process steps; decreases the laminate surface area and lamination parts interface (e.g., at solar cell and backplane) exposed to wet chemistry in wet etch steps; provides a handle at the cell perimeter for wafer handling and minimizing damage to the thin silicon perimeter; and increases through-put of parts at lamination and subsequent process steps. In other words, the disclosed solution provides effective backplane protection during wet etching (e.g. immersion bath etch) while increasing fabrication through-put (at least by a factor of two). Further, the resultant part (lamination structure) is symmetric from front to back thus minimizing stress and bow after lamination and subsequent process steps as material is taken away or added to the exposed solar cell surface (e.g., in solar cell fabrication processes such as wet etch/texture and passivation) thus decreasing processing failures and increasing manufacturing yield.
In the lamination stack provided herein, silicon cells are laminated to corresponding peripherally bonded backplanes separated by a release layer (or in another embodiment silicon cells are laminated to either side of a dual sided backplane having an embedded center release sheet).
In one embodiment, the backplanes (e.g, each having a corresponding attached release sheet) of backplane laminated solar cells are peripherally laminated together and separated by the compressed release sheets. In another embodiment, the solar cells are laminated to a dual-sided backplane sheet having an embedded release layer.
Wet etch processing may include a silicon etch back (e.g, KOH) used to thin a wafer thickness, for example from 200 μm to 60 μm in a wet bath immersion etch during which the lamination stack disclosed provides backplane protection from the wet etchant as well as mechanical wafer support. In other words, after a thinning etch and subsequent cell release along the release layer, the resulting active backplane surface and backplane/cell interface is free from etchant damage caused by etchant exposure. Further, as the lamination structures provided increase the rigidity of the cell and backplane (i.e., decrease the flexibility of the cells) allowing for placement of more cells in a cassette (e.g., in an etch cassette for a wet bench) during an etchant process (i.e., in some instances cells flexing requires empty buffer cassette slots between used cassette slots)—thus further improving through-put beyond concurrent cell processing with two cells per cassette slot by allowing for the use of more slots (i.e., there is less need for buffer cassette slots as the structure has increased rigidity).
After etch processing, additional solar cell fabrication processing such as cell shape definition cuts, texturization, and passivation may be performed while the cells protected by the lamination stack or after the cells are separated along the release layer. Further, this backplane lamination system may be packaged as a flat product having outer solar cell layers and inner backplane lamination films and a center release sheet.
Consumable release sheet materials include a spray-on release coating deposited on the backside of the backplane (i.e., the backplane surface opposite the solar cell absorber) prior to lamination. The release spray may use a physical hard mask to prevent coating of the perimeter handle bonded backplane (e.g., prepreg to prepreg interface), which may should not coated to ensure the perimeter is sealed. Example spray release agents include PTFE based sprays, silicone, and nano-particle based sprays. A spray-on release coating may further reduce cost of lamination materials and the number of parts required during lamination alignment.
The lamination stack provided herein may be used for and incorporated in high-volume solar cell fabrication processes. For example,
After the release/trim cut is complete, the two parts may remain connected by Van der Wall's forces. A slight amount of force may be required to separate the release sheets, for example supplied by using a 156 mm square wafer (200 um thick) slid gently between the two parts (a process which may be automated).
The solar cells are released along the release layer (e.g., Pacolone) for example using an etchant selective to the release layer (i.e., a release sheet temperature or light sensitive or reactive to some form of gas based or liquid chemistry), a mechanical pull or cutting process, or a combination.
During cell processing, alignment of the cell to the backplane (e.g., prepreg) is critical. Scribe lines may be used as fiducials during backplane lamination.
The release (trim) cuts to expose the release layer and remove the laminate handle may be performed using mechanical scribing (cutting with a knife) or laser (e.g., IR pulsed nanosecond laser) down to sub millimeter accuracy. For example, with reference to the dimensions of
The backplane material may be made of a thin (for instance, with a thickness in the range of about 50 microns to about 250 microns thick), flexible, and electrically insulating polymeric material sheet such as an inexpensive aramid fiber prepreg material, such as those commonly used in printed circuit boards, which meets cell process integration and reliability requirements including coefficient of thermal expansion (CTE) matching with the solar cell absorber (e.g., crystalline silicon, mono or multi crystalline, for crystalline silicon solar cells). And while various suitable polymeric (such as plastics, fluropolymers, prepregs, etc.) and suitable non-polymeric materials (such as glass, ceramics, etc.) may be used as the electrically insulating backplane material, the desired backplane material choice depends on many considerations including, but not limited to, cost, ease of process integration, relative CTE match to silicon, thermal stability, chemical resistance, reliability, flexibility/pliability, etc.
Prepreg sheets are used as building blocks of printed circuit boards and may be made from combinations of resins and CTE-reducing fibers or particles. Generally, prepregs are reinforcing materials pre-impregnated with resin and ready to use to produce composite parts (prepregs may be used to produce composites faster and easier than wet lay-up systems). Prepregs may be manufactured by combining reinforcement fibers or fabrics with specially formulated pre-catalyzed resins using equipment designed to ensure consistency. Further, backplane resin content may be adjusted to mitigate cell bow after processing (for example a general trend of higher backplane resin content leading to higher cell bow has been observed). Covered by a flexible backing paper, prepregs may be easily handled and remain flexible/pliable for a certain time period (out-life) at room temperature. The backplane material may be a relatively inexpensive, low-CTE (typically with CTE <10 ppm/° C., or in some instances with CTE <5 ppm/° C.), thin (usually 50 microns to 250 microns, and in some instances in the range of about 50 to 150 microns) prepreg sheet which is relatively chemically resistant to the optional silicon thinning etch chemistry (e.g., alkaline or acidic silicon etch chemistry) and texturization chemicals (e.g., alkaline or acidic silicon texturization chemistry), and is relatively thermally stable at temperatures up to at least 180° C. (and in some instances to temperatures as high about 400° C. during the back-end solar cell processing).
The foregoing description of the exemplary embodiments is provided to enable any person skilled in the art to make or use the claimed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the innovative faculty. Thus, the claimed subject matter is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
This application claims the benefit of U.S. provisional patent application 61/843,849 filed on Jul. 8, 2013 which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61843849 | Jul 2013 | US |
