Patent Application
20090173944
This application claims the priority benefit of Taiwan application serial no. 97100188, filed on Jan. 3, 2008. The entirety the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
1. Field of the Invention
The present invention generally relates to a semiconductor device structure, and more particularly, to a thin film transistor (TFT) structure.
2. Description of Related Art
In a semiconductor process, TFTs usually serve as a switching device. In general, a TFT includes a gate, a gate dielectric layer, a channel layer, a source and a drain, wherein the gate, source and the drain are respectively a single metal layer or a metal stacked layer composed of, for example, aluminum, chromium, tungsten, tantalum or titanium. In the above-mentioned conductive materials, aluminum has been broadly used in TFT electrode structures because of its low cost and unique properties thereof such as low resistivity, good adhesiveness onto a substrate and good etching characteristics easily to proceed an etching process, wherein the TFT electrodes include, for example, gate, source and drain.
However, aluminum has a large coefficient of thermal expansion (CTE), so that the thermal strain is easily produced between an aluminum layer and a substrate through heat treatment process, for example, annealing. Moreover, a mismatch of thermal strain between the aluminum layer and the substrate is created, wherein the aluminum layer suffers extreme stress during the annealing process and consequently the aluminum atoms in metallurgical structures diffuse along boundaries of aluminum crystal grains, which further leads to a formation of hillocks (or termed as aluminum hillocks). The hillocks may cause of current leakage, short-circuit, open-circuit or other faults affecting the TFT performance.
To solve the above-mentioned problem, one of the conventional solutions is to respectively form a molybdenum nitride layer on the aluminum layer and between the aluminum layer and the substrate so as to form a triple-layer structure of molybdenum nitride layer-aluminum layer-molybdenum nitride layer (MoN—Al—MoN), wherein the molybdenum nitride layers function to cover the boundaries of aluminum crystal grains to prevent the aluminum atoms from diffusing along the boundaries of aluminum crystal grains, and to lighten the above-mentioned mismatch of thermal strains because the molybdenum nitride layer has a CTE less than that of the aluminum layer. In this way, the prior art is able to avoid the formation of the hillocks.
In fact, during conducting a thin film deposition process of the molybdenum nitride layer by using, for example, reactive sputtering process, the process easily causes defects on the substrate surface. In more detail, when the reactive sputtering process uses molybdenum (Mo) as the target material and mixed gas of argon (Ar) and nitrogen (N) are taken as reaction gas, the Mo atoms sputtered through bombardment by ions would combine with the ionized N atoms, N ions or N atom free-radicals in plasma and form molybdenum nitride (MoN) deposited on the substrate. However, on the other hand, gas-phase nucleation often occurs in the chemical reactive environment during the thin film deposition process and the particles produced from the gas-phase nucleation are directly adsorbed or deposited onto the substrate surface and then form defects on the substrate surface. In addition, it is easily to cause micro arcing during the reactive sputtering process and the surface of the molybdenum target may bombarded through the micro arcing to produce a great deal of micro particles, wherein the micro particles also cause surface defects. In order to avoid the above-mentioned problem, the molybdenum nitride layer can be substituted by a molybdenum layer so as to form a triple structure of molybdenum layer-aluminum layer-molybdenum layer (Mo—Al—Mo triple-layer structure), wherein the method of forming a molybdenum layer can excluded the reactive sputtering process, thus, the above-mentioned problem can be significantly solved.
Accordingly, the present invention is directed to a TFT capable of avoiding formation of undercuts during the fabrication thereof.
The present invention is also directed to an active device array substrate, wherein the structure of the active device is capable of avoiding formation of undercuts during the fabrication process, and therefore the reliability of the pixels is effectively promoted.
The present invention is further directed to a liquid crystal display panel (LCD panel) capable of avoiding formation of the undercuts in the process and improving the display quality of the LCD panel.
The present invention provides a TFT, which includes a substrate, a gate, a gate dielectric layer, a channel layer, a source and a drain. The gate and the gate dielectric layer are disposed on the substrate, the gate dielectric layer covers the gate, the channel layer is disposed on the gate dielectric layer above the gate, and the source and the drain are respectively disposed on a part of the channel layer at both sides of the gate, wherein at least one of the gate, the source and the drain has a lower conductive layer, an upper conductive layer and an intermediate conductive layer located between the lower conductive layer and the upper conductive layer. The material of the lower conductive layer is different from that of the intermediate conductive layer, and the thickness of the lower conductive layer is less than or equal to about 150 Å (angstrom).
The present invention provides an active device array substrate, which includes a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixels. The scan lines and the data lines are disposed on the substrate, and the pixels are disposed on the substrate and electrically connected to the corresponding scan lines and data lines. Each of the pixels includes an active device and an electrode electrically connected to the active device, and at least one of the active devices includes a gate, a gate dielectric layer, a channel layer, a source and a drain. The gate and the gate dielectric layer are disposed on the substrate, the gate dielectric layer covers the gate, the channel layer is disposed on the gate dielectric layer above the gate and the source and the drain are respectively disposed on a part of the channel layer at both sides of the gate, wherein at least one of the gate, the source and the drain has a lower conductive layer, an upper conductive layer and an intermediate conductive layer located between the lower conductive layer and the upper conductive layer. The material of the lower conductive layer is different from that of the intermediate conductive layer, and the thickness of the lower conductive layer is less than or equal to about 150 Å.
The present invention provides an LCD panel, which includes an active device array substrate, an opposite substrate and a liquid crystal layer disposed therebetween. The active device array substrate includes a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixels. The scan lines and the data lines are disposed on the substrate, and the pixels are disposed on the substrate and electrically connected to the corresponding scan lines and data lines. Each of the pixels includes an active device and an electrode electrically connected to the active device, and at least one of the active devices includes a gate, a gate dielectric layer, a channel layer, a source and a drain. The gate and the gate dielectric layer are disposed on the substrate, the gate dielectric layer covers the gate, the channel layer is disposed on the gate dielectric layer above the gate and the source and the drain are respectively disposed on a part of the channel layer at both sides of the gate, wherein at least one of the gate, the source and the drain has a lower conductive layer, an upper conductive layer and an intermediate conductive layer located between the lower conductive layer and the upper conductive layer. The material of the lower conductive layer is different from that of the intermediate conductive layer, and the thickness of the lower conductive layer is less than or equal to about 150 Å. The opposite substrate is disposed at the opposite side of the active device array substrate, and the liquid crystal layer is disposed between the opposite substrate and the active device array substrate.
In an embodiment of the present invention, the TFT further includes an etching stop layer disposed over the channel layer.
In an embodiment of the present invention, the TFT further includes a heavily-doped semiconductor layer disposed between the channel layer and the source and between the channel layer and the drain.
In an embodiment of the present invention, the thickness of the above-mentioned lower conductive layer is about 100 Å.
In an embodiment of the present invention, the thickness of the intermediate conductive layer ranges from about 1200 Å to about 6000 Å.
In an embodiment of the present invention, the thickness of the upper conductive layer is ranges from about 100 Å to about 2000 Å.
In an embodiment of the present invention, the materials of the lower conductive layer and upper conductive layer include molybdenum (Mo), titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), columbium (Nb), neodymium (Nd), a combination of the above-mentioned elements, an alloy of the above-mentioned elements or a nitride of the above-mentioned elements.
In an embodiment of the present invention, the material of the above-mentioned intermediate conductive layer includes aluminum (Al), copper (Cu), a combination of the above-mentioned metals or an alloy of aluminum-copper.
In an embodiment of the present invention, the active device further includes an etching stop layer disposed over the channel layer.
In an embodiment of the present invention, the active device further includes a heavily-doped semiconductor layer disposed between the channel layer and the source and between the channel layer and the drain.
In an embodiment of the present invention, the materials of the scan line and gate have a same composition, and the materials of the data line and the drain have a same composition.
In an embodiment of the present invention, the active device array substrate further includes at least a pad disposed on the substrate and the pad is electrically connected to the scan line or the data line, wherein the pad has a pad lower conductive layer, a pad upper conductive layer and a pad intermediate conductive layer. The pad intermediate conductive layer is located between the pad lower conductive layer and the pad upper conductive layer. The material of the pad lower conductive layer is different from the material of the pad intermediate conductive layer, and the thickness of the pad lower conductive layer is less than or equal to about 150 Å.
In an embodiment of the present invention, the opposite substrate includes a color filter substrate.
Since at least one of the gate, the source and the drain in the TFT of the present invention has a lower conductive layer, an intermediate conductive layer and an upper conductive layer, and the thickness of the lower conductive layer is less than or equal to about 150 Å, therefore, the structure of the present invention is able to avoid formation of undercut of the gate, the source or the drain, which may improve the reliability of the TFT and retain the desired electrical performance thereof and the normal operation of the pixel, so that the display quality of the LCD panel may be effectively promoted.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Still referring to
Note that the present invention can effectively overcome the undercut problem in the process caused by the prior art through controlling the thickness of the lower conductive layer 112. In more detail, the thickness of the lower conductive layer 112 can be controlled as required by the design, for example but not limited to less than or equal to about 150 Å, and preferably, for example, about 100 Å. In this way, the undercut formed in the fabrication process of the gate 202 can be avoided. For example, in the gate 202 of the embodiment, when the thickness of the lower conductive layer is controlled to be less than or equal to about 150 Å, the lower conductive layer contributes to protect the Mo—Al—Mo multi-layer structure from damage during the etching process. On the other hand, the lower conductive layer 112 and the upper conductive layer 116 of the present invention can serve as a buffer layer for the intermediate conductive layer 114 so as to effectively prevent the intermediate conductive layer 114 from damage in the subsequent process. Therefore, compared to the prior art, the present invention not only avoids the formation of hillocks on the aluminium layer but also avoids the formation of undercuts.
According to an embodiment of the present invention, the gate 202, the source 210s and the drain 210d respectively having a lower conductive layer with a thickness less than or equal to about 150 Å, an intermediate conductive layer and an upper conductive layer may be formed, for example, by the following process. First, a lower conductive material layer (not shown), an intermediate conductive material layer (not shown) and an upper conductive material layer (not shown) are sequentially formed on the substrate 200. Next, a patterned photoresist layer including the electrode pattern is formed on the upper conductive material layer above substrate 200. Next, using the patterned photoresist layer as a mask to perform a wet etching process on the triple conductive material layer to form an electrode. In general, when an electrode includes a conductive stacked layer composed of different materials, the etching rates of each conductive material layer is different, which tends to form undercuts at the electrode. However, it is possible to effectively overcome the formation of undercuts in the conductive stacked layer in a wet etching process by controlling the thickness of the lower conductive layer. Therefore, it is possible to effectively avoid the gate 202, the source 210s or the drain 210d from damage during the fabrication process and thereby retain the desired performance of the TFT 201.
Referring to
The gate 202 of the active device 216 is electrically connected to the corresponding scan line 230, and the source 210s is electrically connected to a data line 240. The active device 216 comprises, for example, a protection layer 212 to cover the gate dielectric layer 204, the channel layer 206, the source 210s and the drain 210d, and the pixel electrode 218 is disposed on the protection layer 212 and electrically connected to the drain 210d through a via hole 214. In the embodiment, the material of the scan line is substantially the same as that of the gate 202, and the material of the data line 240 is substantially the same as that of the source 210s and the drain 210d. In other words, the scan line 230 in the embodiment may have a lower conductive layer 112, an intermediate conductive layer 114 and an upper conductive layer 116 as well and the thickness of the lower conductive layer 112 is less than or equal to about 150 Å. In other embodiments where the source 210s and the drain 210d have the same structure, the data line 250 may have the same structure as that of the source and the drain.
In this way, in the embodiment where the scan line 230 or the data line 250 has a structure including a lower conductive layer 112 with a thickness ranging in a specific scope, an intermediate conductive layer 114 and an upper conductive layer 116, the structure of the present invention is able to effectively avoid the formation of the undercuts at the scan lines or the data lines by controlling the thickness of the lower conductive layer 112, which further avoids a possible open-circuit problem due to the formation of the undercuts during the patterning process on the scan line or the data line and ensure the desired operation of the pixels.
Referring to
Since the gate, the source, the drain or a combination of the said gate, source and drain of at least an active device among a plurality of active devices in the LCD panel 10 has a lower conductive layer, an intermediate conductive layer and an upper conductive layer wherein the thickness of the lower conductive layer is less than or equal to about 150 Å, therefore, formation of undercuts during the fabrication of the active device would be unlikely. Moreover, it can avoid the scan line or the data line having the above-mentioned stacked layer structure from open-circuit problem due to formation of undercuts, which ensures the normal operation of the pixels and thereby promote the display quality of the LCD panel.
In summary, the gate, the source, the drain or a combination of the said gate, source and drain of the present invention comprises a lower conductive layer, an intermediate conductive layer and an upper conductive layer. By controlling the thickness of the lower conductive layer, the formation of the undercut during the etching process used for fabricating the electrode (for example, the gate, the source or the drain) may be avoided. Moreover, the opening circuit issue of the scan line and the data line due formation of the undercuts may be avoided, and therefore the desired performances of the TFT, and the desired operation of the pixels and the display quality of the LCD panel may be effectively promoted.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 97100188 | Jan 2008 | TW | national |
