BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with reference to the accompanying drawings, wherein:
FIGS. 1A-1C show schematic cross sections of a mechanism for forming coffee rings;
FIG. 2A-2F show schematic cross sections of processes for forming an upper gate TFT of a first embodiment of the invention;
FIG. 3A shows an equivalent circuitry of a separate dual devices TFT of a first embodiment of the invention;
FIG. 3B shows an equivalent circuitry of combining the separate dual devices TFT of FIG. 3A into one device TFT;
FIG. 4 shows a device electric measurement curve of an upper gate TFT of a first embodiment of the invention;
FIG. 5 shows a schematic cross section of a upper gate CMOS TFT of a second embodiment of the invention;
FIG. 6 shows a schematic cross section of a bottom gate TFT of a third embodiment of the invention;
FIG. 7 shows a schematic cross section of a bottom gate CMOS TFT of a fourth embodiment of the invention;
FIG. 8 shows a schematic cross section of a dual-gate TFT of a fifth embodiment of the invention;
FIG. 9 shows a schematic cross section of a dual-gate CMOS TFT of a sixth embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. The description is provided for illustrating the general principles of the invention and is not meant to be limiting. The scope of the invention is best determined by reference to the appended claims.
The invention utilizes an inkjet printing technology and the natural phenomenon of a solution drop drying into a coffee ring to make a micro-line structure of the coffee ring ridge. A micro-line structure having two ridges can be utilized in fabricating dual TFT and CMOS devices. Additionally, the dual TFT can be further connected into one device to reduce area, simplify process, and enhance yield rate.
The conventional electric device only uses one ridge of the coffee ring such that the gap between the devices is increased and not suited for high density and high resolution applications. The ridge of the coffee ring can be treated to adjust the contact angle with a solution such that a self-alignment effect can be achieved. The invention uses two ridges of the coffee ring in combination with electrode design and inkjet printing to form the three types of devices as described in the following.
1. Two devices with one end connected, which can be used for simplifying circuit structure and reducing area of a device with more than two TFTs.
2. A CMOS device having N type and P type soluble semiconductor or semiconductor precursor material disposed on two adjacent channels by inkjet printing respectively.
3. A Dual-gate TFT increasing the effective channel width of a TFT and enhancing device current.
Thus, the device can be fabricated into an amplifier circuit, a feedback circuit, a CMOS or a dual-gate TFT.
FIRST EMBODIMENT
FIGS. 2A-2F show cross sections of fabrication steps of a first embodiment of the invention. Referring to FIG. 2A, a substrate 20, such as glass, silicon, plastic substrate or other flexible substrate, is first provided. The selected substrate is then cleaned and treated by a surface treatment step such as plasma treatment. A polymer solution is inkjet printed by a sprinkle-nozzle on the substrate 20 into a dot or a line shape, and then dried into a coffee ring film 21. The polymer may be, but is not limited to, poly(3-alkylthiophene) (P3AT), poly(9,9-dioctylfluorene-co-bithiophene) (F8T2), polymethyl methacrylate (PMMA), poly(4-vinylphenol) (PVP), polyvinyl alcohol (PVA), polyacrylonitrile (PAN), polyimide (PI), or polyoxymethylene (POM). The polymer is dissolved in a solvent into a solution for inkjet printing. The solvent includes a watery liquid or an oily liquid.
Referring to FIG. 2B, a central part 23 of the coffee ring film 21 is removed by an etching method, and two coffee ring ridges 22 are left as a separating layer. The width of the ridge is about 1˜50 μm, and the height of the ridge is about 100˜5000 Å. If the polymer solution is inkjet printed on the substrate 20 into the shape of a line, two parallel micrometer scale lines are formed on the substrate. As shown in FIG. 2B, the coffee ring ridges 22 are treated with plasma 25 to make the coffee ring ridges 22 hydrophobic and to increase affinity of coffee ring ridges 22 to a semiconductor solution. The utilized plasma gas may be O2, N2, CF4, SF6 or combinations thereof. The etching method may be a surface micro-etching method, but is not limited to plasma treatment, which can be practiced by dipping, spraying, dispensing, printing or combinations thereof. The spraying, dispensing or printing is practiced by sprinkling a solvent on the substrate to etch the thin central part of the coffee ring.
FIG. 2C shows a solution of conductive material inkjet printed on the coffee ring ridge 22 into two separate areas due to the hydrophobic coffee ring ridge. The two separate areas are formed into films on the two sides of the ridge as a source layer 24 and a drain layer 26. The solution of conductive material may be an inkjet printed electrode material, or an ink solution of conductive polymer, wherein poly-3,4-ethylenedioxythiophene (PEDOT) or nanometal solution such as nanosilver paste is preferable.
Referring to FIG. 2D, a semiconductor layer 28 is inkjet printed or coated on the coffee ring ridge 22, and portions of the source layer 24 and the drain layer 26 adjacent to the coffee ring ridge 22. The semiconductor layer is formed from a solution of semiconductor material which can be inkjet printed. The semiconductor material may be, but is not limited to the following materials or combinations thereof: a nanoderivative of an inorganic semiconductor such as ZnO; a derivative of a carbon cluster such as [6,6]-phenyl C61-butyric acid methyl ester (PCBM), pentacene precursor, P3AT, or F8T2; other semiconductor materials with negative charge which contain the cyanogen group or the heterocycle group, for example, dicyano perylene-3,4,9,10-bis(dicarboximides) (PDI-CN2) or derivatives thereof. The semiconductor layer can also be formed by vacuum deposition or vapor deposition, and the materials thereof may be an organic semiconductor material such as pentacene or PCBM.
Referring to FIG. 2E, an upper gate dielectric layer 30 is inkjet printed, coated or vacuum deposited on the semiconductor layer 28, the source layer 24 and the drain layer 26. The upper gate dielectric layer can be formed of an organic or inorganic insulating material. The organic insulating material is, for example, PMMA, PVP, PVA, PAN, PI or POM. The inorganic insulating material is, for example, SiO2, Ta2O5, Al2O3, or Si3N4. The material of the upper gate dielectric layer also may be combinations of the stated organic polymer and the inorganic nanoderivative.
Referring to FIG. 2F, an upper gate layer 32 is finally inkjet printed or coated on the upper gate dielectric layer 30 and aligned with the separating layer 22 to form a TFT. The upper gate layer can be formed from a metal or a solution of conductive material. The conductive material is, for example, PEDOT or nanosilver paste. The metal is, for example, Ag, Al, Au, alloys thereof or combinations thereof. The structure of the metal may comprise one, or more than one layer.
An equivalent circuitry of the TFT of FIG. 2F is as shown in FIG. 3A, wherein the TFT is a separated a dual device type TFT. All applications based on this kind of circuitry can utilize the TFT structure of the invention. The conductive films inkjet printed on the exterior sides of the two ridges are connected into a common electrode. An equivalent circuitry connecting method is shown as FIG. 3B. The dual devices of the TFT are combined into one device such that two channels are connected into one wider channel to enhance the current of the device.
The invention can complete a high current, micro-length gate, interconnecting dual devices, and dual current devices by inkjet printing, vacuum or low pressure film forming methods or combinations thereof, without requiring photolithography and etching processes.
An electric measurement curve of the device with a structure of one ridge is shown as FIG. 4, wherein the separating layer 22 is comprised of PMMA, the source layer 24 and the drain layer 26 are comprised of PEDOT, the semiconductor layer 28 is made of P3AT, the upper gate dielectric layer 30 is comprised of PVP, and the upper gate layer is comprised of PEDOT. The mobility of the organic TFT formed from the above materials is above 8.81*10−2 cm2/V−s and the gate critical voltage (Vt) is about 3.89V. As shown in FIG. 4, the drain current is labeled as Id, the gate voltage is labeled as Vg, and the drain voltage is labeled as Vd.
SECOND EMBODIMENT
In the second embodiment of the invention, the different semiconductor materials are inkjet printed on the two ridges, one is N type semiconductor, and the other is P type semiconductor, thus completing a CMOS TFT structure.
As shown in FIG. 5, a substrate 20 is first provided, and then two ridges 22 of the coffee ring are formed on the substrate 20 as a separating layer. A source layer 24 and a drain layer 26 are disposed on opposite sides of the ridge 22. A P type semiconductor layer 27 is disposed on one ridge 22 and portions of the source/drain layer. An N type semiconductor layer 29 is disposed on the other ridge 22 and portions of the source/drain layer. A gate dielectric layer 30 is disposed on the P type semiconductor layer 27, the N type semiconductor layer 29, the source layer 24 and the drain layer 26. A gate layer 32 is disposed on the gate dielectric layer 30, corresponding to the ridges 22. In the second embodiment, with the exception of the P type semiconductor layer 27 and the N type semiconductor layer 29, the material and fabrication method of the other layers are the same as the first embodiment. In the second embodiment, the material of the P type semiconductor layer 27 is preferably pentacene, P3AT or a derivative of PF polymer. The material of the N type semiconductor layer 29 is preferably ZnO, PCBM, or other semiconductor material with negative charge, which contain the cyanogen group or the heterocycle group, for example, dicyano perylene-3,4,9,10-bis(dicarboximides) (PDI-CN2). The P type and N type semiconductor layers are both formed by inkjet printing.
THIRD EMBODIMENT
According to the structure of the first embodiment, wherein the substrate can be replaced by a substrate having a conductive layer and an inorganic gate dielectric layer, and the upper gate layer and the upper gate dielectric layer can be removed to form a bottom gate device.
The third embodiment of the invention is as shown in FIG. 6. A substrate 40 is first provided. A bottom gate layer 42 is disposed on the substrate 40, and the patterning process thereof is not required. The material of the bottom gate layer 42 may be a heavily doped N type or P type semiconductor such as a heavily doped Si, Ge, or GaAs; an organic conductive film such as PEDOT; or a metal or an inorganic conductive film such as ITO, IZO, Ag, Au, Al, or Cr. A bottom gate dielectric layer 44 is disposed above the bottom gate layer 42, and underlying a separating layer 46 and a source/drain layer 48/50. The material of the bottom gate dielectric layer 44 may be an inorganic insulating material, an organic insulating material or combinations thereof, the material is preferably an inorganic insulating material such as SiO2, Ta2O5, Al2O3, or Si3N4.
After cleaning and surface treating the bottom gate dielectric layer 44, the other layers include the ridges 46, the source layers 48, the drain layer 50, and the semiconductor layers 52 are formed on the bottom gate dielectric layer 44 to complete a bottom gate TFT device according to the material and fabrication method of the first embodiment.
FOURTH EMBODIMENT
The difference between the fourth and the third embodiments is that the material of the semiconductor layers inkjet printed on the two ridges of the fourth embodiment are different. The difference between the fourth and the second embodiments is that, in the fourth embodiment, a bottom gate structure is used in the fourth embodiment. The fourth embodiment use N type semiconductor inkjet printed on one ridge, and P type semiconductor inkjet printed on the other ridge to form a CMOS TFT.
As shown in FIG. 7, a substrate 40 is first provided. A bottom gate layer 42 is then disposed on the substrate 40. A bottom gate dielectric layer 44 is disposed above the bottom gate layer 42, and underlying a separating layer 46 and a source/drain layer 48/50. The P type semiconductor layer 51 is disposed on one ridge 46 and portions of the source/drain layer 48/50. The N type semiconductor layer 53 is disposed on the other ridge 46 and portions of the source/drain layer 48/50. The positions of the P type and N type semiconductor layers can be exchanged. The material of the P type semiconductor layer 51 is the same as the first embodiment. The material of the N type semiconductor layer 53 is the same as the second embodiment. The material and fabrication method of the bottom gate layer 42 and the bottom gate dielectric layer 44 are the same as the third embodiment. The material and fabrication method of the other layers are the same as the first embodiment.
FIFTH EMBODIMENT
Combining the structures of the first and the third embodiments and using the upper gate and the bottom gate structures can form a TFT device with double gate structure. Thus, the operative current and on/off ratio of the TFT device, and the performance of the device can be enhanced.
The fifth embodiment of the invention is as shown as FIG. 8. A substrate 40 is first provided. A bottom gate layer 62 is disposed on the substrate 40 and a bottom gate dielectric layer 64 is disposed on the bottom gate layer 62. The material of the three layers is the same as the third embodiment. After cleaning and surface treatment of the bottom gate dielectric layer 64, the other layers including the ridges 66, the source layers 68, the drain layer 70, the semiconductor layers 72, the upper gate dielectric layer 74 and the upper gate layer 76 are formed on the bottom gate dielectric layer 64 to form a double gate TFT with an upper gate 76 and a bottom gate 62 according to the material and fabrication method of the first embodiment.
SIXTH EMBODIMENT
The difference between the sixth and the fifth embodiments is that the materials of the semiconductor layers inkjet printed on the two ridges of the sixth embodiment are different. The sixth embodiment uses N type semiconductor inkjet printed on one ridge, and P type semiconductor inkjet printed on the other ridge to form a double gate CMOS TFT.
As shown in FIG. 9, a substrate 60 is first provided. A bottom gate layer 62 is then disposed on the substrate 40 and a bottom gate dielectric layer 64 is then disposed on the bottom gate layer 62. The materials of the layers 62 and 64 are the same as the fifth embodiment. After cleaning and surface treating the bottom gate dielectric layer 64, the other layers include the ridges 66, the source layers 68, the drain layer 70, the P type semiconductor layer 71, the N type semiconductor layer 73, the upper gate dielectric layer 74 and the upper gate layer 76 are formed on the bottom gate dielectric layer 64 to form a double gate CMOS TFT according to the material and fabrication method of the first and second embodiments.
In the first to sixth embodiments, a piezoelectric or a thermal bubble type nozzle performs the inkjet printing.
The invention provides the following advantages:
1. The width of the micro-line of the coffee ring formed by inkjet printing can be about 1˜50 μm, thus the channel length of the TFT shrinks and the operative current thereof is enhanced.
2. The channels of TFTs formed by inkjet printing can provide TFTs with a circular or linear shape.
3. The inkjet printing of the invention can be performed with organic materials which is extendable and flexible, thus the device can be formed on a flexible substrate to widen the application range.
4. TFTs formed by inkjet printing in combination with the coffee ring effect can fabricate two channels at one time to form a dual TFT device, or the two devices can be connected into one device to enhance the yield rate or increase the channel width thereof, such that the area of the device can be reduced and the open rate is increased.
5. N type and P type semiconductor materials inkjet printed on the two adjacent channels or the two adjacent positions of the same ridge formed by inkjet printing can form a TFT with COMS structure to widen the applications thereof.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20080054257
