THIN-FILM TRANSISTOR ARRAY AND METHOD OF MANUFACTURING THE SAME

Abstract

A thin-film transistor array includes a substrate and thin-film transistors positioned in matrix on the substrate. The thin-film transistors each include source and drain electrodes formed on a gate insulation layer, and a semiconductor layer formed on the gate insulation layer and positioned between the source and drain electrodes. The semiconductor layer is formed in stripes over the plurality of thin-film transistors such that one of the stripes has a long axis direction coinciding with a channel width direction of one of the thin-film transistors. The semiconductor layer has a cross section in a short axis direction of the stripe such that a thickness of the semiconductor layer gradually decreases outwardly from a center portion of the stripe.

Description

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a thin-film transistor array and a method of manufacturing the same.

DISCUSSION OF THE BACKGROUND

Due to the remarkable development of information technology, information is frequently transmitted/received, currently, with laptop computers or portable information terminals. It is commonly accepted that a ubiquitous society in which information can be exchanged anywhere will be attained in near future. In such a society, lighter and slimmer information terminals are desirable.

Silicon based materials are mainstream semiconductor materials currently, and photolithography is generally used as a method of manufacturing semiconductors.

Printed electronics that is a technique of manufacturing electrical components using a printing technique is attracting attention in recent years. Use of a printing technique can achieve advantages such as of reducing cost incurred in equipment and manufacture compared to photolithography, and enabling use of a plastic substrate which does not need a vacuum and high temperature environment. Further, use of a printing process is advantageous in that materials are highly efficiently utilized, and development and etching can be omitted, leading to producing a smaller amount of waste liquid. Thus, only low environmental loads are imposed by such a printing process.

However, the printing process is likely to produce patterns with low uniformity in film thickness compared to photolithography. For example, when a semiconductor layer in a transistor is formed as described in PTL 1, various printing states can arise depending on the printing conditions, although not described in PTL 1, and accordingly variable transistor characteristics are obtained. Further, the electric current in a transistor array depends on the thickness of the semiconductor film, which may lead to low uniformity in transistor characteristics.

PTL 1: JP-A 2006-063334

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a thin-film transistor array includes a substrate and thin-film transistors positioned in matrix on the substrate. The thin-film transistors each include a gate insulation layer, a source electrode formed on the gate insulation layer, a drain electrode formed on the gate insulation layer, and a semiconductor layer formed on the gate insulation layer and positioned between the source electrode and the drain electrode. The semiconductor layer is formed in stripes over the plurality of thin-film transistors such that one of the stripes has a long axis direction coinciding with a channel width direction of one of the thin-film transistors. The semiconductor layer has a cross section in a short axis direction of the stripe such that a thickness of the semiconductor layer gradually decreases outwardly from a center portion of the stripe.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a schematic plan view illustrating a thin-film transistor array according to an embodiment.

FIGS. 2(a) and 2(b) are diagrams including a schematic plan view and a schematic cross-sectional view illustrating a thin-film transistor according to an example.

FIGS. 3(a) and 3(b) are diagrams including a schematic plan view and a schematic cross-sectional view illustrating a thin-film transistor according to another example.

FIGS. 4(a)-4(c) are diagrams including enlarged schematic cross-sectional views each illustrating a cross-sectional shape of a semiconductor layer of a thin-film transistor.

FIGS. 5(a) and 5(b) are diagrams including a schematic plan view and a schematic cross-sectional view illustrating a thin-film transistor according to a comparative example.

FIGS. 6(a) and 6(b) are diagrams including a schematic plan view and a schematic cross-sectional view illustrating a thin-film transistor according to an example.

FIG. 7 is a graph showing a relationship of a maximum thickness of a semiconductor film, with the on- and off-currents, in a thin-film transistor according to an example.

FIG. 8 is a graph showing a relationship of a distance between a maximum thickness position and a channel center of a semiconductor film, with mobility, in the case when the semiconductor width of a thin-film transistor according to an example is changed.

FIG. 9 is a graph showing a relationship of a distance between a maximum thickness position and a channel center of a semiconductor film, with mobility, in the case when the channel length of a thin-film transistor according to an example is changed.

DESCRIPTION OF THE EMBODIMENTS

The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.

A thin-film transistor array according to an embodiment of the present application will be described with reference to the drawings. FIG. 1 is a schematic plan view illustrating a thin-film transistor array 1. FIGS. 2(a) and 2(b) are diagrams including a schematic plan view of a thin-film transistor 2 and a schematic cross-sectional view taken along the line a-b of the plan view according to an example of a thin-film transistor configuring the thin-film transistor array 1.

As shown in FIGS. 2(a) and 2(b), the thin-film transistor 2 comprises a gate electrode 21, a gate wiring 22 and a capacitor electrode 23, a gate insulation layer 11 formed on these elements, a pixel electrode 25, a drain electrode 26, a source electrode 27 and a source wiring 28 formed on the gate insulation layer 11, and a semiconductor layer 121 formed between the source electrode 27 and the drain electrode 26 on the gate insulation layer 11. As shown in 11) FIG. 1, the thin-film transistor array 1 is formed by arranging a plurality of thin-film transistors 2 in a matrix on an insulative substrate 10. Further, a connection is established between the gate electrode 21 and the gate wiring 22, between the source electrode 27 and the source wiring 28, and between the pixel electrode 25 and the drain electrode 26.

As shown in FIGS. 1-2(b), the semiconductor layer 121 is formed in a stripe shape across the plurality of thin-film transistors 2, with the long axis direction of the stripe coinciding with the channel width direction of the transistor. Specifically, the semiconductor layer 121 is formed such that a distance d of 10 μm or less in plan view is ensured between a portion (thick portion) 12M of the semiconductor layer 121 with a maximum thickness in the short axis direction of the stripe shape semiconductor layer and a center 29 of the channel.

The thin-film transistor 2 configured as described above can achieve high-performance transistor characteristics because the position of the thick portion of the semiconductor layer 121 falls within the channel region if the semiconductor layer 121 is displaced to an extent corresponding to approximately the channel length when forming the semiconductor layer 121. In particular, when the relationship between the thickness of the semiconductor layer 121 and the on-current of the transistor at a predetermined voltage is plotted, the on-current tends to be saturated at a predetermined thickness d1 as a boundary. Specifically, when the thickness of the semiconductor layer 121 of the channel region is larger than the threshold (thickness d1), uniformity of the transistor characteristics improves in the thin-film transistor array. Further, when the relationship between the thickness of the semiconductor layer 121 and the off-current is plotted, the off-current tends to increase in excess of a predetermined thickness d2.

Further, as shown in FIG. 2 (b), the semiconductor layer 121 may have a cross-sectional shape in the short axis direction, in which the thickness gradually decreases towards both directions from the center of the semiconductor stripe area. It should be noted that the thickness of the semiconductor layer 121 referred to herein is not the height of the semiconductor layer 121. Namely, the thickness of the semiconductor layer 121 on the source electrode 27 and the drain electrode 26 is obtained by subtracting the height of the source electrode 27 or the drain electrode 26 from the height of the semiconductor layer 121. FIG. 2 (b) shows that the maximum thickness 12M of the semiconductor layer 121 is larger than the thickness of the source electrode 27 and the drain electrode 26, but the maximum thickness 12M of the semiconductor layer 121 may be smaller than or equal to the thickness of the source electrode 27 and the drain electrode 26.

In the thin-film transistor 2 configured as described above, a part of the semiconductor layer 121 extending out of the channel region without directly contributing to the drain current can be made thinner to reduce the usage amount, thereby reducing cost of the transistor. However, the part of the semiconductor layer 121 extending out of the channel region and present on the source electrode 27 and the drain electrode 26, plays a role of contacting the source electrode 27 and the drain electrode 26 and indirectly contributes to the drain current. Therefore, the semiconductor layer 121 preferably overlaps the source electrode 27 and the drain electrode 26 to some extent (e.g., an overlap of 15 μm or more).

FIGS. 3(a) and 3(b) are diagrams including a schematic plan view and a schematic cross-sectional view taken along the line c-d of the plan view according to an example of the thin-film transistor configuring the thin-film transistor array 1. It should be noted that the components common with the thin-film transistor 2 are designated with the same reference signs to omit duplicate description.

As shown in FIG. 3 (b), a stripe shaped semiconductor layer 122 of the thin-film transistor 3 has a cross-sectional shape in the short axis direction in which the thickness gradually decreases towards lateral directions from the center of the semiconductor stripe area in the channel length direction. Furthermore, the cross-sectional shape has sub-peaks 13 on both ends of the semiconductor layer 122. The sub-peaks 13 each have a thickness smaller than the thickness 12M of the center portion.

The thin-film transistor 3 configured as described above can achieve high-performance transistor characteristics because the position of the thick portion of the semiconductor layer 122 falls within the channel region if the semiconductor layer 122 is displaced to an extent corresponding to approximately the channel length when forming the semiconductor layer 122.

Further, as shown in FIG. 3 (b), the sub-peaks 13 may overlap with the source electrode 27 and the drain electrode 26 in plan view.

The thin-film transistor 3 configured as described above can reduce the contact resistance between the semiconductor layer 122 and the source electrode 27 or the drain electrode 26, and thus 11) high-performance transistor characteristics can be obtained. For example, satisfactory characteristics can be obtained if the contact length (length across which the semiconductor layer 122 contacts the surface of the source electrode 27 or the drain electrode 26) is designed to be about 5 μm.

FIGS. 4(a)-4(c) shows a set of diagrams each showing a cross-sectional shape of the semiconductor layer 121 or 122. The diagrams FIGS. 4(a) and 4(b) are examples of the semiconductor layer 121 of the thin-film transistor 2. In both diagrams, the film thickness gradually decreases in the width direction (right-and-left direction in FIGS. 4(a)-4(c)) that is the short axis direction. FIG. 4 (c) is an example of the semiconductor layer 122 of the thin-film transistor 3. The semiconductor layer 122 has a thickness which gradually decreases in the width direction (right-and-left direction in FIGS. 4(a)-4(c)) that is the short axis direction and increases on both ends, and forms the respective sub-peaks 13 (h2) each having a thickness smaller than a thickness (h1) of the center portion.

A flexible substrate is desirably used as the insulative substrate 10. Examples of generally used material include plastic materials, such as polyethylene terephthalate (PET), polyimide, polyethersulfone (PES), polyethylene naphthalate (PEN) and polycarbonate. A glass substrate such as quartz or a silicon wafer can be used as the insulating substrate 10, but a plastic substrate is preferably used in consideration of the reduction in thickness and weight and achievement of flexibility. Further, in consideration of the temperature used for the manufacturing processes, PEN or polyimide is desirably used as the substrate 10.

The materials used for the electrodes are not specifically limited, but the materials generally used for forming the thin films of the electrodes include metals and oxides, such as gold, platinum, nickel and indium tin oxide, solutions dispersed with a conductive polymer, such as poly (ethylenedioxythiophene)/polystyrene sulfonate (PEDOT/PSS) or polyaniline, or dispersed with metal colloidal particles such as of gold, silver or nickel, or thick film pastes using metal particles such as of silver, as a conductive material. Further, the method of forming the electrodes is not specifically limited, but a dry deposition method, such as vapor deposition or sputtering may be used. However, considering flexibility and cost reduction, a wet deposition method, such as screen printing, reverse offset printing, relief printing, or an inkjet method, is desirably used.

The materials used for the gate insulation layer 11 are not specifically limited, but generally used materials include polymer solutions such as of polyvinyl phenol, polymethylmethacrylate, polyimide, polyvinyl alcohol or an epoxy resin, or solutions dispersed with particles such as of alumina or silica gel. Further, a thin film made of PET, PEN or PES may be used as the gate insulation layer 11.

The materials used for the semiconductor layer 121 or 122 are not specifically limited, but generally used materials include high-molecular-weight organic semiconductor materials, such as polythiophene, polyallylamine, fluorene-bithiophene copolymer and derivatives thereof, and low-molecular-weight organic semiconductor materials, such as pentacene, tetracene, copper phthalocyanine, perylene and derivatives thereof. However, to achieve cost reduction, flexibility and area increase, it is desirable to use an organic semiconductor material to which a printing method can be applied. Further, carbon compounds, such as carbon nano-tubes or fullerene, or a semiconductor nano-particle dispersion may be used as a semiconductor material. Printing methods that can be used for forming the organic semiconductor layer include known methods, such as gravure printing, offset printing, screen printing and ink-jet methods. Generally, the semiconductor materials mentioned above have low solubility in a solvent, and thus it is desirable to use a method, such as relief printing, reverse offset printing or ink jet method, or a method using a dispenser, suitable for low viscosity solutions. Relief printing is particularly preferable since the short printing period can reduce the amount of ink used and thus reduce the cost incurred in printing by increasing the usage efficiency of the ink, in conjunction with reducing environmental load compared to photolithography. Also, relief printing is suitable for printing the stripe shaped semiconductor layer 121 or 122. Further, the semiconductor layer 121 or 122 formed into a stripe shape can contribute to averaging the distribution of thickness variation in a stripe shape area due to the unevenness of an anilox roll to thereby fix the thickness of the semiconductor layer 121 or 122 and make the TFT properties uniform. Further, the cross-sectional shape of the semiconductor layer 121 or 122 in terms of thickness can be easily achieved by using relief printing and optimizing the printing conditions.

The thin-film transistor array 1 may be provided with a sealing layer 30, a gas barrier layer (not shown), a planarizing film (not shown), an interlayer insulation film 31, an upper pixel electrode 32, and the like, as needed (FIGS. 6(a) and 6(b)). FIGS. 6(a) and 6(b) show a thin-film transistor 5 obtained by forming the sealing layer 30 covering the semiconductor layer 121, the interlayer insulation film 31 having an opening on the pixel electrode 25, and the upper pixel electrode 32 connected to the pixel electrode 25 via the opening, on the thin-film transistor 2 shown in FIGS. 2(a) and 2(b). FIGS. 6(a) and 6(b) are diagrams including a schematic plan view and a schematic cross-sectional view taken along the line g-h of the plan view. Specifically, when an organic semiconductor material is used as the semiconductor layer 121 or 122, the semiconductor layer 121 or 122 may be damaged by the solvent or the like, depending on the material of the interlayer insulation film 31. Therefore, it is preferable to provide the sealing layer 30 between the semiconductor layer 121 or 122 and the interlayer insulation film 31 (insulating layer formed on the semiconductor layer 121 or 122, the source electrode 27, and the drain electrode 26).

FIGS. 6(a) and 6(b) show an example in which the thin-film transistor 2 of FIGS. 2(a) and 2(b) is provided thereon with the sealing layer 30, the interlayer insulation film 31, and the upper pixel electrode 32. Alternatively, the sealing layer 30, the interlayer insulation film 31, and the upper pixel electrode 32 may be provided on the thin-film transistor 3 of FIGS. 3(a) and 3(b). Also, a display medium can be sandwiched between the thin-film transistor array shown in FIGS. 2(a)-3(b) or FIGS. 6(a)(b) and a counter substrate having a counter electrode to thereby provide a display. In this case, in FIG. 2(a)(b) or 3(a)(b), the pixel electrode 25 applies a voltage to the display medium to contribute to displaying, and in FIGS. 6(a) and 6(b), the upper pixel electrode 32 applies a voltage to the display medium to contribute to displaying. In this case, it is desirable that the thin-film transistor array of FIG. 2(a)(b) or 3(a)(b) further includes a sealing layer 30, with the sealing layer 30 covering not only the semiconductor layer 121, but also the source electrode 27 and the source wiring 28. Alternately, it is desirable that the thin-film transistor array of FIG. 2(a)(b) or 3(a)(b) further includes a sealing layer 30 and an interlayer insulation film 31, with the sealing layer 30 covering at least the semiconductor layer 121, and with the interlayer insulation film 31 covering the source electrode 27 and the source wiring 28.

In thin film transistor arrays, source and drain are named for the sake of convenience, and thus may be named conversely. The electrode connected to the source wiring is referred to as a source electrode, and the electrode connected to the pixel electrode is referred to as a drain electrode.

Hereinafter, examples will be described.

The carrier mobility [cm²/Vs] which can be suitably applied to an electronic device of a display device, such as an electronic paper, is preferably 0.1 or more as a target value. Further, it is preferable that an on-current is 0.5 μA or more and an off-current is 0.5 μA or less.

EXAMPLE 1

Example 1 will be described. In the present example, a thin-film transistor array was fabricated using bottom-gate bottom-contact type thin-film transistors 2 as shown in FIGS. 1-2(b) (enlarged view and cross-sectional view). A polyethylene naphthalate (PEN) film was used as the substrate 10. A gate electrode 21, a gate wiring 22, a capacitor electrode 23, and a capacitor wiring 24 were formed on the substrate 10 by use of an ink jet method and an ink having dispersed silver nanoparticles. Polyimide was applied as a gate insulation layer 11 by use of a die coater, followed by drying for 1 hour at 180° C., thereby forming the gate insulation layer 11. Then, a source electrode 27, a drain electrode 26, a source wiring 28 and a pixel electrode 25 were formed on the gate insulation layer 11 by use of an ink jet method and an ink having dispersed silver nanoparticles. Poly[2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene] was used as the semiconductor material. As a preliminary experiment, a thin-film transistor was formed with inclusion of a semiconductor layer whose thickness had been changed using a spin-coating method, followed by measuring the drain current. The drain current increased with the increase of the thickness of the semiconductor layer, but the drain current was saturated at 50 nm or more. Then, dichlorobenzene having 0.5 wt % of poly[2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene] dissolved therein was used as an ink. Further, a relief printing plate made of a photosensitive resin was used to print a stripe shaped semiconductor by relief printing, followed by drying for 60 minutes at 180° C., thereby forming a semiconductor layer 121. The stripe shaped semiconductor layer 121 had a cross-sectional shape in which the center portion was thick but gradually thinned towards both sides, and the thickness of the portion 12M with a maximum thickness was 70 nm. The distance d in plan view was 5 μm, the distance d being the length between the portion 12M of the stripe shaped semiconductor layer with the maximum thickness and the center 29 of the channel region. As a result, high-performance transistor characteristics were obtained, and uniformity of the transistor characteristics was high in the thin-film transistor array.

EXAMPLE 2

Elements of a striped semiconductor layer 121 (having a shape in which the center portion was thick but gradually thinned towards both sides) were fabricated by the same method as in Example 1. The semiconductor layer 121 had a channel length of 10 μm, a width of 100 μm, a maximum thickness of 15 nm, 25 nm, 50 nm, 70 nm, 100 nm, 150 nm or 200 nm, and had a distance d=0 μm between the maximum thickness portion and the center of the channel. In this case, an Id at Vd=−15V and Vg=−20V was taken to be an on-current, and an Id at Vd=−15V and Vg=+20V was taken to be an off-current, and the values were plotted as shown in FIG. 7. The on-current was 0.5 μA or more when the maximum thickness was 25 nm or more, and the off-current was 0.5 pA or less when the maximum thickness was 150 nm or less. In all cases, uniformity of the transistor characteristics was high.

EXAMPLE 3

Elements of a striped semiconductor layer 121 (having a shape in which the center portion is thick but gradually thinned towards both sides) were fabricated by the same method as in Example 1. The semiconductor layer 121 had a channel length of 10 μm, a maximum thickness of 70 nm, a width of 50 μm, 70 μm, 100 μm or 150 μm, and had the distance d=0 μm, 5 μm, 10 μm, 15 μm, 20 μm, 30 μm, 40 μm or 50 pm between the maximum thickness portion and center of the channel, and mobility in this case was plotted as shown in FIG. 8. A mobility of 0.1 cm²/Vs or more was obtained when the distance d was 10 μm or less between the maximum thickness portion and the channel center. In all cases, uniformity of the transistor characteristics was high.

EXAMPLE 4

Elements of a striped semiconductor layer 121 (having a shape in which the center portion is thick but gradually thinned towards both sides) were fabricated by the same method as in Example 1. The semiconductor layer 121 had a maximum thickness of 70 nm, a width of 100 μm, a channel length of 5 μm, 10 μm, 20 μm, 30 μm or 40 μm, and had the distance d=0 μm, 5 μm, 10 μm, 15 μm, 20 μm, 30 μm, 40 μm, or 50 μm between the maximum thickness portion and the center of the channel, and mobility in this case was plotted as shown in FIG. 9. A mobility of 0.1 cm²/Vs or more was obtained when the distance d was 10 μm or less between the maximum thickness portion and the channel center. In all cases, uniformity of the transistor characteristics was high.

EXAMPLE 5

Example 5 will be described. In the present example, a thin-film transistor array was fabricated using the bottom-gate bottom-contact type thin-film transistors 3 shown in FIG. 1 and FIGS. 3(a) and 3(b) (enlarged view and cross-sectional view). Example 5 was similar to Example 1, except that the pressing amount when the ink was transferred to the substrate 10 in forming the semiconductor layer 122 was increased by 20 μm compared to in Example 1. In this case, the semiconductor layer 122 had a cross-sectional shape in terms of thickness in which the center portion was thick but gradually thinned towards both sides, with the sub-peaks 13 being further provided. The portion 12M with a maximum thickness had a thickness of 70 nm, while the sub-peaks each had a thickness of 40 nm in both ends of the cross section of the semiconductor layer in the channel length direction. Further, the distance d in plan view was 5 pm between the portion 12M having the maximum thickness and the center 29 of the channel region. Thus, high-performance transistor characteristics were obtained and high uniformity was achieved in the transistor characteristics of the thin-film transistor array.

Example 6

The elements of the striped semiconductor layer 122 (having a shape in which the center portion was thick but gradually thinned towards both sides, with sub-peaks being further provided) were fabricated by the same method as in Example 5. The semiconductor layer 122 had a channel length of 10 μm, a maximum thickness of 70 nm, a sub-peak thickness of 40 nm, a width of 50 μm or 100 μm, and had the distance d=0 μm, 5 μm, 10 μm, 15 μm, 20 μm, 30 μm or 40 μm between the maximum thickness portion and the center of the channel, and mobility was plotted as shown in FIG. 8 by hollow marks. A higher mobility than in Example 3 was obtained when an overlap of the source and drain electrodes with the semiconductor layer in width direction was 5 μm to 15 μm. In all cases, uniformity of the transistor characteristics was high.

COMPARATIVE EXAMPLE

A Comparative Example will be described. The Comparative Example was similar to Example 1, except that the printing conditions in Example 1 were changed such that the semiconductor layer had a cross-sectional shape in terms of thickness in which the center portion was not thinned towards both sides, with no provision of sub-peaks. Under such printing conditions, the thickness of the semiconductor layer was uneven, and the current characteristics of the channel portion varied. Thus, in the Comparative Example, uniformity of the transistor characteristics was low.

Consequently, the thin-film transistor arrays of the Examples were confirmed to have uniformity in the transistor characteristics.

Further, it was also confirmed that higher transistor characteristics were achieved if a 10 μm or less distance was ensured between the portion of the semiconductor layer with the maximum thickness and the center of the channel region in the channel length direction.

An embodiment of the present invention is a thin-film transistor array with high uniformity in transistor characteristics.

An aspect of the present invention is a thin-film transistor array in which a plurality of thin-film transistors are arranged in a matrix on a substrate, the thin-film transistors each including a source electrode and a drain electrode formed on a gate insulation layer, and a semiconductor layer formed on the gate insulation layer so as to be located between the source electrode and the drain electrode. In the thin-film transistor array, the semiconductor layer is formed into a stripe shape across the plurality of thin-film transistors, with a long axis direction of the stripe coinciding with a channel width direction of a transistor, the semiconductor layer having a cross section in the short axis direction of the stripe such that the semiconductor layer has a thickness gradually decreasing outwardly from a center of the semiconductor.

The stripe of the semiconductor layer may have a cross-sectional shape in the short axis direction such that a 10 μm or less distance is ensured between a portion of the semiconductor layer with a maximum thickness and the center of the channel region relative to a channel length direction.

The portion of the semiconductor layer with a maximum thickness may have a thickness in a range of 25 nm or more to 150 nm or less.

The stripe of the semiconductor layer may have a cross-sectional shape in a short axis direction such that the semiconductor layer has a thickness gradually decreasing outwardly from a center, with sub-peaks being provided on both ends of the semiconductor layer, the sub-peaks each having a thickness smaller than the thickness of the center portion.

The sub-peaks on both ends of the semiconductor layer may respectively overlap, in plan view, with the source electrode and the drain electrode.

Another aspect of the present invention is a method of manufacturing the aforementioned thin-film transistor array including a step of forming the semiconductor layer using a relief printing method.

According to the embodiments of the present invention, a high quality thin-film transistor array with high uniformity in the transistor characteristics is provided by permitting a portion with a maximum thickness in a cross section of the stripe shaped semiconductor layer to approximately coincide with the center of the channel.

INDUSTRIAL APPLICABILITY

The technique described in the present application is useful for thin-film transistor arrays, and thus is useful for electrophoretic displays, liquid crystal displays, and the like which use the thin-film transistor arrays based on the technique described in the present application.

REFERENCE SIGNS LIST

1 Thin-film transistor array

2,3,4 Thin-film transistor

10 Substrate

11 Gate insulation layer

121,122,123 Semiconductor layer

12M Portion of semiconductor layer with maximum thickness

13 Sub-peak

21 Gate electrode

22 Gate wiring

23 Capacitor electrode

24 Capacitor wiring

25 Pixel electrode

26 Drain electrode

27 Source electrode

28 Source wiring

29 Channel center line

30 Sealing layer

31 Interlayer insulation film

32 Upper pixel electrode

Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Claims

1. A thin-film transistor array, comprising: a substrate; anda plurality of thin-film transistors positioned in matrix on the substrate, the thin-film transistors each including a gate insulation layer,a source electrode formed on the gate insulation layer,a drain electrode formed on the gate insulation layer, anda semiconductor layer formed on the gate insulation layer and positioned between the source electrode and the drain electrode,wherein the semiconductor layer is formed in stripes over the plurality of thin-film transistors such that one of the stripes has a long axis direction coinciding with a channel width direction of one of the thin-film transistors, andthe semiconductor layer has a cross section in a short axis direction of the stripe such that a thickness of the semiconductor gradually decreases outwardly from a center portion of the stripe.

2. The thin-film transistor array of claim 1, wherein the semiconductor layer has a channel region and is formed such that a portion of the semiconductor layer having a maximum thickness is positioned at a distance of 10 μm or less from a center line in a channel length direction of the channel region.

3. The thin-film transistor array of claim 2, wherein the distance is in a range of from 5 μm to 10 μm.

4. The thin-film transistor array of claim 1, wherein a portion of the semiconductor layer with a maximum thickness has a thickness in a range of from 25 nm to 150 nm.

5. The thin-film transistor array of claim 2, wherein the portion of the semiconductor layer with a maximum thickness has a thickness in a range of from 25 nm to 150 nm.

6. The thin-film transistor array of claim 2, wherein the portion of the semiconductor layer with a maximum thickness has a thickness in a range of from 25 nm to 70 nm.

7. The thin-film transistor array of claim 2, wherein the portion of the semiconductor layer with a maximum thickness has a thickness in a range of from 70 nm to 150 nm.

8. The thin-film transistor array of claim 3, wherein the portion of the semiconductor layer with a maximum thickness has a thickness in a range of from 25 nm to 70 nm.

9. The thin-film transistor array of claim 3, wherein the portion of the semiconductor layer with a maximum thickness has a thickness in a range of from 70 nm to 150 nm.

10. The thin-film transistor array of claim 1, wherein the semiconductor layer forming the stripe has a cross section in a short axis direction such that a thickness of the semiconductor layer gradually decreases outwardly from a center portion, and that sub-peaks are present in both end portions of the semiconductor layer and each have a thickness smaller than the thickness in the center portion of the semiconductor layer.

11. The thin-film transistor array of claim 2, wherein the semiconductor layer forming the stripe has a cross section in a short axis direction such that a thickness of the semiconductor layer gradually decreases outwardly from a center portion, and that sub-peaks are present in both end portions of the semiconductor layer and each have a thickness smaller than the thickness in the center portion of the semiconductor layer.

12. The thin-film transistor array of claim 4, wherein the semiconductor layer forming the stripe has a cross section in a short axis direction such that a thickness of the semiconductor layer gradually decreases outwardly from a center portion, and that sub-peaks are present in both end portions of the semiconductor layer and each have a thickness smaller than the thickness in the center portion of the semiconductor layer.

13. The thin-film transistor array of claim 10, wherein the sub-peaks on both end portions of the semiconductor layer overlap respectively with the source electrode and the drain electrode in a plan view.

14. The thin-film transistor array of claim 11, wherein the sub-peaks on both end portions of the semiconductor layer overlap respectively with the source electrode and the drain electrode in a plan view.

15. The thin-film transistor array of claim 12, wherein the sub-peaks on both end portions of the semiconductor layer overlap respectively with the source electrode and the drain electrode in a plan view.

16. A method of manufacturing the thin-film transistor array according to claim 1, comprising: forming the plurality of thin-film transistors in matrix on the substrate such that the thin-film transistors each include the source and drain electrodes and the semiconductor layer on the gate insulation layer,wherein the forming of the thin-film transistors includes forming the semiconductor layer by a relief printing method.

17. A method of manufacturing the thin-film transistor array according to claim 2, comprising: forming the plurality of thin-film transistors in matrix on the substrate such that the thin-film transistors each include the source and drain electrodes and the semiconductor layer on the gate insulation layer,wherein the forming of the thin-film transistors includes forming the semiconductor layer by a relief printing method.

18. A method of manufacturing the thin-film transistor array according to claim 4, comprising: forming the plurality of thin-film transistors in matrix on the substrate such that the thin-film transistors each include the source and drain electrodes and the semiconductor layer on the gate insulation layer,wherein the forming of the thin-film transistors includes forming the semiconductor layer by a relief printing method.

19. A method of manufacturing the thin-film transistor array according to claim 10, comprising: forming the plurality of thin-film transistors in matrix on the substrate such that the thin-film transistors each include the source and drain electrodes and the semiconductor layer on the gate insulation layer,wherein the forming of the thin-film transistors includes forming the semiconductor layer by a relief printing method.

20. A method of manufacturing the thin-film transistor array according to claim 13, comprising: forming the plurality of thin-film transistors in matrix on the substrate such that the thin-film transistors each include the source and drain electrodes and the semiconductor layer on the gate insulation layer,wherein the forming of the thin-film transistors includes forming the semiconductor layer by a relief printing method.