BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-section view of the unit structure of a conventional a-Si TFT array.
FIG. 2A-2F are cross-sectional views of the unit structure of the TFT array manufactured, each corresponding to in a process of the method according to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIGS. 2A-2F, according to which one embodiment of the present invention will be described thoroughly. These drawings show the processes for manufacturing the TFT array in terms of a single unit.
Now referring to FIG. 2A, a first transparent conducting material 300, such as ITO (indium tin oxide) or IZO (indium zinc oxide) is deposited on a glass substrate 200. A first metal 400, such as multi-layer film of AlNd or Mo, is deposited on the first transparent conducting material 300.
Next, a first photolithography process is performed on the first transparent conducting material 300 and the first metal 400 with a first photomask. Dry etching or wet etching is used to form a gate 500, a scan line 600, a pixel electrode 700, a first electrode 800 of the storage capacitor and a first transparent conducting layer 900 for the scan pad on the substrate 200. Among them, each of the gate 500, the scan line 600 and the first electrode 800 of the storage capacitor consists of a first transparent conducting layer 300 and a layer of first metal 400, while each of the pixel electrode 700 and the first transparent conducting layer 900 for the scan pad is formed of the first transparent conducting layer 300 which is covered with the layer of first metal 400. The result is shown in FIG. 2B.
In the structure shown in FIG. 2B, a gate-insulating material, such as SiNx, a semiconductor material, i.e., a-Si, and a doped semiconductor material, i.e., n-type a-Si, are deposited in sequence. Then, a second photolithography process is performed on the three layers of materials described above with a second photomask, which is a gray-tone mask. Dry etching or wet etching is used to form an island-like active region 1300 consisting of a gate-insulating layer 1000, a layer of semiconductor 1100 and a layer of doped semiconductor 1200, as shown in FIG. 2C. Exposure through the gray-tone mask leads to a spatial variation of thickness after the process of etching. The photomask has differences of transparency and thus the photoresist undergoes various levels of exposure dose, which makes different thicknesses in the photoresist region when the process of development is done. According to the present invention, the various thicknesses fabricated over the structure depends on the design of the gray-tone mask. Moreover, the active region 1300 covers the gate 500, having a transporting channel 1400 formed inside the layer of semiconductor 1100. The result is shown in FIG. 2C.
According to the present invention, the portion of the layer of semiconductor 1100 on the first electrode 800 of the storage capacitor has a thickness defined in the process with gray-tone mask. Reducing the thickness of the layer of semiconductor 1100 by using a design of the gray-tone mask may increase the capacitance of the storage capacitor and, therefore decrease the area of the storage capacitor, thereby increasing the aperture ratio of the pixel.
As compared to dry etching, which can not control the etching level precisely, wet etching may remove selected layers of material by using an appropriate etchant of low etch selectivity ratio to those layers. This embodiment preferably adopts a process of wet etching, wherein a etchant is used that has low etch selectivity ratio to the layer of first metal 400 while has high etch selectivity ratio to the first transparent conducting layer 300. This will remove the portions of the layer of first metal 400 on the pixel electrode 700 and on the first transparent conducting layer 900 for the scan pad, as shown in FIG. 2C. The result is shown in FIG. 2D.
Referring to FIG. 2E, a passivation material, e.g., SiNx, is subsequently deposited. Then, a process of back-side exposure is performed on the passivation material so as to form a passivation layer 1600, wherein the layer of first metal that has been patterned serves as a photomask such that the passivation layer 1600 is right above the transporting channel 1400, or the gate 500, and the scan line 600 and that a dielectric region 1500 of the storage capacitor is formed due to the stacking of the passivation layer 1600, the gate-insulating layer 1000 and the layer of semiconductor 1100. In the way of the back-side exposure according to the present invention, the layer of first metal 400 comprised in the gate 500, in the scan line 600 and in the first electrode 800 of the storage capacitor functions as a photomask so that the passivation layer 1600 is formed right above the transporting channel 1400, the scan line 600 and the first electrode 800 of the storage capacitor. Thus, the present invention fulfills the purpose of protecting the TFT devices.
Next, referring to FIG. 2F, a second metal is deposited, which is suitable for a source/drain. A third photolithography process is performed on the second metal deposited with a third photomask to form a source 1710, a drain 1720, a data line 1730 and a second electrode 1740 of the storage capacitor. Moreover, a scan pad 1800 may be formed that consists of a layer of the second metal and the first transparent conducting layer 900 for the scan pad. The second metal includes, for example, a multi-layer film of AlNd or Mo, and a second transparent conducting layer (e.g., ITO or IZO covers and protects the multi-layer film against degradation).
According to the embodiments of the present invention, as shown in FIG. 2F for example, the TFT array is disposed on a substrate 200 and each unit of the TFT array includes: a transistor, a pixel electrode 700, a scan line 600, a data line 1730, a passivation layer 1600 and a storage capacitor. The transistor includes a gate 500, a source 1710, a drain 1720 and an active region 1300. The active region 1300 is formed by depositing a gate-insulating layer 1000, a layer of semiconductor 1100 and a layer of doped semiconductor 1200 in sequence on a substrate 200. The gate 500 is disposed on the substrate 200 and is under the gate-insulating layer 1000. The source 1710 and drain 1720 are disposed on the layer of doped semiconductor 1200 respectively and are electrically connected via a transporting channel 1400. The transporting channel 1400 is formed inside the layer of semiconductor 1100. The pixel electrode 700 is disposed on the substrate 200 and outside of the active region 1300, and electrically connected to the drain 1720 for the n-type TFT or to the source 1710 for the p-type TFT. The scan line 600 is disposed on the substrate 200 and under the gate-insulating layer 1000. The data line 1730 is disposed on a portion of the layer of doped semiconductor 1200 and vertically intersected with the scan line 600. The passivation layer 1600 is disposed on the layer of semiconductor 1100. The storage capacitor has a first electrode 800 of the storage capacitor disposed on the substrate 200 and under the gate-insulating layer 1000, a second electrode 1740 of the storage capacitor disposed on the passivation layer 1600, and a dielectric region 1500 of the storage capacitor interposed between the first electrode 800 of the storage capacitor and the second electrode 1740 of the storage capacitor, wherein the dielectric region 1500 of the storage capacitor is formed by stacking the gate-insulting layer 1000, the layer of semiconductor 1100 and the passivation layer 1600 in sequence from the first electrode 800 to the second electrode 1740 of the storage capacitor.
According to the embodiments of the present invention, as shown in FIG. 2F, each unit of the TFT array further comprises a scan pad 1800 disposed on the edge of the substrate 200. The scan pad 1800 includes a layer of second metal and the first transparent conducting layer 900 for the scan pad.
According to the embodiments of the present invention, the gate 500, the scan line 600 and the first electrode 800 of the storage capacitor are formed, respectively, with a first transparent conducting layer and a layer of first metal stacked in sequence on the substrate 200. The pixel electrode 700 is made of a first transparent conducting layer. Further, the scan pad 1800 is formed with the first transparent conducting layer and a second metal stacked in sequence on the substrate 200. The source 1710, the drain 1720, the data line 1730 and the second electrode 1740 of the storage capacitor are made of the second metal. The second metal includes, for example, a multi-layer film of metal, and a second transparent conducting layer covers the multi-layer film.
As described above, the TFT array and the method of manufacturing the same according to the present invention, which comprises only three photomask processes, can reduce the manufacturing cost, shorten the manufacturing procedure and increase the production efficiency and the market power. Additionally, the invention can utilize a gray-tone mask designed for reducing the thickness and, relatively, the area of the storage capacitor, thereby increasing the aperture ratio of each TFT. The invention can take a way of back-side exposure to make a passivation layer above at least the transporting channel in order that the TFT can be protected by the layer. Furthermore, a transparent conducting layer can be used for the source, the drain, the data line and the second electrode of the storage capacitor and/or the scan pad, so as to reduce the resistance effectively and to increase reliability and yield of the TFTs.
While the invention has been described in detail with certain preferable embodiments, this description is not intended to limit the invention for which other embodiments may be possibly employed. In particular, the invention is not only applicable to a-Si TFTs, but also to poly-silicon TFTs or any one that is based on suitable semiconductor material. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.
Patent Application
20070243673
