Patent Application
20250015192
This application claims priority to Chinese Patent Application No. 202310831160.X, filed in the China National Intellectual Property Administration on Jul. 6, 2023, the disclosure of which is hereby incorporated by reference in its entirety.
The present disclosure relates to a technical field of display, and in particular to a thin film transistor, an array substrate, and a display panel.
A thin film transistor (TFT) is a core device of a display panel. Depending on semiconductor material of an active layer of the thin film transistor, the thin film transistor mainly includes an oxide semiconductor thin film transistor and an amorphous silicon semiconductor thin film transistor. The oxide semiconductor thin film transistors has attracted wide attention due to its high mobility, excellent uniformity, good transparency, low cost, and the like, and is increasingly applied to large-sized high-resolution display fields. However, the oxide semiconductor device is prone to generate photogenerated carriers under light, which affects the stability of the oxide semiconductor thin film transistor.
An embodiment of the present disclosure provides a thin film transistor including a gate, a source, a drain, and an active layer. The active layer includes a first oxide layer and a second oxide layer that are stacked, the source and the drain are both located at a side of the second oxide layer away from the first oxide layer, the first oxide layer is a crystalline oxide layer, and the second oxide layer is a lanthanide oxide layer.
The gate is disposed at a side of the first oxide layer or the second oxide layer, and when the gate is disposed at a side of the first oxide layer away from the second oxide layer, an atomic proportion of an indium element in the first oxide layer is greater than an atomic proportion of an indium element in the second oxide layer; when the gate is disposed at the side of the second oxide layer away from the first oxide layer, the atomic proportion of the indium element in the first oxide layer is less than the atomic proportion of the indium element in the second oxide layer.
In a thin film transistor provided in an embodiment of the present disclosure, the atomic proportion of the indium element in the first oxide layer gradually decreases in a direction away from the gate, and the atomic proportion of the indium element in the second oxide layer gradually decreases in the direction away from the gate.
In a thin film transistor provided in an embodiment of the present disclosure, an atomic proportion of an oxygen element in the first oxide layer gradually increases in the direction away from the gate, and an atomic proportion of an oxygen element in the second oxide layer gradually increases in the direction away from the gate.
In a thin film transistor provided in an embodiment of the present disclosure, a number of atoms of the indium element in the first oxide layer accounts for 50% to 100% of a number of atoms of a metal element in the first oxide layer, and a proportion of a number of atoms of the oxygen element in the first oxide layer ranges from more than 50%; a number of atoms of the indium element in the second oxide layer accounts for 50% to 100% of a number of atoms of a metal element in the second oxide layer, and a proportion of a number of atoms of the oxygen element in the second oxide layer ranges from more than 50%.
In a thin film transistor provided in an embodiment of the present disclosure, a proportion of a number of atoms of lanthanide in the lanthanide oxide layer ranges from 0.05% to 3%.
In a thin film transistor provided in an embodiment of the present disclosure, the thin film transistor further includes a first auxiliary layer provided corresponding to the active layer, and the first auxiliary layer is disposed at the side of the first oxide layer away from the second oxide layer.
In a thin film transistor provided in an embodiment of the present disclosure, the thin film transistor further includes a second auxiliary layer provided corresponding to the active layer, and the second auxiliary layer is disposed at the side of the second oxide layer away from the first oxide layer.
In a thin film transistor provided in an embodiment of the present disclosure, the second auxiliary layer includes an insulating portion and conductor portions located at both sides of the insulating portion, and the conductor portions are provided corresponding to the source and the drain respectively.
An embodiment of the present disclosure further provides an array substrate including the thin film transistor of one of the foregoing embodiments.
An embodiment of the present disclosure further provides a display panel including a first substrate and a second substrate disposed opposite to each other, one of the first substrate and the second substrate includes an array substrate of one of the foregoing embodiments.
In order to more clearly explain the embodiments or the technical solutions in the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art, and it may be apparent that the drawings in the following description are only some embodiments of the present disclosure. For those skilled in the art, without paying any creative work, other drawings can be obtained based on these drawings.
The following description of the embodiments is made with reference to the accompanying drawings to illustrate specific embodiments in which the present disclosure may be implemented. The direction terms mentioned in the present disclosure, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], and the like, are only the direction of the attached drawings. Therefore, the directional terms used are used to describe and understand the present disclosure, rather than to limit the present disclosure. In the drawings, units with similar structures are indicated by the same reference numerals. In the drawings, thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thickness of each component shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto.
Referring to
In the present embodiment, the active layer 40 of the thin film transistor 100 includes the first oxide layer 41 and the second oxide layer 42. The first oxide layer 41 is the crystalline oxide layer and the second oxide layer 42 is the lanthanide oxide layer. After crystallization of the crystalline oxide layer, the defect states are reduced, and fewer photogenerated carriers are generated when exposed to light, thereby reducing a concentration of free carriers of the channel layer of the active layer 40. When the lanthanide oxide layer is illuminated, a shallow recombination center generated by a lanthanide element has a function of capturing a photogenerated carrier, thereby avoiding a device threshold voltage offset and an off-state current rising when the device is illuminated, improving the stability of the thin film transistor 100, and solving the problem of poor stability of the conventional oxide semiconductor thin film transistor.
Specifically, referring to
The gate 10 may be formed as a plurality of layers or a single layer including a low resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material having high corrosion resistance.
The gate insulating layer 51 covers the gate 10 and the substrate, and the gate insulating layer 51 may include an inorganic insulating material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and/or zinc oxide (ZnO2). The gate insulating layer 51 may include a single layer or a plurality of layers including one or more of the inorganic insulating materials mentioned above.
The active layer 40 is provided on the gate insulating layer 51 and corresponds to the gate 10. The active layer 40 includes the first oxide layer 41 and the second oxide layer 42 that are stacked, the first oxide layer 41 is the crystalline oxide layer, and the second oxide layer 42 is the lanthanide oxide layer. Alternatively, material of the first oxide layer 41 includes one of semiconductor materials such as indium gallium oxide (IGO), indium gallium tin oxide (IGTO), indium oxide (InO), indium zinc oxide (IZO), or indium tin oxide (ITO). The first oxide layer 41 may be formed as the crystalline oxide layer by thermal annealing, laser crystallization, seed crystallization, or other crystallization methods.
The first oxide layer 41 is made of crystalline oxide, so that M-O bonding can be strengthened, the number of deep defect states (DOS) of the first oxide layer 41 can be reduced, fewer photogenerated carriers are generated when the first oxide layer 41 is exposed to light, the free carrier concentration of the channel layer of the active layer 40 can be reduced, and the photostability of the device may be improved. The crystalline oxide may also reduce the effect of hydrogen implantation during subsequent processes on the device to further improve the stability of the device.
The second oxide layer 42 is disposed at a side of the first oxide layer 41 away from the substrate, the second oxide layer 42 is disposed corresponding to the first oxide layer, and the outer boundary of the second oxide layer 42 is aligned with the outer boundary of the first oxide layer 41. The thickness of the second oxide layer 42 is greater than 150 angstroms, and the thickness of the first oxide layer 41 may be greater than or equal to the thickness of the second oxide layer 42.
Alternatively, the material of the second oxide layer 42 includes one of semiconductor materials such as indium zinc oxide IZO, indium oxide (InO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or the like. The second oxide layer 42 is a lanthanide oxide layer formed by doping a lanthanide in the semiconductor material mentioned above. A proportion of the number of atoms of the lanthanide in the lanthanide oxide layer ranges from 0.05% to 3%, such as 0.05%, 0.1%, 0.6%, 0.8%, 1%, 1.5%, 1.8%, 2%, 2.6%, etc. When the proportion of the number of atoms of the lanthanide is too low, the function of capturing photogenerated carriers may not be realized. When the proportion of the number of atoms of the lanthanide is too high, the semiconductor characteristics of the second oxide layer 42 are affected. The lanthanide includes one of Pr, Dy, Yb, and the like.
The second oxide layer 42 is made of the lanthanide oxide. When the second oxide layer 42 is exposed to light, the shallow recombination center generated by the lanthanide element has a function of capturing the photogenerated carrier, thereby avoiding a device threshold voltage offset and an off-state current rising when the device is exposed to light, and improving the stability of the thin film transistor 100. Moreover, the use of lanthanide oxides can also improve the resistance to cupric acid etching and hydrogen diffusion of the second oxide layer 42, and further improve the stability of the device.
In the present embodiment, the crystalline oxide and the lanthanide oxide are used as the active layer 40, so that in addition to higher mobility, the photostability of the device is better than that of a general oxide device (e.g., IGZO), the defect states are reduced after the crystallization of the crystalline oxide layer, and the free carrier concentration of the channel layer of the active layer 40 is reduced due to fewer photogenerated carriers when the crystalline oxide layer is exposed to light. When the lanthanide oxide layer is illuminated, the shallow recombination center generated by the lanthanide element has the function of capturing the photogenerated carrier, thereby avoiding the device threshold voltage offset and the off-state current rising when the device is illuminated, improving the stability of the thin film transistor 100, and solving the problem of poor stability of the conventional oxide semiconductor thin film transistor 100.
Further, since the gate 10 is located at the side of the first oxide layer 41 away from the second oxide layer 42, an atomic proportion of the indium element in the first oxide layer 41 may be made larger than an atomic proportion of the indium element in the second oxide layer 42 to improve the mobility of the first oxide layer 41. Alternatively, the number of atoms of the indium element in the first oxide layer 41 accounts for 50% to 100% of the number of atoms of the metal element in the first oxide layer 41, such as 50%, 60%, 70%, 80%, 90%, 100%, etc., and the proportion of the number of atoms of the oxygen element in the first oxide layer 41 is in the range of more than 50%, such as 50%, 60%, 70%, etc. The number of atoms of the indium element in the second oxide layer 42 accounts for 50% to 100% of the number of atoms of the metal element in the second oxide layer 42, such as 50%, 60%, 70%, 80%, 90%, 100%, and the like, and the proportion of the number of atoms of the oxygen element in the second oxide layer 42 is in the range of more than 50%, such as 50%, 60%, 70%, etc. The proportion of the number of atoms of the element refers to the proportion of the number of atoms, for example, the proportion of the number of atoms of the indium element in the number of atoms of the metal element in the first oxide layer 41 is in the range of 50% to 100%, which refers to the percentage of the number of atoms of the indium element to the number of atoms of all metal elements in the first oxide layer 41.
In an embodiment, the atomic proportion of the indium element in the first oxide layer 41 gradually decreases in the direction away from the gate 10, and the atomic proportion of the oxygen element in the first oxide layer 41 gradually increases in the direction away from the gate 10. In this way, the portion of the first oxide layer 41 that is close to the gate 10 may have a higher atomic proportion of the indium element, so that the mobility of the first oxide layer 41 may be improved. At the same time, the stability of the thin film transistor 100 may be further improved, for example, the voltage stability and the light stability at the channel of the active layer may be improved, and the threshold voltage drift may be avoided. The atomic proportion refers to the proportion of the number of atoms.
Further, the atomic proportion of the indium element in the second oxide layer 42 also gradually decreases in a direction away from the gate 10, and the atomic proportion of the oxygen element in the second oxide layer 42 also gradually increases in the direction away from the gate 10. In this way, the portion of the second oxide layer 42 away from the gate 10 has a lower atomic proportion of the indium element, so that lanthanides with a higher proportion of the number of atoms may be provided, and thus the barrier performance of the second oxide layer 42 may be improved, for example, an etching liquid damage resistance performance.
With continued reference to
Alternatively, each of the source 20 and the drain 30 may include a conductive material including, for example, Mo, Al, Cu, and/or Ti, and may be a single layer or multiple layers including one or more of the conductive materials mentioned above.
A passivation layer 52 covers the source 20, the drain 30, the second oxide layer 42, and the gate insulating layer 51 to insulate moisture and oxygen and protect the source 20, the drain 30, and the active layer 40. The passivation layer 52 may include an inorganic insulating material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and/or zinc oxide (ZnO2). The passivation layer 52 may be a single layer or multiple layers including one or more of the inorganic insulating materials mentioned above.
In an embodiment, referring to
Specifically, the thin film transistor 100 further includes a light shielding layer 60, and the light shielding layer 60 is disposed on the substrate and corresponds to the active layer 40 to shield the active layer 40 from light. Material of the light shielding layer 60 may include a light shielding metal, such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu). The light shielding layer 60 may be a single layer or multiple layers including one or more of the light shielding metal materials mentioned above.
A buffer layer 53 covers the light shielding layer 60 and the substrate. The buffer layer 53 may prevent undesirable impurities or contaminants (e.g., moisture, oxygen, etc.) from diffusing from the substrate into devices that may be damaged by these impurities or contaminants, while also providing a flat top surface. In order to improve the function of preventing moisture and other impurities from permeating through the substrate, the buffer layer 53 may be a silicon oxide film, a silicon nitride film, or multiple layers including the silicon oxide film and the silicon nitride film. Further, the buffer layer 53 may be formed of a plurality of layers having different refractive indices, so as to scatter external light incident from the outside.
The active layer 40 is disposed on the buffer layer 53, the gate insulating layer 51 is disposed on the active layer 40, the gate 10 is disposed on the gate insulating layer 51, and the gate 10 and the gate insulating layer 51 are each disposed corresponding to the active layer 40.
An interlayer insulating layer 54 covers the gate 10, the active layer 40, and the buffer layer 53, and the interlayer insulating layer 54 may include an inorganic insulating material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and/or zinc oxide (ZnO2). The interlayer insulating layer 54 may be a single layer or multiple layers including one or more of the inorganic insulating materials mentioned above.
The source 20 and the drain 30 are disposed on the interlayer insulating layer 54 and electrically connected to the active layer 40 through via holes in the interlayer insulating layer 54. The passivation layer 52 covers the source 20, the drain 30, and the interlayer insulating layer 54. For other description, referring to the above-mentioned embodiments, and details are not described herein.
In an embodiment, referring to
Specifically, referring to
By forming the first auxiliary layer 70 having a thinner thickness before forming the active layer 40, the first auxiliary layer 70 may seize oxygen elements in the active layer 40, so that the first oxide layer 41 is easier to crystallize. Further, the metal element in the first auxiliary layer 70 forms a metal oxide after seizing the oxygen element in the active layer 40, and the first auxiliary layer 70 is in contact with the gate insulating layer 51, and the gate insulating layer 51 supplements oxygen element to the first auxiliary layer 70, so that the metal oxide formed by the first auxiliary layer 70 tends to have insulator characteristic, and the first auxiliary layer 70 does not affect the semiconductor characteristic of the first oxide layer 41 while facilitating crystallization of the first oxide layer 41. For other description, referring to the above-mentioned embodiments, and details are not described herein.
In an embodiment, referring to
In an embodiment, referring to
Specifically, referring to
By forming the second auxiliary layer 80 with a thinner thickness on the active layer 40, the second auxiliary layer 80 may seize the oxygen element in the active layer 40, so that the metal element in the second auxiliary layer 80 forms a metal oxide after seizing the oxygen element in the active layer 40. For example, when the second auxiliary layer 80 include Ti or Mo, the corresponding TiO2, MoO that tend to have conductor characteristics are formed to improve the contact impedance. At the same time, a portion of the second auxiliary layer 80, which is not covered by the source 20 and the drain 30, is also in contact with the passivation layer 52, which supplements oxygen element to the second auxiliary layer 80, so that the metal oxide formed by the second auxiliary layer 80 tends to have the insulator characteristic, and thus the second auxiliary layer 80 forms an insulating portion 81 and conductor portions 82 on opposite sides of the insulating portion 81. The conductor portions 82 are provided corresponding to the source 20 and the drain 30, the source 20 and the drain 30 are electrically connected to the active layer 40 through the corresponding conductor portions 82, respectively. The insulating portion 81 may protect the active layer 40 from contact with the etching liquid. For other description, referring to the above-mentioned embodiments, and details are not described herein.
In an embodiment, referring to
In an embodiment, an embodiment of the present disclosure further provides an array substrate, and the array substrate includes the thin film transistor 100 according to one of the foregoing embodiments.
In an embodiment, an embodiment of the present disclosure further provides a display panel, the display panel includes first and second substrates arranged opposite to each other, and one of the first and second substrates includes an array substrate according to one of the foregoing embodiments. The display panel includes a display panel such as a liquid crystal display panel.
It can be seen from the above embodiments that: the present disclosure provides a thin film transistor, an array substrate, and a display panel. The active layer of the thin film transistor includes a first oxide layer and a second oxide layer. The first oxide layer is the crystalline oxide layer, and the second oxide layer is the lanthanide oxide layer. When the crystalline oxide layer and the lanthanide oxide layer are used as active layers, in addition to having a higher mobility, the photostability of the device is better than that of a general oxide device (such as IGZO). After the crystalline oxide layer is crystallized, the defect states are reduced, and there is fewer photogenerated carriers when the crystalline oxide layer is exposed to light, thereby reducing a free carrier concentration of the channel layer of the active layer. When the lanthanide oxide layer is illuminated, the shallow recombination center generated by the lanthanide element has the function of capturing the photogenerated carrier, thereby avoiding a device threshold voltage offset and an off-state current rising when the device is illuminated, improving the stability of the thin film transistor, and solving the problem of poor stability of the conventional oxide semiconductor thin film transistor.
In the above-mentioned embodiments, the description of each embodiment has its own emphasis, and parts not described in detail in a certain embodiment may be referred to the related description of other embodiments.
The embodiments of the present disclosure are described in detail above, the principles and embodiments of the present disclosure are described herein with reference to specific embodiments. The description of the above embodiments is merely intended to assist in understanding the technical solution of the present disclosure and the core concepts thereof. It may be appreciated by those ordinary skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments, or equivalent replacements may be made to some of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310831160.X | Jul 2023 | CN | national |
