Thin film transistor array substrate and method fabricating the same

Information

  • Patent Application
  • 20080001152
  • Publication Number
    20080001152
  • Date Filed
    December 27, 2006
    18 years ago
  • Date Published
    January 03, 2008
    16 years ago
Abstract
A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs. In particular, the method comprises a thin film transistor (TFT) array comprising: forming a gate line and a gate electrode on a substrate; forming a semiconductor layer to be insulated from the gate electrode, and overlapped with a portion of the gate electrode; forming a source electrode and a drain electrode on both sides of the semiconductor layer, respectively, while forming a data line intersecting with the gate line; forming a passivation layer over an entire upper surface of the substrate including the source electrode and the drain electrode using a sol compound of a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y; light-exposing and developing the passivation layer to form a contact hole through which the drain electrode is exposed; and forming a pixel electrode to be in contact with the drain electrode through the contact hole.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:



FIGS. 1A to 1C are sectional views illustrating a method for fabricating a conventional TFT array substrate.



FIGS. 2A to 2C are sectional views illustrating a method for fabricating a TFT array substrate according to the present invention.



FIG. 3 is a diagram illustrating a material for a passivation layer



FIG. 4 is a diagram illustrating a material for a passivation layer material.





DETAILED DESCRIPTION


FIGS. 2A to 2C are sectional views illustrating a method for fabricating a TFT array substrate. FIG. 3 is an example diagram illustrating a material for a passivation layer. FIG. 4 is another example diagram illustrating a material for a passivation layer.


Typically, the TFT array substrate includes a gate line and a gate electrode branched from the gate line, a semiconductor layer insulated from the gate electrode by a gate insulating film and overlapped with a portion of the gate electrode, a data line intersecting with the gate line, a source electrode and a drain electrode branched from the data line respectively formed on both sides of the semiconductor layer, and a pixel electrode in contact with the drain electrode through a passivation layer. As shown in FIG. 3, a sol compound of a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y is used as a material for the passivation layer.


The photosensitive groups X and Y may be at least one selected from the group consisting of a double bond (e.g.,







), a triple bond (e.g.,







), an acrylate group (e.g.,







), an epoxy group (e.g.,







) and an oxetane group (e.g.,







).


The metal of the metal alkoxide may be at least one selected from the group consisting of titanium (Ti), zirconium (Zr), yttrium (Y), aluminium (Al), hafnium (Hf), calcium (Ca) and magnesium (Mg). The dielectric constant, transmittance or thermal stability of the sol compound may be changed depending on the content ratio of the silicon alkoxide to the metal alkoxide.


Alternatively, another material for the passivation layer is illustrated in FIG. 4. As shown in FIG. 4, a material having a structure in which nanoparticles 201 are dispersed in a polymer matrix 200 having a photosensitive group X and a photosensitive group Y may be used for the passivation layer. The nanoparticles 201 may be O2, AlO3, or MgO nanoparticles. The polymer matrix may be at least one selected from the group consisting of inorganic polymers such as polysiloxanes and polysilanes; organic polymers such as polyacrylates, polyimides and polyvinyls; and inorganic/organic hybrid polymers. The dielectric constant, transmittance or thermal stability of the passivation layer may be changed depending on the amount and kind of the nanoparticles used.


The passivation layer material may further contain a radical photo-initiator selected from benzophenones and acetophenones, or a cationic photo-initiator selected from aryldiazoniums, diaryliodiniums and triarylsulfoniums. When the passivation layer made of such a material is subjected to light exposure, the photosensitive groups X and Y are photo-crosslinked each other. The resulting photo-crosslinked portion is removed during a subsequent developing process.


As shown in FIG. 2a, a metal having a low resistivity such as copper (Cu), aluminum (Al), aluminum alloy such as aluminum-neodymium (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) or molybdenum-tungsten (MoW) is deposited on a substrate 111 by sputtering at high temperature. The deposited layer is subjected to a patterning process to form a gate line (not shown), a gate electrode 112a diverged from the gate line, and a storage electrode 132 arranged to be parallel to the gate line.


Then, an inorganic material such as a silicon nitride (SiNx) or a silicon oxide (SiOx) is deposited over the entire upper surface of the substrate 111 including the gate electrode 112a by plasma enhanced chemical vapor deposition (PECVD) to form a gate insulating film 113.


Subsequently, amorphous silicon (a-Si) and amorphous silicon doped with an n-type impurity (n+a-Si) are deposited on the gate insulating film 113. The deposited layers are patterned by photolithography to form a semiconductor layer 114 and an ohmic contact layer (not shown).


A metal having a low resistivity such as copper (Cu), aluminum (Al), aluminum-neodymium (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) or molybdenum-tungsten (MoW) is deposited over the entire upper surface of the resulting structure including the semiconductor layer 114. The deposited layer is patterned by photolithography to form a source electrode 115a and a drain electrode 115b on both sides of the semiconductor layer 114, respectively. A date line 115 is formed to be integrally connected to the source electrode 115a.


The data line intersects with the gate line such that a unit pixel is defined at an intersection of the data line and gate line. The gate electrode 112a, the gate insulating film 113, the semiconductor layer 114, the ohmic contact layer, the source 115a and drain electrode 115b constitute a thin film transistor (TFT), which is located at the intersection of the gate line and the data line. The TFT may be a top-gate type TFT whose gate electrode is located on source/drain electrodes, or an organic TFT.


Subsequently, a passivation layer 116 is formed over the entire upper surface of the resulting structure including the TFT. As described above, the passivation layer 116 may be made of a material having a chemical network structure due to a bonding between a metal alkoxide and a silicon alkoxide, or a material having a structure in which nanoparticles are dispersed in a polymer matrix. The passivation layer 116 made of such a material has not only a film passivation function, but also a photoresist (PR) function.


The formation of the passivation layer 116 using the material having a chemical network structure due to a bonding between a metal alkoxide and a silicon alkoxide will be explained in more detail. In this case, a sol compound of a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y is coated over the entire upper surface of the structure including the source electrode 115a and drain electrode 115b by using a printing or coating method. Soft-baking is performed at a temperature high enough to evaporate a solvent present in the sol compound, to form a passivation layer 116.


As shown in FIG. 3, the sol compound is prepared by adding H2O or alcohol to a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y. In this case, the metal alkoxide and the silicon alkoxide bond together to form a sol compound having a chemical network structure. As a result, the passivation layer 116 can ensure a superior thermal stability. The H2O or alcohol acts as not only a solvent but also a catalyst.


The photosensitive groups X and Y may be at least one selected from the group consisting of a double bond (e.g.,







), a triple bond (e.g.,







), an acrylate group (e.g.,







), an epoxy group (e.g.,







) and an oxetane group (e.g.,







).


The metal of the metal alkoxide may be at least one selected from the group consisting of titanium (Ti), zirconium (Zr), yttrium (Y), aluminium (Al), hafnium (Hf), calcium (Ca) and magnesium (Mg). R of the metal alkoxide and silicon alkoxide may be alkyl group (e.g., CHC3—, C2H5—, C3H7—, . . . , CnH2n+1) or phenyl group.


The dielectric constant, transmittance or thermal stability of the sol compound may be changed depending on the content ratio of the silicon alkoxide to the metal alkoxide. It is preferred that the passivation layer be made of a material having a low dielectric constant for the formation of a structure having a high aperture ratio. Thus, such a low dielectric constant may be achieved by appropriately adjusting the content ratio of the silicon alkoxide to the metal alkoxide.


Next, the formation of a passivation layer using a material having a structure in which nanoparticles are dispersed in a polymer matrix will be explained in more detail. The film material may be formed by using a printing or coating method. Soft-baking is performed at a temperature high enough for to evaporate a solvent present in the sol compound, to form a passivation layer 116.


The photosensitive groups X and Y may be at least one selected from the group consisting of a double bond (e.g.,







), a triple bond (e.g.,







), an acrylate group (e.g.,







), an epoxy group (e.g.,







) and an oxetane group (e.g.,







.


The dielectric constant, transmittance or thermal stability of the passivation layer may be changed depending on the amount or kind of the nanoparticles dispersed in the polymer matrix. The nanoparticles 201 may be O2, AlO3, or MgO nanoparticles.


After the completion of the soft-baking, an exposure mask 120 with a predetermined pattern is coated on the soft-baked passivation layer. The coated passivation layer is exposed to ultraviolet (UV) rays or x-rays. At this time, the photosensitive groups X and Y are photo-crosslinked in accordance with the light exposure. The material for the passivation layer is directly exposed to light. The passivation layer material further contains a radical photo-initiator selected from benzophenones and acetophenones, or a cationic photo-initiator selected from aryldiazoniums, diaryliodiniums and triarylsulfoniums.


Then, the passivation layer is developed using an alkaline developing solution such as KOH or NaOH. As a result, the exposed and then photo-crosslinked part of the passivation layer is removed, as it is dissolved in the developing solution. In this case, the unexposed part of the passivation layer still remains. The developing process is achieved by using a dipping, puddling or shower spraying method.


As shown in FIG. 2B, the exposed part is removed to form a contact hole 120 through which a drain electrode 115b is exposed. After the completion of the contact hole 120, a hard-baking is carried out at a higher temperature than that of the soft-baking.


The use of direct exposing and developing processes for the formation of the contact hole on the passivation layer eliminates the need to form an additional photoresist, and thus, avoids the necessity for various processes such as photoresist coating, soft-baking, light exposure, developing, hard-baking, and stripping.


As shown in FIG. 2C, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited over the entire upper surface of the passivation layer 116 including the contact hole 120, and is then subjected to patterning to form a pixel electrode 117 to be electrically in contact with the drain electrode 115b. The pixel electrode 17 is formed-to be overlapped with the storage electrode 132 to form a storage capacitor.


Although not shown, the TFT array substrate fabricated in accordance with the procedure is joined to an opposite substrate, such that they face each other. A liquid crystal layer is sealed in a space between the TFT array substrate and the opposite substrate. The opposite substrate includes black matrix layers for preventing leakage of light, and color filter layers formed between the adjacent black matrix layers while having color resists R, G, and B arranged in a certain order. The opposite substrate also includes an over coat layer formed on each color filter layer to protect the color filter layer and to level the surface of the color filter layer, and a common electrode formed on the over coat layer to generate an electric field together with the associated pixel electrode of the TFT array substrate.


As apparent from the above description, a TFT array substrate and a method for fabricating the TFT array substrate have the following advantages.


First, since the passivation layer has not only a film passivation function, but also a photoresist function, it is unnecessary to form an additional photoresist for patterning the passivation layer. Accordingly, there is no necessity for various processes such as photoresist coating, soft-baking, light exposure, developing, hard-baking, and stripping, thereby simplifying the fabrication process and ensuring reduced preparation and materials costs.


Second, each of photosensitivity groups X and Y constituting the passivation layer has reactivity, and thus, induces a crosslinking in the molecule. As a result, the passivation layer material ensures an enhancement in thermal stability.


Third, the insulativity, coatability, heat resistance, hardness and transmittance of the organic/inorganic materials can be readily controlled in accordance with the content ratio of silicon alkoxide to metal alkoxide. Thus, the passivation layer made of the materials is suitable for use in a liquid crystal display (LCD) device.


Fourth, the passivation layer can be formed using a printing or coating method. Accordingly, the fabrication process and the management of equipment used in the process can be simplified, as compared to the case using PECVD.


It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims
  • 1. A thin film transistor (TFT) array comprising: a gate line and a gate electrode overlying a substrate;a semiconductor layer insulated from the gate electrode and overlapped with a portion of the gate electrode;a source electrode and a drain electrode overlying both sides of the semiconductor layer, respectively, and a data line intersecting with the gate line;a passivation layer overlying an entire upper surface of the substrate including the source electrode and the drain electrode, the passivation layer being made of a sol compound having a photosensitive group; anda pixel electrode in contact with the drain electrode.
  • 2. The TFT array according to claim 1, wherein the sol compound comprises a metal alkoxide having a photosensitive group and a silicon alkoxide having a photosensitive group.
  • 3. The TFT array according to claim 2, wherein the metal alkoxide is selected from at least the group consisting of Ti, Zr, Y, Al, Hf, Ca and Mg.
  • 4. The TFT array according to claim 1, wherein the sol compound includes a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y, and wherein each of the photosensitive groups X and Y is selected from at least one the group consisting of a double bond group, a triple bond group, an acrylate group, an epoxy group and an oxetane group.
  • 5. The TFT array according to claim 4, wherein the photosensitive groups X and Y of the sol compound are photo-crosslinked under a light-exposing process.
  • 6. The TFT array according to claim 5, wherein the photosensitive groups X and Y of the photo-crosslinked e sol compound are removed.
  • 7. The TFT array according to claim 2, wherein at least one of a dielectric constant, a transmittance and a thermal stability are changed according to a content ratio of the metal alkoxide and the silicon alkoxide.
  • 8. The TFT array according to claim 1, wherein the sol compound further contains a radical photo-initiator selected from the group consisting of benzophenones and acetophenones, or a cationic photo-initiator selected from the group consisting of aryldiazoniums, diaryliodiniums and triarylsulfoniums.
  • 9. A thin film transistor (TFT) array comprising: a gate line and a gate electrode overlying a substrate;a semiconductor layer insulated from the gate electrode and overlapped with a portion of the gate electrode;a source electrode and a drain electrode respectively overlying both sides of the semiconductor layer, and a data line intersecting with the gate line;a passivation layer in which nanoparticles are dispersed in a polymer matrix having a photosensitive group; anda pixel electrode in contact with the drain electrode.
  • 10. The TFT array according to claim 9, wherein the polymer matrix includes photosensitive groups X and Y, and wherein each of the photosensitive groups X and Y is selected from at least one the group consisting of a double bond group, a triple bond group, an acrylate group, an epoxy group and an oxetane group.
  • 11. The TFT array according to claim 9, wherein the nanoparticle is selected from the group consisting of O2, AlO3, and MgO.
  • 12. The TFT array according to claim 9, wherein the polymer matrix is selected from the group consisting of inorganic polymers including polysiloxanes and polysilanes; organic polymers including polyacrylates, polyimides and polyvinyls; and inorganic/organic hybrid polymers.
  • 13. The TFT array according to claim 9, wherein the photosensitive groups X and Y of the passivation layer are photo-crosslinked under a light-exposing process.
  • 14. The TFT array according to claim 13, wherein the photosensitive groups X and Y of the photo-crosslinked passivation layer are removed.
  • 15. The TFT array according to claim 9, wherein at least one of a dielectric constant, a transmittance and a thermal stability of the passivation layer is changed depending on the nanoparticles.
  • 16. The TFT array according to claim 9, wherein the polymer matrix further comprises a radical photo-initiator selected from the group consisting of benzophenones and acetophenones, or a cationic photo-initiator selected from the group consisting of aryldiazoniums, diaryliodiniums and triarylsulfoniums.
  • 17. A method for fabricating a thin film transistor (TFT) array, the method comprising: forming a gate line and a gate electrode overlying a substrate;forming a semiconductor layer to be insulated from the gate electrode, and to be overlapped with a portion of the gate electrode;forming a source electrode and a drain electrode overlying both sides of the semiconductor layer, respectively, while forming a data line intersecting with the gate line;forming a passivation layer overlying an entire upper surface of the substrate including the source electrode and the drain electrode using a sol compound having a photosensitive group;forming a contact hole, with a photolithography process, in the passivation layer, through which the drain electrode is exposed; andforming a pixel electrode to be in contact with the drain electrode through the contact hole.
  • 18. The method according to claim 17, wherein the sol compound includes a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y, and wherein each of the photosensitive groups X and Y is selected from at least one of the group consisting of a double bond group, a triple bond group, an acrylate group, an epoxy group and an oxetane group.
  • 19. The method according to claim 18, wherein the metal of the metal alkoxide is at least one selected from the group consisting of Ti, Zr, Y, Al, Hf, Ca and Mg.
  • 20. The method according to claim 18, wherein the photosensitive groups X and Y of the sol compound are photo-crosslinked under a light-exposing process, and a photo-crosslinked portion of the sol compound is removed from the passivation layer under a developing process.
  • 21. The method according to claim 17, wherein developing the passivation layer comprises using an alkaline developing solution.
  • 22. The method according to claim 18, wherein at least one of a dielectric constant, a transmittance and a thermal stability of the sol compound is changed based on a content ratio of the silicon alkoxide to the metal alkoxide.
  • 23. The method according to claim 17, wherein forming the passivation layer comprises using a printing or coating method.
  • 24. The method array according to claim 17, wherein the sol compound further contains a radical photo-initiator selected from the group consisting of benzophenones and acetophenones, or a cationic photo-initiator selected from the group consisting of aryldiazoniums, diaryliodiniums and triarylsulfoniums.
  • 25. A method for fabricating a thin film transistor (TFT) array, the method comprising: forming a gate line and a gate electrode overlying a substrate;forming a semiconductor layer to be insulated from the gate electrode, and overlapped with a portion of the gate electrode;forming a source electrode and a drain electrode overlying both sides of the semiconductor layer, while forming a data line intersecting with the gate line;forming a passivation layer overlying an entire upper surface of the substrate including the source electrode and the drain electrode using a material in which nanoparticles are dispersed in a polymer matrix having a photosensitive group;forming a contact hole, with a photolithography process, in the passivation layer, through which the drain electrode is exposed; andforming a pixel electrode to be in contact with the drain electrode through the contact hole.
  • 26. The method according to claim 25, wherein the polymer matrix includes photosensitive groups X and Y, and wherein each of photosensitive groups X and Y is at least one selected from the group consisting of a double bond group, a triple bond group, an acrylate group, an epoxy group and an oxetane group.
  • 27. The method according to claim 25, wherein the nanoparticle is selected from the group consisting of O2, AlO3, and MgO.
  • 28. The method according to claim 25, wherein the polymer matrix is selected from the group consisting of inorganic polymers including polysiloxanes and polysilanes; organic polymers including polyacrylates, polyimides and polyvinyls; and inorganic/organic hybrid polymers.
  • 29. The method according to claim 25, wherein the photosensitive groups X and Y are photo-crosslinked under a light-exposing process, and a photo-crosslinked portion is removed from the passivation layer under a developing process.
  • 30. The method according to claim 25, wherein developing the passivation layer comprises using an alkaline developing solution.
  • 31. The method according to claim 25, wherein at least one of a dielectric constant, a transmittance and a thermal stability of the nanoparticles is changed based on a content ratio of the silicon alkoxide to the metal alkoxide.
  • 32. The method according to claim 25, wherein forming the passivation layer comprises using a printing or coating method.
  • 33. The method according to claim 25, wherein the polymer matrix further comprises a radical photo-initiator selected from the group consisting of benzophenones and acetophenones, or a cationic photo-initiator selected from the group consisting of aryldiazoniums, diaryliodiniums and triarylsulfoniums.
Priority Claims (1)
Number Date Country Kind
P2006-061430 Jun 2006 KR national