THIN FILM TRANSISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Abstract

A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are sectional views showing a manufacturing process of a thin film transistor device and a method of manufacturing the same according to a first embodiment of the present invention;

FIGS. 2A to 2C are sectional views showing a manufacturing process of a thin film transistor device and a method of manufacturing the same according to a second embodiment of the present invention; and

FIGS. 3A to 3C are sectional views showing a manufacturing process of a thin film transistor device and a method of manufacturing the same according to a third embodiment of the present invention.

Claims

1. A thin film transistor device, comprising: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate;an interlayer insulating layer covering the thin film transistor;a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer;a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; anda second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.

2. The thin film transistor device according to claim 1, wherein the first upper insulating layer includes at least one of an organic Spin On Dielectrics (SOD) film, an organic Spin On Grass (SOG) film, an inorganic SOD film, an inorganic SOG film, and a high-heat-resistance organic polymer film resistant to a temperature of about 400° C. or higher.

3. The thin film transistor device according to claim 1, wherein surface roughness of the first upper insulating layer is 50 nm or less in terms of a RMS value in a 100 μm2 area.

4. The thin film transistor device according to claim 1, wherein the second upper insulating layer includes a silicon nitride film layer or a silicon oxynitride film layer.

5. An active matrix type display device comprising the thin film transistor device according to claim 1.

6. A method of manufacturing a thin film transistor device, comprising: forming the thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode on an insulating substrate;forming an interlayer insulating layer on the thin film transistor;forming a contact hole in the interlayer insulating layer and forming a line connected with the source region, the drain region, and the gate electrode through the contact hole;forming a first upper insulating layer on the line and the interlayer insulating layer and executing planarization to smooth out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; andforming a second upper insulating layer on the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.

7. The method of manufacturing a thin film transistor device according to claim 6, further comprising: executing heat treatment after the forming of the second upper insulating layer.

8. The method of manufacturing a thin film transistor device according to claim 6, wherein the planarization of the first upper insulating layer includes a coating process.

9. The method of manufacturing a thin film transistor device according to claim 6, wherein the planarization of the first upper insulating layer includes a chemical mechanical polishing process.

10. A thin film transistor device, comprising: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate;a first interlayer insulating layer covering the thin film transistor and smoothing out irregularities of a surface of the thin film transistor; anda second interlayer insulating layer covering the first interlayer insulating layer,the second interlayer insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first interlayer insulating layer.

11. The thin film transistor device according to claim 10, wherein the first interlayer insulating layer includes at least one of an organic Spin On Dielectrics (SOD) film, an organic Spin On Grass (SOG) film, an inorganic SOD film, an inorganic SOG film, and a high-heat-resistance organic polymer film resistant to a temperature of about 400° C. or higher.

12. The thin film transistor device according to claim 10, wherein the second upper insulating layer includes a silicon nitride film layer or a silicon oxynitride film layer.

13. An active matrix type display device comprising a thin film transistor device according to claim 10.

14. A method of manufacturing a thin film transistor device, comprising: forming the thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode on an insulating substrate;forming a first interlayer insulating layer on the thin film transistor, and executing planarization to smooth out irregularities of a surface of the thin film transistor; andforming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first interlayer insulating layer.

15. The method of manufacturing a thin film transistor device according to claim 14, further comprising: executing heat treatment after the forming of the second interlayer insulating layer.

16. The method of manufacturing a thin film transistor device according to claim 14, wherein the planarization of the first interlayer insulating layer includes a coating process.