Patent Application
20230387137
The present invention relates to a thin film transistor containing a metal oxide semiconductor.
A thin film transistor containing a metal oxide semiconductor exemplified by InGaZnO (hereinafter referred to as IGZO) is used as an element for driving pixels of a display. A thin film transistor containing IGZO with a composition ratio of In and Ga of 1:1 has a mobility of about 10 cm2/Vs. Although this mobility is higher than a mobility of a thin film transistor containing an amorphous silicon, it is lower than a mobility of a thin film transistor containing a low-temperature polysilicon.
In recent years, with the increase in the number of pixels and size of a display represented by 4K and 8K resolution display, IGZO capable of manufacturing a thin film transistor having higher mobility than an amorphous silicon and superior uniformity in a large area than a low-temperature polysilicon has been adopted. For example, in order to improve the mobility of IGZO, a thin film transistor containing IGZO in which In is richer than 1:1 in the composition ratio of In and Ga has been developed. In addition, a thin film transistor containing a metal oxide semiconductor that enables higher mobility than IGZO are being developed for next-generation displays. As one of them, a thin film transistor using InSnZnO (hereinafter referred to as ITZO) can achieve a mobility of about 50 cm2/Vs. Therefore, a thin film transistor used in a circuit requiring high mobility can be replaced with ITZO from a low-temperature polysilicon. On the other hand, an n-type thin film transistor containing ITZO has a disadvantage that a negative shift occurs in a threshold voltage due to NBTS (Negative Bias Temperature Stress). Hereinafter, the threshold voltage is sometimes simply referred to as a threshold. A threshold before stress application is shown as Vth, and the amount of the shift obtained by subtracting the threshold before stress application from a threshold after stress application is shown as ΔVth. In addition, the threshold is also used in the case of NBIS and PBTS. In the n-type thin film transistor, the negative shift of the threshold due to an application of a continuous negative-bias voltage means that the transistor that should be initially controlled to an off state by the application of the negative-bias voltage is turned on by itself over time, and thus the amount of the negative shift needs to be sufficiently reduced.
For example, Non-Patent Literature 1 (W. -H, Tseng et. al., Solid-State Electronics 103 (2015), 173-177) discloses that, as a way to solve this problem, an N2O plasma treatment on a backchannel side of ITZO is performed at appropriate times for defects caused by C═O and C—O coupling or the like that deteriorate properties of the thin film transistor.
According to FIG. 6 of Non-Patent Literature 1, it can be understood that, in a ITZO thin film transistor, a negative shift of a threshold due to the NBTS decreases as a duration of the N2O plasma treatment increases, but the negative shift increases if the processing time exceeds an optimum value. That is, in order to reduce the negative shift of the threshold in accordance with the process described in Non-Patent Literature 1, it is considered that it is necessary to grasp a surface condition of a backchannel of ITZO and precisely control the duration of the N2O plasma treatment in accordance with the surface condition. Even when passivation layers are formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method after the N2O plasma treatment, it becomes more difficult to control the duration due to exposure to the N2O plasma. As a result, a requirement of such control can also cause manufacturing variations. Therefore, it is desired to reduce the negative shift of the threshold by a method different from the N2O plasma treatment.
A thin film transistor according to an embodiment is a thin film transistor formed on a substrate, the thin film transistor includes a channel formed by at least part of a metal oxide semiconductor layer containing Indium (In), a gate electrode, a gate insulating layer arranged between the channel and the gate electrode, and a source electrode and a drain electrode connected to the metal oxide semiconductor layer. The average concentration of carbon atoms in an area from a surface to a depth of 5 nm of the channel may be 1.5×1021 cm−3 or less. The maximum concentration of carbon atoms in the area from the surface to the depth 5 nm of the channel may be 19 at % or less. The electron affinity of a passivation layer having an insulating property and covering the channel may be smaller than the electron affinity of the metal oxide semiconductor layer.
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The following embodiments are examples, and the present invention should not be construed as being limited to these embodiments. In the drawings referred to in the present embodiment, the same or similar parts are denoted by the same reference sign or similar reference sign (only denoted by A, B, and the like after a numeral), and repetitive description thereof may be omitted. In the drawings, dimensional ratios may be different from actual ratios, or part of the configuration may be omitted from the drawings for clarity of explanation.
In describing a positional relationship of a second component with respect to a first component, expressions “above”/“over” and “below”/“under” are not limited to the case where the second component is in contact with the first component above or below, and includes cases where still other configurations are interposed unless otherwise specified.
In this example, a display device in an embodiment is an organic EL (Electro Luminescence) display using an OLED (Organic Light Emitting Diode). The organic EL display may enable color display by using a plurality of OLEDs that emit light of different colors, or may enable color display by using the OLED that emits white light and color filters. The display device may further have a function of a touch sensor. The touch sensor detects contacts of a finger, a stylus, or the like on the display surface by, for example, a self-capacitance method or a mutual capacitance method.
The display device includes a thin film transistor containing ITZO. According to a driving method of the display device, the thin film transistor spends much time controlled in an off state. Therefore, it is not desirable to use a thin film transistor in which a negative shift of a threshold due to NBTS is likely to occur. As described in detail below, according to the thin film transistor containing ITZO, it has been achieved that the negative shift of the threshold due to the NBTS is reduced by methods based on findings obtained by the inventors.
First, a configuration of the display device will be described, and a configuration of the thin film transistor included in the display device and a configuration for achieving the reduction of the negative shift of the threshold due to the NBTS will be described later.
[Configuration of Display Device]
In the display area D1, a plurality of scan signal lines GL, a plurality of data signal lines SL, and a plurality of pixels PX are arranged. For example, the plurality of pixels PX are arranged in a matrix. The scan signal line GL and the data signal line SL are arranged so as to intersect with each other. The pixels PX are arranged at a part where the scan signal line GL and the data signal line SL intersect with each other. In
The drive circuit GD is arranged adjacent to the display area D1 and is connected to the scan signal line GL. The driver IC chip CD is connected to the data signal line SL and the drive circuit GD. The driver IC chip CD controls a signal to be supplied to the data signal line SL based on an external control signal, and further controls the drive circuit GD to control a signal to be supplied to the scan signal line GL. In this example, the drive circuit GD includes a circuit such as a shift register using a thin film transistor 100 (see
The pixel PX includes a light emitting element that is an OLED, and a pixel circuit for controlling light emission by the light emitting element. The pixel circuit includes elements such as the thin film transistor 100 and a capacitor. In this embodiment, the pixel circuit included in one pixel PX has a plurality of thin film transistors 100. In this example, light emitted from the light emitting element travels in a direction opposite to the first substrate 1 on which the light emitting element is formed, and is visually recognized by a user through the second substrate 2. That is, a top emission type is applied to the display device 1000. A bottom emission type may be applied to the display device 1000.
The first supporting substrate 10 and the second substrate 2 are glass substrates. One or both of the first supporting substrate 10 and the second substrate 2 may be a flexible substrate such as an organic resin substrate.
The base insulating layer 110 is arranged on the first supporting substrate 10, and prevents intrusions of moisture and gas into the inside. The base insulating layer 110 includes, for example, an insulating film such as silicon oxide or silicon nitride. The base insulating layer 110 may include a structure in which multiple types of insulating films are stacked.
As described above, the thin film transistor 100 contains ITZO as a semiconductor layer and is arranged on the base insulating layer 110. In this example, the thin film transistor 100 is a thin film transistor of a BCE (Back Channel Etch) type. A detailed configuration of the thin film transistor 100 will be described later.
The interlayer insulating layer 200 covers the thin film transistor 100. The interlayer insulating layer 200 includes, for example, an inorganic insulating film such as silicon oxide or silicon nitride. The interlayer insulating layer 200 may include a structure in which multiple types of insulating films are stacked. In this example, a silicon oxide film of the interlayer insulating layer 200 is in contact with the thin film transistor 100. The interlayer insulating layer 200 may further include a planarization insulating film on the inorganic insulating film. The planarization insulating film may be an organic insulating film such as acrylic, polyimide, or epoxy resin. In the case where the interlayer insulating layer 200 includes a structure in which a plurality of insulating films are stacked, a conductive film used for wirings and the like may be arranged between the plurality of insulating films.
The pixel electrode 300 is connected to a drain electrode 172 (see
The bank layer 400 covers an end portion of the pixel electrode 300 and includes an opening portion that exposes part of the pixel electrode 300. The bank layer 400 includes, for example, an organic insulating film such as acrylic, polyimide, or epoxy resin.
The light emitting layer 500 is arranged so as to cover part of the pixel electrode 300 and the bank layer 400. The light emitting layer 500 has a structure in which multiple types of organic materials are stacked. The light emitting layer 500 emits light by a current being supplied. By changing at least one of the plurality of organic materials constituting the light emitting layer 500, emission colors can be made different from each other.
The counter electrode 600 covers the light emitting layer 500. The counter electrode 600 includes a conductive film that functions as an anode of the light emitting layer 500. The counter electrode 600 includes a stacked structure of one type of conductive film or multiple types of conductive films. As described above, depending on the configuration of the pixel circuit, the counter electrode 600 may function as a cathode of the light emitting layer 500. As described above, since the top emission type is applied to the display device 1000, the counter electrode 600 has light transmittance. The pixel electrode 300, the light emitting layer 500, and the counter electrode 600 form light emitting elements in each of the pixels PX.
The sealing layer 900 is an insulating layer that covers the entire display area D1 and prevents intrusions of moisture and gases into the light emitting layer 500. The sealing layer 900 includes, for example, a structure in which a silicon nitride film arranged on the counter electrode 600 and a planarization insulating film on the silicon nitride film are stacked, and has light transmittance. The planarization insulating film may be, for example, an organic insulating film such as acrylic, polyimide, or epoxy resin. The sealing layer 900 may be arranged so as to be sandwiched between the silicon nitride film and the second substrate 2 and function as a member for bonding the first substrate 1 and the second substrate 2.
[Method for Manufacturing Display Device]
Next, a method for manufacturing the display device 1000 will be described.
A gate electrode 120 is obtained by forming a film of a conductive material formed by the PVD method on the base insulating layer 110 in a desired pattern. The desired pattern is formed by, for example, an etching process or a lift-off process using a photoresist by photolithography. The gate electrode 120 may be formed in a patterned state by a printing method, an ink jet method, or the like. When the gate electrode 120 is formed, at least one of the scan signal line GL and the data signal line SL may be formed at the same time. The conductive material is, for example, a metal such as molybdenum, tantalum, tungsten, gold, copper, chromium, aluminum, or a metal compound containing at least one of these metals. The gate electrode 120 may include a structure in which multiple types of conductive materials are stacked. In this example, the gate electrode 120 includes a structure in which molybdenum and copper are stacked in this order from the first supporting substrate 10 side.
A gate insulating layer 130 is formed to cover the gate electrode 120 and the base insulating layer 110 by the CVD method or the PVD method. Although a thickness of the gate insulating layer 130 may vary, for example, 20 nm or more and 200 nm or less is preferable, and 50 nm or more and 150 nm or less is more preferable. A configuration after the gate insulating layer 130 is formed corresponds to
Subsequently, an ITZO film is formed on the gate insulating layer 130 by the CVD method or the PVD method. In this case, ITZO is formed by the sputtering method using gas containing argon and oxygen. In this example, the ITZO film is amorphous, but may contain microcrystals. Elements other than In, Sn, Zn and O may be contained. In an area from a surface to a depth of 5 nm of a channel CH (see
When photolithography is performed, an upper surface 150a of the semiconducting layers 150 contacts the photoresist PR. As will be described later, when the photoresist PR comes into contact with the semiconductor layer 150 which is the ITZO film, the carbon atoms “C” which are organic compounds contained in the photoresist PR are bound to the contact surface (upper surface 150a). Even if the upper surface 150a of the semiconductor layer 150 is exposed to an etchant (hereinafter referred to as a stripping solution) for removing the photoresist PR, the carbon atoms bound to the upper surface 150a are not removed.
The carbon atoms remain as “C—O” and “C═O” (hereinafter referred to as carbon residual components). It is said that ITZO has the surface on which “C—O” and “C═O” are easily adsorbed due to having SnOx (tin oxide). It is said that In2Ox (indium oxide) and ZnOx (zinc oxide) have the same tendency as SnOx (tin oxide), although their impacts are small. The carbon residual components introduce defects into ITZO. In ITZO, electrons are supplied by the carbon residual components to increase an electron density, and holes are trapped in the defects due to the NBTS, which are considered to cause the thresholds to shift to negative.
In the case where the semiconductor layer 150 is formed by the lift-off process, although the upper surface 150a of the semiconductor layer 150 is not contacted by the photoresist PR, there is a possibility that a carbon residual component may similarly be generated on the upper surface 150a due to an effect of organic compounds contained in the stripping solution and components of the dissolved photoresist PR by being exposed by the stripping solution when removing the photoresist PR for lift-off.
The source electrode 171 and the drain electrode 172 are formed by forming films of conductive materials formed on the semiconductor layer 150 and the gate insulating layer 130 in desired patterns by the PVD method. The desired patterns are formed by, for example, the etching process or the lift-off process using the photoresist by photolithography. When the source electrode 171 and the drain electrode 172 are formed, at least one of the scan signal line GL and the data signal line SL may be formed at the same time. The conductive material is, for example, a metal such as molybdenum, tantalum, tungsten, gold, copper, chromium, aluminum, or a metal compound containing at least one of these metals.
The source electrode 171 and the drain electrode 172 are preferably made of a conductive material having oxidation resistance. The source electrode 171 and the drain electrode 172 may include a structure in which multiple types of conductive materials are stacked. In this case, it is preferable that at least the conductive material exposed on the upper surface has oxidation resistance. In this example, the source electrode 171 and the drain electrode 172 include a structure in which molybdenum and copper are stacked in this order from the semiconductor layer 150 side.
A configuration after the source electrode 171 and the drain electrode 172 are formed by the etching process in which the photoresist PR is formed on the conductive material corresponds to
Depending on the etchant used to form the source electrode 171 and the drain electrode 172, the backchannel-side surface 150b may contain the carbon residual components. For example, in a PAN etchant including phosphoric acid, nitric acid, and acetic acid, acetic acid may cause the carbon residual components to be generated. At least the backchannel-side surface 150b contacts the photoresist PR in a state shown in
In the case where the source electrode 171 and the drain electrode 172 are formed by the lift-off process, the carbon residual components are generated on the backchannel-side surface 150b because the photoresist PR is formed on the backchannel-side surface 150b.
It has been found by the inventors that in order to reduce the negative shift of the thresholds due to the NBTS, it is essential to reduce carbon residual components on a surface of the channel CH. That is, it is preferable that a surface of the channel CH on the side of the gate electrode 120 (hereinafter, referred to as a gate-side surface 150g) and the surface on the opposite side (backchannel-side surface 150b) have less carbon residual components.
On the other hand, as described above, in the state where the surface of the channel CH is exposed, the carbon residual components may be increased by various manufacturing processes. It is meaningless to temporarily reduce the carbon residual components, and it is significant that the carbon residual components on the surface of the channel CH are reduced when the surface of the channel CH becomes unexposed, that is, in the state where the surface of the channel CH becomes covered with other layers. Further, after the surface of the channel CH becomes unexposed, it is difficult to desorb the carbon residual components from the surface of the channel CH.
Since a source surface 150s and a drain surface 150d are not parts that function as the channel CH, the carbon residual components may not be reduced. The source surface 150s corresponds to a part of the surface of the semiconductor layer 150 that is in contact with the source electrode 171. The drain surface 150d corresponds to a part of the surface of the semiconductor layer 150 that is in contact with the drain electrode 172.
In this example, as shown in
The oxygen-containing atmosphere may include the air, and may include atmosphere having an oxygen concentration higher than that of the air. The oxygen-containing atmosphere does not exclude atmosphere having an oxygen concentration lower than that of the air if oxygen is contained.
A condition of the UV ozone treatment or a condition of the heat treatment is set such that an average concentration of the carbon atoms in an area from the exposed part of the backchannel-side surface 150b to the depth of 5 nm is reduced to 1.5×1021 cm−3 or less as a result of the desorption of the carbon atoms. It is preferable that the average concentration of carbon atoms in the area from the exposed part of the backchannel-side surface 150b to the depth of 5 nm is reduced to 3.5×1020 cm−3 or less.
The condition of the UV ozone treatment or the condition of the heat treatment may be set such that, as a result of the desorption of the carbon atoms, a maximum concentration of the carbon atoms in the area from the exposed part of the backchannel-side surface 150b to the depth of 5 nm is reduced to 19 at % or less as measured by an Auger electron spectroscopy. The maximum concentration of carbon atoms in the area from the exposed portion of the backchannel-side surface 150b to the depth of 5 nm is preferably reduced to 8 at % or less. For example, the conditions of the UV treatment are, for example, UV light intensity, exposure time, oxygen concentration, substrate temperature, and the like. The conditions of the heat treatment are, for example, heating temperature, heating time, oxygen concentration, and the like.
Other than the exposed part of the backchannel-side surface 150b, that is, the source surface 150s is covered with the source electrode 171, and the drain surface 150d is covered with the drain electrode 172. Therefore, even if the source surface 150s and the drain surface 150d are subjected to the UV ozone treatment or the heat treatment, the carbon residual components are hardly desorbed, and the carbon atoms are more concentrated than the exposed parts of the backchannel-side surface 150b. However, since the source surface 150s and the drain surface 150d do not function as channels of the thin film transistor 100, the presence of carbon residual components has little effect.
For the gate-side surface 150g, there is no factor that causes carbon residual components. Even if the carbon residual components are present on the gate insulating layer 130 before the ITZO film is formed on the gate insulating layer 130, the carbon residual component is reduced by a process (sputtering containing oxygen) when the ITZO film is formed by the PVD method. As a result, the carbon atoms are desorbed and fall within the concentration range described above. In addition, although the gate insulating layer or the semiconductor layer is usually manufactured by a gas phase method, in the case where the gate insulating layer or the semiconductor layer is manufactured by a liquid phase method instead of the gas phase method, there is a factor that the carbon residual components are also generated in the gate-side surface 150g.
After the process of reducing the carbon residual component, an interlayer insulating layer 200 is formed to cover the thin film transistor 100. The thin film transistor 100, in particular a portion contacting the exposed portion of the backchannel-side surface 150b, is protected from carbon atoms by an inorganic insulating material containing a small carbon component so that no carbon residual components are generated again. That is, after the carbon atoms are desorbed from the surface of the channel CH, an insulating layer that protects the channel CH is formed prior to the formation of the layer containing carbon atoms on the surface of the channel CH.
In this example, the interlayer insulating layer 200 includes a structure in which the silicon oxide film, the silicon nitride film, and an organic resin film are stacked in this order from the thin film transistor 100 side. Films of inorganic insulating materials are formed by the CVD method or the PVD method. When forming a film of the inorganic insulating material, a film forming method in which the introduction of carbon atoms is necessary is not adopted. For example, forming aluminum oxide by an ALD (Atomic Layer Deposition) method is not preferable because carbon-containing trimethylaluminum (TMA) is used. However, this type of aluminum oxide can also be used as an inorganic insulating material that does not touch the surface of the channel CH. If it is possible to reduce the number of carbon residual components that eventually occur on the surface of the channel CH by setting the deposition temperature or the like, the inorganic insulating material may be used as the inorganic insulating material that contacts the surface of the channel CH by the ALD method. The organic resin film is formed by a solution coating method or a printing method. A contact hole communicating to the drain electrode 172 is formed in the interlayer insulating layer 200.
The pixel electrode 300 is formed on the interlayer insulating layer 200 and is connected to the drain electrode 172 via the contact hole. The pixel electrodes 300 are formed by, for example, the PVD method. The configuration after the pixel electrode 300 is formed corresponds to
According to the thin film transistor 100 described above, since the carbon atoms are desorbed from the channel CH surface by the treatment of reducing the carbon residual components adsorbed on the surface of the channel CH and the insulating layers covering the channel CH surface are formed prior to the material containing the carbon atoms contacting the channel CH surface, the negative shift of the thresholds due to the NBTS is reduced.
Next, we explain the experimental findings that the reduction of carbon residual components enabled us to reduce the negative shift of the thresholds due to the NBTS. As described above, the inventors have found that the negative shift of the thresholds in the NBTS can be reduced by reducing the carbon residual components on the channel CH surface. In order to verify this, a thin film transistor for threshold shift measurement was fabricated.
The gate electrode 125 is a conductive P-type silicon substrate. The gate insulating layer 135 is a thermal oxide film formed on the surface of the silicon substrate and has a thickness of 150 nm. The semiconducting layer 155 is ITZO and has a thickness of 20 nm. The composition ratio In (indium):Sn (tin):Zn (zinc) excluding O (oxygen) is 20:40:40 (at %). This composition ratio is based on the amount of the elements charged (nominal value) and corresponds to the composition ratio of a target in the case where the target is single. The composition ratio of the actually formed semiconductor layer 155 is shown as Auger electron spectroscopy measurement results described later. In the actual semiconductor layer 155 (also in the semiconductor layer 150 described above), a portion having 10 at % of Sn or more and a portion having 13 at % of Sn or more may be contained in an area from the surface to the depth of 5 nm of the channel CH. In the area from the surface to the depth of 5 nm of CH of channel, the atomic percent of Sn may include a portion greater than the atomic percent of Zn. In the case where Sn is highly concentrated, although the carbon residual components are likely to be generated, the carbon residual components can be reduced as described below, which is not a major issue. The length (channel length) of the channel CH of the thin film transistor is 30 μm, and the channel width is 60 μm. From the viewpoint of miniaturization, the channel length is preferably 100 μm or less, more preferably 30 μm or less, still more preferably 10 μm or less, and still more preferably 3 μm or less. Next, a method of manufacturing a thin film transistor for threshold shift measurement will be described.
As shown in
[Carbon Residual Components]
An ITZO film was formed on the substrate, a sample prior to forming the photoresist (hereinafter referred to as a Before PR sample) and a sample from which the photoresist was removed after forming the photoresist on the ITZO film (hereinafter referred to as a After PR sample) were prepared, and a TDS (Thermal Desorption Spectrometry) measurement and a HAX-PES (Hard X-ray Photoelectron Spectroscopy) measurement were performed.
[Effect of Heat Treatment on Carbon Residual Components]
An effect of the heat treatment for the After PR sample on the desorption of the carbon residual components was confirmed.
Specifically, the desorption quantity of CO is 1.0×1015 cm−2 in the case of the After PR sample which is not heat-treated (R. T.), 0.5×1015 cm−2 in the case of the After PR sample which is heat-treated at 300° C. for 1 hour, 1.5×1014 cm−2 in the case of the After PR sample which is heat-treated at 350° C. for 1 hour, and the After PR sample which is heat-treated at 400° C. for 1 hour was at the lower limit of detection (1.0×1014 cm−2) or less.
Considering the results of the TDS measurements and the results of the Auger electron spectroscopy measurements, CO desorption is 1.0×1015 cm−2 in the case of the After PR samples which are not heat-treated (R. T.), and 50 at % of carbon atoms were measured at the outermost surface. In this case, based on a relationship described below, it can be said that an average concentration of carbon atoms ranging from the surface to the depth of 5 nm of the ITZO film is about 1.0×1022 cm−3 and is at least more than 1.5×1021 cm−3.
For the After PR sample which is heat-treated at 400° C. for 1 hour, CO desorption is below the lower limit of detection (1.0×1014 cm−2) by TDS and 8 at % of carbon was measured at the outermost surface by Auger electron spectroscopy. In this case, it can be said that the average concentration of carbon atoms in an area from the surface to the depth of 5 nm of the ITZO film is 3.5×1020 cm−3.
In the case of the After PR sample heat-treated at 350° C. for 1 hour, the CO desorption amount is 1.5×1014 cm−2. Considering the TDS measurement results, the highest concentration of carbon atoms at the outermost surface is estimated to be 19 at % in the case where the heat treatment is performed at 350° C. for the sample after the heat treatment. In this case, it can be said that the average concentration of carbon atoms in an area from the surface to the depth of 5 nm of the ITZO film is 1.5×1021 cm−3.
A relationship between the results of the TDS measurements and the results of the Auger electron spectroscopy measurements and the carbon-atom concentration is explained. ITZO has an atomic count of approximately 8.0×1022 cm−3 per unit volume (1 cubic centimeter) in view of molecular weight and film density. According to the results of the Auger electron spectroscopy measurement, the total amount of C relative to the total amount of In, Sn, Zn and O contained in the depth of 5 nm from the surface of ITZO film (sputtering time: 2 minutes) is hereinafter referred to as carbon-relative concentration. The carbon-relative concentration is obtained as a value obtained by integrating the atomic percentage of C in the range from the surface to a depth of 5 nm relative to a value (100×5) obtained by integrating 100% in the range from the surface to a depth of 5 nm.
According to the After PR samples without the heat treatment, the carbon-relative concentration is approximately 12.5%. By multiplying the relative carbon concentration by the number of atoms per unit volume described above, the number of carbon atoms per unit volume can be obtained. The number of carbon atoms per unit volume corresponds to the average concentration in an area from the surface to the depth of 5 nm, hereinafter referred to as a carbon atom concentration.
In the case of the After PR sample without the heat treatment, the carbon atom concentration is calculated as about 1.0×1022 cm−3. On the other hand, in the case of the After PR sample which is heat-treated at 400° C. for 1 hour, a calculated carbon atom concentration is 3.5×1020 cm−3. Here, according to the TDS measurement results, the After PR sample which is heat-treated at 350° C. for 1 hour has a CO desorption amount of 0.15 times that of the After PR sample which is not heat-treated. Therefore, a carbon atom concentration is estimated to be 1.5×1021 cm−3 in the case of After PR samples heat-treated at 350° C. for 1 hour.
Considering profiles of the carbon atoms of the Auger electron spectroscopy measurement of the After PR sample which is not heat-treated and the After PR sample which is heat-treated at 400° C. for 1 hour and the carbon atom concentration described above, it is estimated from the carbon atom concentration that the highest concentration of carbon atoms at the outermost surface is 19 at % in the case of the After PR sample heat-treated at 350° C. for 1 hour.
A position of the channel CH in the semiconductor layer 150 in the thin film transistor 100 may be defined as follows. In the case of the backchannel-side surface 150b, if measured by Auger electron spectroscopy as described above from an inorganic insulating film of the adjacent interlayer insulating layer 200 toward the semiconductor layer 150 (channel CH), the position where In, Sn and Zn are detected is defined as the surface. On the other hand, in the case of the gate-side surface 150g, if measured by Auger electron spectroscopy as described above from the neighboring gate insulating layer 130 toward the semiconductor layer 150 (channel CH), the position where In, Sn and Zn are detected is defined as the surface.
[Effect on NBTS]
In the thin film transistor for threshold measurement, as shown in
[Effect on NBIS]
In the thin film transistor for threshold measurement, after the source electrode 176 and the drain electrode 177 were formed as shown in
In the case where a thin film transistor having the amount of the threshold shift of “−6.5V” due to the NBIS is used in a display device and the amount of this shift is problematic, a light shielding layer may be provided in the vicinity of the thin film transistor so as to prevent a light entry path to the channel CH. Since the intrusion of light is prevented by the light shielding layer, the negative shift of the threshold can be further reduced, and thus reliability of the thin film transistor can be improved.
Although the light shielding layer is not included in a display device according to an embodiment, the light shielding layer may be arranged in the upper layer or the lower layer of the thin film transistor 100 so as to prevent the light from entering the channel CH. By reducing the carbon residual component, the amount of the threshold shift is reduced even under light irradiation. Therefore, in order to achieve the amount of the threshold shift necessary for ensuring reliability, the amount of light to be shielded can also be reduced. As a result, by reducing the carbon residual component, the light-shielding layer arranged around the thin film transistor 100 can be made small or omitted.
[Effect of UV Ozone Treatment on Carbon Residual Components]
An effect of the UV ozone treatment on the After PR samples on the desorption of carbon residual components was confirmed.
Since the UV ozone treatment can be performed even at room temperature, even if the thin film transistor 100 shown in
[Effect on NBTS]
In thin film transistors for threshold measurement, a UV ozonated thin film transistor was prepared after the source electrode 176 and the drain electrode 177 were formed as shown in
The amount of the threshold shift due to the PBTS is kept sufficiently small as in the case of the NBTS. Although omitted in the above explanation, the PBTS is presented for reference because the amount of the threshold shift is kept small without reducing the carbon residual components (the UV ozone treatment or the heat treatment) with respect to the After PR sample.
[Modification]
The present disclosure is not limited to the embodiments described above, and includes various other modifications. For example, the embodiments described above have been described in detail for the purpose of showing the present disclosure clearly, and are not necessarily limited to those having all the described configurations. It is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. Some modification examples will be described below.
[Thin Film Transistor with Other Structure]
The thin film transistor used in the display device 1000 is not limited to the thin film transistor 100 in the embodiment described above, and thin film transistors having various structures can be adopted. In the following description, two exemplary configurations of a thin film transistor containing ITZO will be described.
The thin film transistor 100 is a BCE thin film transistor, but an ESL (Etch Stop Layer) thin film transistor may be applied to the display device 1000.
In the ESL thin film transistor 100A, a position where the source electrode 171 and the drain electrode 172 are in contact with the semiconductor layer 150 due to the presence of the etch-stop layer 150e differs from the BCE thin film transistor 100. Therefore, as shown in
Although the thin film transistor 100 is a bottom-gate thin film transistor, a top-gate thin film transistor may be applied to the display device 1000.
In the top-gate thin film transistor 100B, a part of the semiconductor layer 150B immediately below the gate electrode 120B corresponds to the channel CH. A source area 151B is formed on a source electrode 171B side with respect to the channel CH, and a drain area 152B is formed on a drain electrode 172B side with respect to the channel CH. For example, the source area 151B and the drain area 152B are, for example, areas in which the resistivity is reduced by supplying hydrogen or the like to the semiconductor layer 150B by self-alignment using the gate electrode 120B as a mask.
As described above, even if a thin film transistor having any configuration is applied to the display device 1000, the treatment (heat treatment or UV ozone treatment) may be performed in which the carbon residual components are desorbed while the channel CH is exposed. Then, after the desorption process and prior to the formation of the layer containing carbon atoms (e.g., photoresist, organic insulating layer, and the like) on the channel CH, an insulating layer (e.g., an inorganic insulating material such as silicon oxide) that protects the channel CH from carbon atoms may be formed.
A thin film transistor containing a semiconductive material other than ITZO may be used in combination with the thin film transistor 100. The semiconductor material other than ITZO may be, for example, another metal oxide semiconductor (for example, IGZO) or a semiconductor containing silicon such as amorphous silicon or polysilicon.
[Application to Electronic Appliance]
The display device 1000 described above may be applied as a display of various electronic appliances such as a smartphone, a laptop computer, and a television. The display device 1000 is not limited to the organic EL display including the light-emitting layer whose light emission is controlled by the pixel circuit. For example, the display device 1000 may be a micro LED display in which the light emitting layer is an LED (Light Emitting Diode), or may be a display including an optical element whose optical properties are controlled by the pixel circuit, for example, a liquid crystal display including a liquid crystal as an optical element.
The thin film transistor described above is not limited to the case where the thin film transistor is applied to an element constituting the display device 1000, and may be applied to an element constituting the control device 1600, the storage device 1700, and the like. That is, the electronic appliance in which the thin film transistor 100 is included may be a configuration in which the display device 1000 is not provided. Examples of the electronic appliance include an electronic appliance other than a display device, such as a storage device, a logic circuit and a peripheral circuit device thereof, a wireless signal processing device, an input device, an imaging device, a neuromorphic computing device, and the like. A thin film transistor containing a semiconductor material other than ITZO may be further applied to such an electronic appliance in combination with a thin film transistor containing ITZO.
[ZSO Passivation Layers]
In the thin film transistor 100, the backchannel-side surface 150b in the channel CH may be covered with a passivation layer formed of a predetermined film to form an insulating layer covering the channel. The passivation layer is preferably an oxide thin film that can be formed by a DC sputtering method under an oxygen-containing atmosphere, and is formed by, for example, an amorphous ZSO (ZnSiO) film. From the viewpoint of adhesion, although the passivation layer preferably contains amorphous at least in part, it may contain a crystal structure such as a microcrystal in part. Although a thickness of the passivation layers may be varied, for example, 2 nm or more and 200 nm or less is preferable, and 3 nm or more and 50 nm or less is more preferable. In this example, the thickness of the passivation layers is 5 nm. The passivation layers can also be applied to the top-gate thin film transistor 100B shown in
The ZSO film is formed by the DC sputtering using a target containing ZnO and SiO2. The ZSO film as the passivation layer has an insulating property. ZSO changes from an insulating state to a conductive state by increasing the ratio of ZnO to SiO2. The ZSO film can be formed by the DC sputtering because it is formed with a target of ZSO having conductivity. In order to prevent reduction of the surface of the semiconductor layer 150, it is preferable that the target of ZSO be contained as a metal oxide instead of Zn as a metal. On the other hand, the passivation layer of the insulating ZSO film is formed by controlling the conditions of sputtering. The ZSO film may be formed by the PVD method other than the DC sputtering, or may be formed by the CVD method or the ALD method as long as the carbon residual components that eventually occur on the surface of the channel CH can be reduced.
The passivation layer is not limited to a ZSO film which is a metal oxide layer containing Zn and silicon (Si), and may be, for example, a ZSTO film which is a metal oxide layer containing Zn, Si, and Sn. In this case, it may be formed by the DC sputtering in an oxygen-containing atmosphere using a target containing ZnO, SnO2 or a target containing ZnO, SiO2, and SnO2.
In the ZSO film, the molar ratio of Zn/(Zn+Si) is preferably in the range of 0.30 or more and 0.95 or less, and more preferably in the range of 0.40 or more and 0.85 or less. In the ZSTO film, the molar ratio of Sn/(Zn+Sn+Si) is preferably in the range of 0.15 or more and 0.95 or less. The molar ratio of Si/(Zn+Sn+Si) is preferably in the range of 0.07 or more and 0.30 or less. These molar ratios are values in films.
The passivation layers may further contain at least one of titanium (Ti), gallium (Ga), niobium (Nb), aluminum (Al), and In with respect to the ZSO film or the ZSTO film. Also in this case, these elements are preferably contained in the target as a metal oxide.
The electron affinity of the passivation layer is preferably smaller than the electron affinity of the semiconductor layer 150 (in this case, the ITZO film). Further, it is preferable that the electron affinity of the passivation layer is in a range of 2.0 eV or more and 4.0 eV or less, and an ionization potential of the passivation layer is in a range of 6.0 eV or more and 8.5 eV or less. More preferably, the electron affinity is in a range of 2.2 eV or more and 3.5 eV or less, and even more preferably in a range of 2.5 eV or more and 3.0 eV or less. A more preferable ionization potential is in a range of 6.0 eV or more and 7.5 eV or less, more preferably in a range of 6.0 eV or more and 7.0 eV or less. By providing a passivation layer having a smaller electron affinity than that of the semiconductor layer, the passivation layer has an effect of preventing injection of electrons from the outside into the semiconductor layer. Further, by providing a passivation layer having an ionization potential larger than that of the semiconductor layer, it is possible to prevent injection of holes from the outside into the semiconductor layer. As a result, it is possible to reduce the threshold shift due to NBS or PBS (Positive Bias Stress).
The electron affinity of the passivation layer can be adjusted by changing the composition ratio in the target. For example, in the case of the ZSO film, a desired electron affinity can be achieved depending on the ratio of ZnO and SiO2 in the target. The electron affinity and the ionization potential can be obtained by a known measurement method such as a quantum chemical theory calculation (electron affinity=energy difference between neutral molecules and anions, ionization potential=energy difference between cations and neutral molecules), or a photoelectron spectroscopy. Specifically, the ionization potential is evaluated using an ultraviolet photoelectron spectroscopy, a band gap is evaluated using a spectrophotometer, and the electron affinity is calculated from the difference between the ionization potential and the band gap.
In a thin film transistor 100D shown in
A thin film transistor 100E including an etch-stop layer 150eE shown in
Thus, the present inventors have found that the passivation layer made of the ZSO film further reduces the threshold shift due to a negative gate-voltage application at 60° C. or under a light irradiation condition. It is considered that the passivation layer reduces the surface level of ITZO and prevents the transfer of charges between ITZO and the outside. Hereinafter, a result of reducing the threshold shift will be described. The thin film transistor for threshold shift measurement corresponds to the thin film transistor for threshold shift measurement shown in
In the case without the passivation layer of the ZSO film, the threshold at 60° C. is shifted to more negative than the threshold at room temperature. On the other hand, in the case where the passivation layers of ZSO film are used, the thresholds are hardly shifted even at 60° C. than the threshold at room temperature. In this way, the passivation layer of the ZSO film reduces the temperature dependence of the threshold.
As shown in
By forming the ZSO film by the DC sputtering, an effect of reducing impurities at the surface of the ITZO film and the interface between the ZSO film and the ITZO film, and an effect of preventing damage caused by the respective processes are produced. As a result, it is presumed that the passivation layer of the ZSO film can improve these effects. The DC sputtering in an oxygen-containing atmosphere also reduces the carbon residual components described above. Therefore, it is also expected to omit the heat treatment and the UV ozone treatment for reducing the carbon residual components, or to replace the heat treatment and the UV ozone treatment with a simple treatment (low temperature, low illumination, or shortened treatment times).
[For ITZO of Different Composition]
In the embodiment described above, although the composition ratio In:Sn:Zn of the target is 20:40:40 (at %), it is not limited to this composition ratio. The measurement results of a threshold shifts due to the NBTS, the PBTS and the NBIS are explained when the composition ratio of the sample is 40:40:20 (at %).
Although in the case where the composition ratio of the targets is In0.4Sn0.4Zn0.2Ox, the negative shift of the thresholds is slightly larger because the mobility is higher than in the case where the composition ratio is In0.2Sn0.4Zn0.4Ox, there is no large difference. As described above, even in ITZO other than a particular composition ratio, reducing effects to the threshold shift in various voltage stresses can be obtained by the same method. According to ITZO in which the mobility is at least equal to or lower than 70 cm2/Vs, it has been confirmed that the threshold shift in the voltage stress is sufficiently reduced.
For example, the amount of the threshold shift having a sufficient reducing effect is preferably 3 V or less, and more preferably 1 V or less. If such a reducing effect is obtained, ITZO having a higher mobility can also be applied to the thin film transistor.
[Thin Film Transistor Using Metal Oxide Semiconductor Other than ITZO]
It has been found that the threshold shift due to the voltage stress in the thin film transistor including an ITZO film as the semiconductor described in detail above can be reduced by the reduction process of carbon residual components in ITGO (In—Sn—Ga oxide) and IZO (In—Zn oxide), in addition to ITZO. Therefore, the knowledge on the effectiveness of reducing carbon residual components described above can be generally applied to a thin film transistor containing a metal oxide semiconductor containing In as a channel. It can be said that the knowledge of the passivation layer can be generally applied to the thin film transistor containing the metal oxide semiconductor containing In as the channel by using a passivation layer having an electron affinity smaller and ionization potential larger than those of the semiconductor layer. As described above, the present invention can be particularly suitably applied to a thin film transistor using a metal oxide semiconductor having a high field-effect mobility. This high field-effect mobility is preferably 20 cm2/Vs or more, particularly preferably 40 cm2/Vs or more.
Effects of the UV ozone treatment on the threshold shift due to the NBS in the case where the ITGO film or the IZO film is applied to the semiconducting layers are explained.
According to the embodiment described above, it is possible to effectively reduce the threshold shift due to the voltage stress occurring in the thin film transistor including the metal oxide semiconductor layers containing In. In addition, according to the embodiment described above, it is possible to effectively reduce the threshold shift due to the NBTS occurring in the thin film transistor including ITZO.
The thin film transistor described above may have the following features.
In an embodiment, a thin film transistor is formed on a substrate, the thin film transistor includes a channel formed by at least part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer arranged between the channel and the gate electrode, a source electrode connected to the metal oxide semiconductor layer, and a drain electrode connected to the metal oxide semiconductor layer. The average concentration of carbon atoms in an area from a surface to the depth of 5 nm of the channel is 1.5×1021 cm−3 or less. The average concentration of carbon atoms in the area may be 3.5×1020 cm−3 or less.
In an embodiment, a thin film transistor is formed on a substrate, the thin film transistor includes a channel formed by at least part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer arranged between the channel and the gate electrode, a source electrode connected to the metal oxide semiconductor layer, and a drain electrode connected to the metal oxide semiconductor layer. The maximum concentration of carbon atoms in an area from a surface to the depth of 5 nm of the channel is 19 at % or less. The maximum concentration may be 8 at % or less.
The gate electrode may be arranged between the substrate and the channel.
The source electrode and the drain electrode may contain a conductive material having oxidation resistance.
The channel may be arranged between the substrate and the gate electrode.
In the metal oxide semiconductor layer, a part of the surface covered with the source electrode and a part of the surface covered with the drain electrode may have a higher concentration of carbon atoms than the surface of the channel.
The amount of a threshold shift may be 0.5 V or less in the case where it is maintained for 3600 seconds that a voltage of the gate electrode with respect to the source electrode and the drain electrode is controlled to be Vth−20 V in a temperature of 60° C. and a dark state.
The metal oxide semiconductor layer may further contain tin (Sn) and zinc (Zn).
An insulating passivation layer covering the channel may be further included. The passivation layer may be a metal oxide layer containing Zn and Si.
In an embodiment, a thin film transistor is formed on a substrate, the thin film transistor includes a channel formed by at least part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer arranged between the channel and the gate electrode, a source electrode connected to the metal oxide semiconductor layer, a drain electrode connected to the metal oxide semiconductor layer, and a passivation layer covering the channel and having an insulating property. The electron affinity of the passivation layer is less than the electron affinity of the metal oxide semiconductor layer.
The electron affinity of the passivation layers may be in a range of 2.0 eV or more and 4.0 eV or less. The ionization potential of the passivation layer may be in a range of 6.0 eV or more and 8.5 eV or less.
The passivation layer may contain amorphous material.
The metal oxide semiconductor layer may further contain tin (Sn) and zinc (Zn).
In an embodiment, a display device includes a plurality of pixel circuits, and each of the plurality of pixel circuits includes the thin film transistor described above.
A plurality of light emitting elements may be included. The plurality of pixel circuits may control light emission by the plurality of light emitting elements.
In an embodiment, an electronic appliance includes the display device described above and a control device that controls the display device.
In an embodiment, a method of manufacturing a thin film transistor includes forming a thin film transistor on a substrate, heating the thin film transistor to 350° C. or higher in atmosphere containing oxygen while a channel is exposed, and forming an insulating layer covering the channel after the heating and before a material containing carbon atoms contacts an exposed portion of the channel. The thin film transistor includes the channel formed by at least part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer arranged between the channel and the gate electrode, a source electrode connected to the metal oxide semiconductor layer on a substrate, and a drain electrode connected to the metal oxide semiconductor layer.
In an embodiment, a method of manufacturing a thin film transistor includes forming a thin film transistor on a substrate, irradiating ultraviolet light in an oxygen-containing atmosphere while a channel is exposed, and forming an insulating layer covering the channel after the irradiating process and before a material containing carbon atoms contacts an exposed portion of the channel. The thin film transistor includes the channel formed by at least part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer arranged between the channel and the gate electrode, a source electrode connected to the metal oxide semiconductor layer, and a drain electrode connected to the metal oxide semiconductor layer.
In an embodiment, a method of manufacturing a thin film transistor includes forming a thin film transistor on a substrate and forming an insulating layer covering a channel by a DC sputtering in an oxygen-containing atmosphere while a channel is exposed. The thin film transistor includes the channel formed by at least part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer arranged between the channel and the gate electrode, a source electrode connected to the metal oxide semiconductor layer, and a drain electrode connected to the metal oxide semiconductor layer.
A target used in the DC sputtering may be a metal oxide having conductivity.
The metal oxide semiconductor layer may be formed by the PVD method.
The average concentration of carbon atoms in an area from a surface to the depth of 5 nm of the exposed portion of the channels prior to the insulating layer being formed may be 1.5×1021 cm−3 or less after the insulating layer is formed. The average concentration may be 3.5×1020 cm−3 or less after the insulating layer is formed.
The maximum concentration of carbon atoms in an area from a surface to the depth of 5 nm of the exposed portion of the channels prior to the insulating layer being formed may be 19 at % or less after the insulating layer is formed. The maximum concentration may be 8 at % or less after the insulating layer is formed.
The gate electrode may be arranged between the substrate and the channel. After the source electrode and the drain electrode are formed, at least part of the carbon atoms present on the surface of the channel may be desorbed.
The channel may be arranged between the substrate and the gate electrode. The insulating layer protecting from carbon atoms may be the gate insulating layer. Before the source electrode and the drain electrode are formed, at least part of the carbon atoms present on the surface of the channel may be desorbed.
The metal oxide semiconductor layer may further contain tin (Sn) and zinc (Zn).
The insulating layer may be a metallic oxide layer containing Zn and Si.
In an embodiment, a method of manufacturing a thin film transistor includes forming a thin film transistor on a substrate, the thin film transistor including a channel formed by at least part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer arranged between the channel and the gate electrode, a source electrode connected to the metal oxide semiconductor layer, a drain electrode connected to the metal oxide semiconductor layer, and a passivation layer having an insulating property and covering the channel. The electron affinity of the passivation layer is smaller than the electron affinity of the metal oxide semiconductor layer.
The electron affinity of the passivation layers may be in a range of 2.0 eV or more and 4.0 eV or less. The ionization potential of the passivation layer may be in a range of 6.0 eV or more and 8.5 eV or less.
The passivation layer may contain amorphous material.
The metal oxide semiconductor layer may further contain tin (Sn) and zinc (Zn).
A thin film transistor formed on a substrate, including:
The channel may have a ratio of Sn to the sum of In and Sn and Zn of 30 (at %) or more. The channel may have a ratio of Sn to the sum of In and Sn and Zn of 40 (at %) or more.
The channel may have a field-effect mobility of 40 cm2/Vs or more. The channel may have a field-effect mobility of 60 cm2/Vs or more.
The insulating layer may be a metal oxide layer containing Zn and Si.
A length of the channel may be 50 μm or less. The length of the channel may be 20 μm or less.
The amount of the threshold shift due to the NBTS may be 1 V or less.
The amount of the threshold shift due to PBTS may be 1 V or less.
The amount of the threshold shift due to NBIS may be 1 V or less.
1: first substrate, 2: second substrate, 10: first supporting substrate, 100, 100A, 100B, 100C, 100D, 100E: thin film transistor, 110: base insulating layer, 120, 120B, 125: gate electrode, 130, 135: gate insulating layer, 150, 150B, 155: semiconductor layer, 150a: upper surface, 150b, 150Bb, 155b: backchannel-side surface, 150d: drain surface, 150e, 150eE: etch-stop layer, 151B: source area, 152B: drain area, 155f: ITZO film, 150g, 150Bg, 155g: gate-side surface, 150s: source surface, 160, 160D: passivation layer, 171, 171B, 176: source electrode, 172, 172B, 177: drain electrode, 175f: gold film, 200: interlayer insulating layer, 300: pixel electrode, 400: bank layer, 500: light emitting layer, 600: counter electrode, 900: sealing layer, 1000: display device, 1500: housing, 1600: control device, 1700: storage device, 2000: electronic appliance.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-026653 | Feb 2021 | JP | national |
| 2021-174071 | Oct 2021 | JP | national |
This application is a Continuation of International Patent Application No. PCT/JP2022/006733, filed on Feb. 18, 2022, which claims the benefit of priority to Japanese Patent Application No. 2021-026653, filed on Feb. 22, 2021 and Japanese Patent Application No. 2021-174071, filed on Oct. 25, 2021, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2022/006733 | Feb 2022 | US |
| Child | 18233414 | US |
