Patent Grant
8466465
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application earlier filed in the Korean Intellectual Property Office on 4 Aug. 2008 and there duly assigned Serial No. 10-2008-0076010.
1. Field of the Invention
The present invention relates to a thin film transistor, a method of manufacturing the same and a flat panel display device having the same, and more particularly to a thin film transistor which has an oxide semiconductor as an activation layer, a method of manufacturing the same and a flat panel display device having the same.
2. Description of the Related Art
A thin film transistor generally includes an activation layer which provides a channel region, a source region, and a drain region, and a gate electrode which is formed on the channel region and electrically insulated from the activation layer by a gate insulating film.
The activation layer of the thin film transistor formed as described above is generally formed of a semiconductor material, such as amorphous silicon or poly-silicon. However, if the activation layer of the thin film transistor is formed of amorphous silicon, it is difficult to implement a driving circuit operating at high speed due to low mobility. Meanwhile, if the activation layer is formed of poly-silicon, mobility is high, but a separate compensation circuit should be added due to uneven threshold voltage.
Also, a conventional method of manufacturing a thin film transistor using a low temperature poly-silicon (LTPS) involves an expensive process such as a laser annealing and has difficulty in property control, so it is difficult to be applied to a large-area substrate.
A study using an oxide semiconductor as an activation layer has been recently conducted in order to solve the problems.
Japanese Laid-Open Patent Publication No. 2004-273614 discloses a thin film transistor which has zinc oxide (ZnO) or an oxide semiconductor having zinc oxide (ZnO) as a main ingredient, as an activation layer.
The compound semiconductor having zinc oxide (ZnO) as a main ingredient is evaluated as a stable material, having an amorphous shape. If such a compound semiconductor is used as an activation layer, the compound semiconductor has various advantages in that the thin film transistor may be manufactured at a low temperature below 350° C. using the existing processing equipment, without additionally buying separate processing equipments, and an ion implantation process may be omitted.
However, there is a need for the development of process and the improvement of property capable of satisfying the electrical property in order to apply the oxide semiconductor to the device.
One of objects of the present invention is to provide a thin film transistor which can maintain stable semiconductor property of an oxide semiconductor layer, a method of manufacturing the same, and a flat panel display device having the same.
In order to accomplish the above object, according to one aspect of the present invention, there is provided a thin film transistor including a substrate; an oxide semiconductor layer formed on the substrate and including a channel region, a source region and a drain region; a gate electrode insulated from the oxide semiconductor layer by a gate insulating film; and source electrode and drain electrode which are coupled to the source region and the drain region, respectively. The oxide semiconductor layer includes a first layer portion and a second layer portion. The first layer portion has a first thickness and a first carrier concentration, and the second layer portion has a second thickness and a second carrier concentration. The second carrier concentration is lower than the first carrier concentration.
In order to accomplish the above object, according to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, including forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming an oxide semiconductor layer on the gate insulating film; and forming a source electrode; and forming a drain electrode. The oxide semiconductor layer includes a channel region, a source region, and a drain region, the step of forming the oxide semiconductor layer comprising depositing a first layer portion having a first thickness and a first carrier concentration; and depositing a second layer portion having a second thickness and a second carrier concentration. The second carrier concentration is lower than the first carrier concentration. The source electrode is formed to be coupled to the source region, and the drain is formed to be coupled to the drain region.
In order to accomplish the above object, according to another aspect of the present invention, there is provided a flat panel display device, including a first substrate; a second substrate including a second electrode; and a liquid crystal layer disposed between the first electrode and second electrode. The first substrate includes a first conductive line, a second conductive line, a thin film transistors coupled to the first conductive line and the second conductive line, and a first electrode coupled to the thin film transistor. Signals supplied to the first electrode are controlled by the thin film transistor. The thin film transistor of the first substrate includes an oxide semiconductor layer formed on the substrate and including a channel region, a source region and a drain region; a gate electrode insulated from the oxide semiconductor layer by a gate insulating film; a source electrode coupled to the source region; and a drain electrode coupled to the drain region. The oxide semiconductor layer includes a first layer portion and a second layer portion. The first layer portion has a first thickness and a first carrier concentration, and the second layer portion has a second thickness and a second carrier concentration. The second carrier concentration is lower than the first carrier concentration.
In order to accomplish the above object, according to another aspect of the present invention, there is provided a flat panel display device, including a first substrate; and a second substrate disposed facing the first substrate. The first substrate includes an organic light emitting device including a first electrode, an organic thin film layer, and a second electrode, and a thin film transistor coupled to the organic light emitting device to control an operation of the organic light emitting device. The thin film transistor of the first substrate includes an oxide semiconductor layer formed on the substrate and including a channel region, a source region and a drain region; a gate electrode insulated from the oxide semiconductor layer by a gate insulating film; a source electrode coupled to the source region; and a drain electrode coupled to the drain region. The oxide semiconductor layer includes a first layer portion and a second layer portion. The first layer portion has a first thickness and a first carrier concentration, and the second layer portion has a second thickness and a second carrier concentration. The second carrier concentration is lower than the first carrier concentration.
The present invention controls a carrier concentration on an upper layer portion to be lower than that on a lower layer portion by controlling an oxygen partial pressure when an oxide semiconductor layer used as an activation layer of a thin film transistor is formed. By controlling the carrier concentration on the upper layer portion to be lower than that on the lower layer portion in preparation for the change in the carrier concentration, the present invention can maintain the carrier concentration above a predetermined level that can maintain the semiconductor property, even if the carrier concentration is increased by plasma damage while forming a passivation layer for protecting the thin film transistor. The present invention does not add a separate process for preventing the property of the oxide semiconductor layer from being changed and applies an existing process for forming the passivation layer as it is, thereby making it possible to improve the compatibility of processes and equipments and prevent increase in manufacturing costs.
A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. In addition, when an element is referred to as being “on” another element, it can be directly on another element or be indirectly on the element with one or more intervening elements interposed therebetween. Also, when an element is referred to as being “connected to” another element, it can be directly connected to the element or be indirectly connected to the element with one or more intervening elements interposed therebetween. Hereinafter, like reference numerals refer to like elements.
Hereinafter, exemplary embodiments according to the present invention will be described with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily carry out the present invention. However, the present invention may be modified in many different forms and it should not be limited to the embodiments set forth herein.
A buffer layer 12 is formed on a substrate 10 made of an insulating material, and a gate electrode 14 is formed on the buffer layer 12. An oxide semiconductor layer 18, which is insulated from the gate electrode 14 by a gate insulating film 16 and provides a channel region, a source region, and a drain region, is formed on an upper layer portion of the gate insulating film 16 that covers the gate electrode 14.
The oxide semiconductor layer 18 has zinc oxide (ZnO) as a main ingredient and is formed of a GaInZnO (GIZO) layer doped with ion of gallium (Ga) or ion of indium (In), or both of them. At this time, the GIZO layer includes a lower layer portion 18a (or a first layer portion) having a carrier concentration of about 1×105 1/cm3 to 1×1017 1/cm3, and an upper layer portion 18b (or a second layer portion) having a carrier concentration lower than that of the lower layer portion 18a. Herein, the unit of carrier concentration (1/cm3) represents number per cubic centimeters. For example, a carrier concentration of the upper layer portion 18b can be about 1×1012 1/cm3 to 1×1015 1/cm3. In other words, the lower layer portion 18a having a predetermined first thickness from an interface contacting the gate insulating film 16 has a first carrier concentration of 1×1015 1/cm3 to 1×1017 1/cm3, and the upper layer portion 18b having a remaining second thickness has a second carrier concentration of about 1×1012 1/cm3 to 1×1015 1/cm3. The lower layer portion 18a, which is a portion where a channel is formed, has a first thickness of 5 nm to 30 nm from the interface contacting the gate insulating film 16, more preferably, a thickness of 5 nm to 10 nm.
Referring to
Referring to
When forming the GaInZnO (GIZO) layer according to the present invention, a carrier concentration of a lower layer portion 18a is controlled to 1×1015 1/cm3 to 1×1017 1/cm3, and a carrier concentration of an upper layer portion 18b is controlled to be lower than the carrier concentration of the lower layer portion 18a. For example, the carrier concentration of the upper layer portion 18b can be about 1×102 1/cm3 to 1×1015 1/cm3. The lower layer portion 18a, which is a portion where a channel is formed, has a thickness of 5 nm to 30 nm from the interface contacting the gate insulating film 16, more preferably, a thickness of 5 nm to 10 nm.
A method for forming the GIZO layer may include a co-sputtering method using two or more targets, such as GaInZnO, InZno and Ga2O3, or a pulse laser deposition method.
The carrier concentration may be controlled by a specific gravity occupied by oxygen, that is, an oxygen partial pressure. For example, if the oxygen partial pressure is controlled to the range of 30 to 90%, the carrier concentration may be controlled optionally within the range of 1×1012 1/cm3 to 1×1015 1/cm3.
If the oxygen partial pressure is increased, oxygen element content within a thin film is increased by reactive sputtering, so one oxygen element is coupled with two electrons within the thin film, thereby reducing the carrier concentration. The GIZO layer is an N type oxide semiconductor, wherein electrons become carriers.
The oxygen concentration difference between the lower layer portion 18a and the upper layer portion 18b according to the control in the oxygen partial pressure may be checked by the Rutherford Backscattering Spectrometry (RBS) analysis or the like.
In case of the GIZO layer, if the carrier concentration is controlled by the oxygen partial pressure, the semiconductor property may be changed into the quasi-conductor property and the carrier concentration may be changed according to the depth (thickness). However, the content ratio of positive ions may not be changed.
The lower layer portion 18a of the GIZO layer constituted as above has specific resistance about 1×102 to 1×104 Ω·cm, and the upper layer portion 18b thereof has specific resistance about 1×104 to 1×106 Ω·cm that is higher than the specific resistance.
Referring to
At this time, assuming that both the lower layer portion 18a and upper layer portion 18b of the oxide semiconductor layer 18 have a concentration about 1×1015 1/cm3 to 1×1017 1/cm3, the oxygen concentration of the upper layer portion 18b is reduced due to the plasma damage during the process of forming the passivation layer 22 so that the carrier concentration is more increased. If the carrier concentration is increased to 1×1017 1/cm3 or more, the oxide semiconductor layer 18 has the conductive property due to the reduction in specific resistance and thus fails to maintain the semiconductor property.
However, the present invention controls the carrier concentration of the upper layer portion 18b to be lower than the lower layer portion 18a, making it possible to maintain the carrier concentration (below 1×1017 1/cm3) such that the oxide semiconductor layer may have semiconductor property even if the carrier concentration is increased due to the plasma damage during the process of forming the passivation layer 22.
Referring to
However, when the oxygen partial pressure is controlled to 35% according to the present invention, as shown in
The thin film transistor of the present invention may be applied to a flat panel display device such as a liquid crystal display device or an organic light emitting display device.
The display panel 100 includes a first substrate 110 and a second substrate 120 disposed to face each other, and a liquid crystal layer 130 interposed between the first and second substrates 110 and 120, wherein a pixel region 113 is defined by a plurality of gate lines 111 and data lines 112 arranged on the substrate 110 in a matrix type. The gate lines 111 and the data lines 112 can be referred to as a first conductive line and second conductive lines, respectively, and vice versa. A thin film transistor 114 which controls signals to be supplied to each pixel and a pixel electrode 115 (or a first electrode) connected to the thin film transistor 114 are formed on a part of the substrate 110, where the gate lines 111 intersect with the data lines 112.
The thin film transistor 114, which has the structure of
Also, a color filter 121 and a common electrode 122 (or a second electrode) are formed on the substrate 120. Further, a first polarizing plate 116 and a second polarizing plate 123 are formed on outer surfaces of the substrates 110 and 120, respectively, and a backlight (not shown) is disposed behind the polarizing plate 116 as a light source.
Meanwhile, a driver LCD Drive IC (not shown) which drives the display panel 100 is mounted in a peripheral of a pixel region 113 of the display panel 100. The driver converts electrical signals provided from the external into scan signals and data signals to supply them to the gate lines 111 and the data lines 112.
Referring to
Referring to
The thin film transistor has the structure of
The organic light emitting device 300 including the thin film transistor constituted as above will be described in more detail with reference to
A buffer layer 12 is formed on a substrate 10, and a gate electrode 14 is formed on the buffer layer 12 in a pixel region 220. At this time, scan lines 224 coupled to a gate electrode 14 may be formed in the pixel region 220, and the scan lines 224 extending from the scan lines 224 in the pixel region 220 and pads 228 to receive signals from the external may be formed in a non-pixel region 230.
An oxide semiconductor layer 18, which is insulated from the gate electrode 14 by a gate insulating film 16 and provides a channel region, a source region, and a drain region, is formed on an upper portion including the gate electrode 14.
The oxide semiconductor layer 18 has zinc oxide (ZnO) as a main ingredient and is formed of a GaInZnO (GIZO) layer doped with ion of gallium (Ga) or ion indium (In). At this time, the GIZO layer includes a lower layer portion 18a having a carrier concentration of about 1×1015 1/cm3 to 1×1017 1/cm3, and an upper layer portion 18b having a carrier concentration lower than that of the lower layer portion 18a, for example, a carrier concentration of about 1×1012 1/cm3 to 1×1015 1/cm3.
Source and drain electrodes 20a and 20b are formed so as to be coupled to the source and drain regions. At this time, the data lines 226 coupled to the source and drain electrodes 20a and 20b are formed in the pixel region 220, and the data lines 226 extending from the data lines 226 in the pixel region 220 and the pads 228 to receive signals from the external are formed in the non-pixel region 230.
A passivation layer 22 is formed on the upper portion including the source and drain electrodes 20a and 20b, and a planarization layer 316 is formed on the passivation layer 22 so as to planarize the surface of the upper portion. A via hole is formed on the planarization layer 316 and the passivation layer 22 in order that the source or drain electrode 20a or 20b is exposed, and an anode electrode 317 coupled to the source or drain electrode 20a or 20b through the via hole is formed.
A pixel definition film 318 is formed on the planarization layer 316 in order that a partial region (light-emitting region) of the anode electrode 317 is exposed, an organic thin film layer 319 is formed on the exposed anode electrode 317, and a cathode electrode 320 is formed on the pixel definition film 318 including the organic thin film layer 319.
Referring to
While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, and equivalents thereof.
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| 20100026169 A1 | Feb 2010 | US |
