BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a block diagram of the driving device of the conventional TFT liquid crystal display panel with a chopper.
FIG. 1B is a voltage-to-time diagram of the POL signal and the control signal in FIG. 1A.
FIG. 1C is a voltage-to-time diagram of the ideal output waveform 102 and the actual output waveform 101 in FIG. 1A.
FIG. 1D is an offset voltage distribution diagram of the frames F11˜F14.
FIG. 2A is a block diagram of the driving device of the TFT LCD according to an embodiment of the present invention.
FIG. 2B is a block diagram of the driving device of the TFT LCD according to another embodiment of the present invention.
FIG. 2C is a circuit block diagram of the source driver 23_1.
FIG. 2D is a flow chart diagram of the operation of the modulation signals CNTRL1 and CNTRL2.
FIG. 2E is a circuit diagram of the output buffer 233_1.
FIG. 2F is a circuit diagram of another embodiment of the output buffer.
FIG. 3A is a voltage-to-time diagram of the POL signal, modulation signal CNTRL1, modulation signal CNTRL2 according to an embodiment of the present invention.
FIG. 3B is a voltage-to-time diagram of the ideal output waveform 301 and the actual output waveform 302 of the output buffer 233_1.
FIG. 3C is a voltage-to-time diagram of the ideal output waveform 303 and the actual output waveform 304 of the output buffer 233_2.
FIG. 3D is an offset voltage distribution diagram of the frames F31˜F34 according to an embodiment of the present invention.
FIG. 4 is an offset voltage distribution diagram of the frames F41˜F44 according to another embodiment of the present invention.
FIG. 5 is an offset voltage distribution diagram of the frames F51˜F54 according to another embodiment of the present invention.
FIG. 6 is an offset voltage distribution diagram of the frames F61˜F64 according to another embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
FIG. 2A is a block diagram of the driving device of a TFT LCD according to an embodiment of the present invention. A vertical synchronization signal functioning as an activating signal for eliminating the offset voltages is input into source drivers 23_1, 23_2 . . . of a TFT liquid crystal display panel driving device 230. The source drivers 23_1, 23_2 . . . drive the liquid crystal display panel together with gate drivers 22_1 . . . . FIG. 2B is a block diagram of the driving device of the TFT LCD according to another embodiment of the present invention. FIG. 2B and FIG. 2A are different in that the first output signal of the gate driver 22_1 is used as an activating signal.
Each source driver of the present embodiment has the same structure, the source driver 23_1 is taken as an example, and FIG. 2C is a circuit block diagram of the source driver 23_1. Image data is input into a processing unit 231 for pretreatment, and the display data 1˜n are output to digital-to-analog converters 232_1˜232_n and then output to the channels 1˜n through the output buffers 233_1˜233_n. A modulation signal generator 234 generates modulation signals CNTRL1 and CNTRL2, and changes the logic states of the modulation signals CNTRL1, CNTRL2 according to the activating signal. Here, the activating signal can be a vertical synchronization signal or the first output signal of the gate driver 22_1, for representing the starting time point of each frame. The modulation signal CNTRL1 is input into odd output buffers 233_1, 233_3 . . . , and the modulation signal CNTRL2 is input into even output buffers 233_2, 233_4 . . . . The output buffers 233_1˜233_n all have chopper function, and the modulation signals CNTRL1, CNTRL2 are used to eliminate the adverse effect of the offset voltages of the output buffer 233 on the frame quality. In the embodiment, the source driver is a source driving device, which utilizes the modulation signal generator 234 to control the output buffers 233_1˜233_n, so as to eliminate the offset voltages and thereby drive the device of the liquid crystal display panel.
FIG. 2D is a flow chart diagram of the operation of modulation signals CNTRL1 and CNTRL2. Initially, the preset modulation signals CNTRL1, CNTRL2 are loaded in Step S201. Then, in Step S203, the modulation signals CNTRL1, CNTRL2 are used and in Step S205, whether an activating signal is received is determined. Here, the activating signal can be a POL signal, a vertical synchronization signal or the first output signal of the gate driver 22_1, or another signal synchronous with the starting time of each frame. If the activating signal is not received, the operation goes back to Step S203 of using the current modulation signals CNTRL1 and CNTRL2. If the activating signal is received, the logic states of the modulation signals CNTRL1 and CNTRL2 are changed in Step S207.
The output buffers in the present embodiment have various structures, the output buffer 233_1 is taken as an example, and FIG. 2E is a circuit diagram of the output buffer 233_1. The output buffer 233_1 receives the modulation signal CNTRL1 to output two different offset voltages. For ease of representation, a signal φ2 is used to represent the modulation signal CNTRL1 and a signal φ1 is used to represent the inverted modulation signal /CNTRL1 in FIG. 2E. The signal φ2 controls switches SW2, SW4, SW6, SW8, and the signal φ1 controls switches SW1, SW3, SW5, SW7. A positive input end P1 and a negative input end N1 of the output buffer 233_1 are respectively connected to a control end of a P-type MOS transistor T1 and a control end of a P-type transistor T2 through switches SW1, SW2 and switches SW3, SW4, so as to input the voltages at the input ends P1, N1 in time sequence into a differential transistor pair formed by transistors T1 and T2. One end of a current source i1 is coupled to a voltage VCC and the other end is coupled to the transistors T1, T2, for providing a driving current to the transistors T1 and T2. Besides, the other ends of the transistors T1 and T2 are respectively coupled to an N-type MOS transistor T3 and an N-type MOS transistor T4, for outputting the driving current to a control end of an N-type MOS transistor T5 under the control of switches SW5, SW6, SW7 and SW8. A current source i2 provides a driving current to the transistor T5 and the transistor T5 outputs output voltages of two offset voltages from an output end Vout in time sequence.
FIG. 2F is a circuit diagram of another embodiment of the output buffer 233_2. In FIG. 2F, the output buffer 233_2 receives the modulation signal CNTRL1 to output two different offset voltages. The difference between FIG. 2F and FIG. 2E is that, in FIG. 2E, the transistors T1, T2 of the differential transistor pair coupled to the input ends P1, N1 are both P-type MOS transistors and the other transistors T3, T4, T5 are N-type MOS transistors; while in FIG. 2F, the transistors T6, T7 of the differential transistor pair coupled to the input ends P2, N2 are both N-type MOS transistors and the other transistors T8, T9, T10 are P-type MOS transistors. The positive input end P2 and the negative input end N2 of the output buffer 233_2 are respectively connected to a control end of the transistor T6 and a control end of the transistor T7 through switches SW9, SW10 and switches SW11, SW12. One end of a current source i3 is coupled to a voltage GND while the other end is coupled to the transistors T6 and T7, for providing a driving current to the transistors T6 and T7. Besides, the other ends of the transistors T6 and T7 are respectively coupled to transistors T8 and T9, for outputting the driving current to a control end of the transistor T10 under the control of switches SW13, SW14, SW15 and SW16. A current source i4 provides a driving current to the transistor T10 and the transistor T10 outputs output voltages of two offset voltages from an output end Vout2 in time sequence. FIGS. 2E and 2F are only two examples of the output buffer, and the output buffers can be optionally designed as output buffers in other forms with chopper function.
FIG. 3A is a timing diagram of the POL signal, modulation signal CNTRL1, and modulation signal CNTRL2 according to an embodiment of the present invention. Frames F31, F32, F33, F34 are respectively displayed during time periods 0˜T31, T31˜T32, T32˜T33, T33˜T34. The POL signal is Logic 1 when frames F31 and F33 are displayed, and becomes Logic 0 when frames F32 and F34 are displayed. When the frames F31 and F32 are displayed, the modulation signal CNTRL1 is Logic 1 and the modulation signal CNTRL2 is Logic 0 according to the state of the POL signal. When the frames F33 and F34 are displayed, the modulation signal CNTRL1 is changed to Logic 0 and the modulation signal CNTRL2 is changed to Logic 1 according to the state of the POL signal. Other frames can be deduced likewise according to the same cycle of every four frames.
In the present embodiment, when the modulation signal CNTRL1 is Logic 1, the output voltages of the output buffers 233_1, 233_3 . . . corresponding to the modulation signal CNTRL1 are larger than their input voltages, that is, they are positive offset voltages. When the modulation signal CNTRL1 is Logic 0, the output voltages of the output buffers 233_1, 233_3 . . . corresponding to the modulation signal CNTRL1 are smaller than their input voltages, that is, they are negative offset voltages. Likewise, when the modulation signal CNTRL2 is Logic 1, the output voltages of the output buffers 233_2, 233_4 . . . are larger than their input voltages, that is, they are positive offset voltages. When the modulation signal CNTRL1 is Logic 0, the output voltages of the output buffers 233_2, 233_4 . . . are smaller than their input voltages, that is, they are negative offset voltages.
FIG. 3B is a voltage-to-time diagram of an ideal output waveform 301 and an actual output waveform 302 of the output buffer 233_1. When the frame F31 is displayed, the voltage of the ideal output waveform 301 is VP2, the voltage of the actual output waveform 302 is V21, and thus the offset voltage is V21−VP2=ΔV. When the frame F32 is displayed, the voltage of the ideal output waveform 301 is VN2, the voltage of the actual output waveform 302 is V23, and thus the offset voltage is V23−VN2=ΔV. When the frame F33 is displayed, the offset voltages is V22−VP2=−ΔV. When the frame F34 is displayed, the offset voltage is V24−VN2=−ΔV.
FIG. 3C is a voltage-to-time diagram of an ideal output waveform 303 and an actual output waveform 304 of the output buffer 233_2. When the frame F31 is displayed, the offset voltage is V34−VN3=−ΔV. When the frame F32 is displayed, the offset voltage is V32−VP3=−ΔV. When the frame F33 is displayed, the offset voltage is V33−VN3=ΔV. When the frame F34 is displayed, the offset voltage is V31−VP3=ΔV.
FIG. 3D is an offset voltage distribution diagram of the frames F31˜F34 according to an embodiment to the present invention. In FIG. 3D, the positive/negative offset voltages are distributed in a column interlaced manner. The present embodiment adopts the modulation signals CNTRL1 and CNTRL2 generated by the modulation signal generator 234 in FIG. 2C. The modulation signal generator 234 provides the modulation signal CNTRL1 to the output buffers 233_1, 233_3 . . . at the odd output ends and provides the modulation signal CNTRL2 to the output buffers 233_2, 233_4 . . . at the even output ends. When the frames F31 and F32 are output, the modulation signal CNTRL1 is Logic 1 and the modulation signal CNTRL2 is Logic 0. When the frames F33 and F34 are output, the modulation signal CNTRL1 is Logic 0 and the modulation signal CNTRL2 is Logic 1. The odd columns of the frames F31 and F32 are ΔV, and the even columns are −ΔV. The effect of the offset voltages on the display quality can be eliminated by uniformly distributing the offset voltages in the space. The odd columns of the frames F33 and F34 are −ΔV, and the even columns are ΔV. The effect of the offset voltages on the display quality can also be eliminated by uniformly distributing the offset voltages in the space. Other frames can be deduced likewise according to the same cycle of every four frames.
FIG. 4 is an offset voltage distribution diagram of frames F41˜F44 according to another embodiment of the present invention. In FIG. 4, the positive/negative offset voltages are distributed in a column/row interlaced checkerboard manner. In the present embodiment, the modulation signals CNTRL1 and CNTRL2 generated by the modulation signal generator 234 in FIG. 2C are changed. When the odd scan lines of the frames F41, F42 and the even scan lines of the frames F43, F44 are output, the modulation signal CNTRL1 at the odd output ends is Logic 1 while the modulation signal CNTRL2 at the even output ends is Logic 0. When the even scan lines of the frames F41, F42 and the odd scan lines of the frames F43, F44 are output, the modulation signal CNTRL1 at the odd output ends is Logic 0 while the modulation signal CNTRL2 at the even output ends is Logic 1. Here, the states of the modulation signals CNTRL1 and CNTRL2 are not only changed according to the aforementioned activating signal, but also changed according to the horizontal synchronous signal. When the frame F41 is displayed, the first row is ΔV, −ΔV, ΔV, −ΔV, ΔV, −ΔV, the second row is −ΔV, ΔV, −ΔV, ΔV, −ΔV, ΔV, the third row and the following rows can be deduced likewise. The uniform distribution of the offset voltages ΔV and −ΔV of the frame F41 can compensate the effect of the offset voltages on the display quality. The distributions of the frames F42 and F41 are the same. When the frame F43 is displayed, the first row is −ΔV, ΔV, −ΔV, ΔV, −ΔV, ΔV, the second row is ΔV, −ΔV, ΔV, −ΔV, ΔV, −ΔV, the third row and the following rows can be deduced likewise. The uniform distribution of the offset voltages ΔV and −ΔV of the frame F43 can compensate the effect of the offset voltages on the display quality. The distributions of the frames F44 and F43 are the same. Other frames can be deduced likewise according to the same cycle of every four frames.
FIG. 5 is an offset voltage distribution diagram of frames F51˜F54 according to another embodiment of the present invention. In FIG. 5, the positive/negative offset voltages are distributed in a row interlaced manner. In the present embodiment, the modulation signals CNTRL1 and CNTRL2 generated by the modulation signal generator 234 in FIG. 2C are changed. When the odd scan lines of the frames F51, F52 and the even scan lines of the frames F53, F54 are output, the modulation signal CNTRL1 at the odd output ends and the modulation signal CNTRL2 at the even output ends are all Logic 1. When the even scan lines of the frames F51, F52 and the odd scan lines of the frames F53, F54 are output, the modulation signal CNTRL1 at the odd output ends and the modulation signal CNTRL2 at the even output ends are all Logic 0. The present embodiment differs from the above embodiment in that the modulation signals CNTRL1 and CNTRL2 are identical and the states thereof are changed according to the horizontal synchronous signal. When the frame F51 is displayed, the odd rows are all ΔV and the even rows are all −ΔV. The uniform distribution of the offset voltages ΔV and −ΔV of the frame F51 can compensate the effect of the offset voltages on the display quality. The distributions of the frames F52 and F51 are the same. When the frame F53 is displayed, the odd rows are all −ΔV and the even rows are all ΔV. The uniform distribution of the offset voltages ΔV and −ΔV of the frame F53 can compensate the effect of the offset voltages on the display quality. The distributions of the frames F54 and F53 are the same. Other frames can be deduced likewise according to the same cycle of every four frames.
FIG. 6 is an offset voltage distribution diagram of frames F61˜F64 according to another embodiment of the present invention. Different from the column interlaced manner in FIG. 3D, the checkerboard manner in FIG. 4 and the row interlaced manner in FIG. 5, FIG. 6 is of an asymmetrical interlaced manner. The pixels of the frames F61˜F64 in FIG. 6 have two offset voltages, and the numbers of the pixels having the two offset voltages in each of the frames F61˜F64 are almost the same. In the present embodiment, the modulation signals CNTRL1 and CNTRL2 generated by the modulation signal generator 234 in FIG. 2C are changed. When a portion of the pixels of a frame is output, the modulation signal received by the output buffer for outputting the portion of the pixels is Logic 1. When the other portion of the pixels of the same frame is output, the modulation signal received by the output buffer for outputting the other portion of the pixels is Logic 0. In particular, when the scan lines 1, 4, 5 of the frames F61, F62 and the scan lines 2, 3, 6, 7 of the frames F63, F64 are output, the modulation signal CNTRL1 at the odd output ends is Logic 1 while the modulation signal CNTRL2 at the even output ends is Logic 0. When the scan lines 2, 3, 6, 7 of the frames F61, F62 and the scan lines 1, 4, 5 of the frames F63, F64 are output, the modulation signal CNTRL1 at the odd output ends is Logic 0 while the modulation signal CNTRL2 at the even output ends is Logic 1. In the present embodiment, the modulation signals CNTRL1 and CNTRL2 are different and the states thereof are changed according to the horizontal synchronous signal. When the frame F61 is displayed, the first, fourth and fifth rows are all ΔV, −ΔV, ΔV, −ΔV, ΔV, −ΔV, and the second, third, sixth and seventh rows are all −ΔV, ΔV, −ΔV, ΔV, −ΔV, ΔV. The uniform distribution of the offset voltages ΔV and −ΔV of the frame F61 can compensate the effect of the offset voltages on the display quality. The distributions of the frames F62 and F61 are the same. When the frame F63 is displayed, the first, fourth and fifth rows are all −ΔV, ΔV, −ΔV, ΔV, −ΔV, ΔV, and the second, third, sixth and seventh rows are all ΔV, −ΔV, ΔV, −ΔV, ΔV, −ΔV. The uniform distribution of the offset voltages ΔV and −ΔV of the frame F63 can compensate the effect of the offset voltages on the display quality. The distributions of the frames F64 and F63 are the same. Other frames can be deduced likewise according to the same cycle of every four frames. In the present embodiment, the distributions of the frames 61 and 62 are the same, and the distributions of the frames 63 and 64 are the same. It should be apparent to those skilled in the art that each frame can have a different distribution manner, instead of being limited to the manner in the embodiment, so as to compensate the effect of the offset voltages on the frame quality by uniformly distributing the positive/negative offset voltages on a frame.
In the above embodiments, if the output buffer receives a modulation signal of Logic 1, it outputs a positive offset voltage, and if the output buffer receives a modulation signal of Logic 0, it outputs a negative offset voltage. In other embodiments of the present invention, the corresponding relation can be opposite, i.e., if the output buffer receives a modulation signal of Logic 0, it outputs a positive offset voltage, and if the output buffer receives a modulation signal of Logic 1, it outputs a negative offset voltage.
The present invention not only provides a driving device in the above embodiments, but also provides a TFT liquid crystal display panel driving method. The technical details of the method have been disclosed in the aforementioned embodiments, and thus will not be described herein.
In view of the above, for different pixels of a frame in the present invention, the effect of the offset voltages on the display quality is eliminated by means of space modulation according to various distribution manners, and no capacitor is needed to store the offset voltages, thus saving circuit elements, preventing the frame flickering phenomenon and improving the display quality.
Though the present invention has been disclosed above by the preferred embodiments, they are not intended to limit the present invention. Anybody skilled in the art can make some modifications and variations without departing from the spirit and scope of the invention. Therefore, the protecting range of the present invention falls in the appended claims.