Patent Application
20080068364
The above and other features of the exemplary embodiments of the present invention will he described in detail with reference to the accompanying drawings, in which:
Exemplary embodiments of the present invention are described below with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the drawings, the size and relative sizes of layers and regions may not be drawn to scale.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. Like numbers may refer to like elements throughout.
Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
Referring to
The gate line patterns 121, 124, and 129 are extended in a first direction. The gate line patterns 121, 124, and 129 include a gate electrode 124. Each of the gate line patterns 121, 124, and 129 has a terminal having a widened width for connecting to an external circuit.
A storage electrode line 131 is formed on the insulating substrate 110. The storage electrode line 131 is extended in the first direction. However, the storage electrode line 131 may have a partially curved portion. A terminal 135 of the storage electrode line 131 has a widened width for connecting to a storage electrode line 131 formed in another pixel. A plurality of storage electrode lines 131 formed in each pixel is connected to a vertical storage line connection bar 91, described below.
The storage electrode line 131 includes a first attaching metal pattern 311 and a first wiring metal pattern 312 formed on the first attaching metal pattern 311. The first attaching metal pattern 311 strengthen an attachment of the first wiring metal pattern 312 to the insulating substrate 110.
A display area is defined as an area in which a pixel corresponding to a pixel electrode 190 is disposed. A peripheral area is defined as an area in which a driving circuit for applying a signal to the display area is formed. The vertical storage line connection bar 91 is formed in the peripheral area in which the terminal 135 of the storage electrode line 131 is disposed. The vertical storage line connection bar 91 may be simultaneously formed with a data line 171. The vertical storage line connection bar 91 is extended in a second direction substantially perpendicular to the first direction. The data line 171 is substantially parallel to the vertical storage line connection bar 91. The vertical storage line connection bar 91 and the terminal 135 of the storage electrode line 131 are connected to each other by a storage contact assistance member 99 including a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc.
The gate line patterns 121, 124, and 129 and the storage electrode line 131 include aluminum (Al), aluminum alloy, silver (Ag), silver alloy, copper (Cu), copper alloy, chromium (Cr), titanium (Ti), tantalum (Ta), and/or molybdenum (Mo), etc. The first attaching metal patterns 211, 241, and 291 may include chromium (Cr), molybdenum (Mo), titanium (Ti), and/or tantalum (Ta), etc., having excellent mechanical and chemical properties. The wiring metal patterns 212, 242, and 292 may include aluminum (Al), silver (Ag), and/or copper (Cu), etc, having a low resistivity. Alternatively, the gate line 121 and the storage electrode line 131 may include various kinds of metal and/or another conductive material.
According to an exemplary embodiment of the present invention, the first attaching metal patterns 211, 241, and 291 include, for example, chromium (Cr). The first wiring metal patterns 212, 242, and 292 include, for example, aluminum (Al). When the first wiring metal patterns 212, 242, and 292 including aluminum (Al) is connected to the storage contact assistance member 99 including indium tin oxide (ITO), a contact property between aluminum and ITO may be lowered. Therefore, a terminal of the first wiring metal patterns 212, 242, and 292 including aluminum (Al) is etched such that the first attaching metal patterns 211, 241, and 291 including chromium (Cr) is exposed. Thus, the first attaching metal patterns 211, 241, and 291 including chromium (Cr) is connected to the vertical storage line connection bar 91 including ITO by the storage contact assistance member 99.
A gate insulating film 140 is formed on the transparent insulating substrate 110 having the gate line patterns 121, 124, and 129 and the storage electrode lines 131 and terminal 135 of the storage electrode line 131 formed thereon.
Semiconductor layers 151, 154, and 159 and ohmic contact layers 161, 163, 165, and 169 are formed on the gate insulating film 140 corresponding to the gate electrode 124. The semiconductor layers 151, 154, and 159 include semiconductor material, such as amorphous silicon. The ohmic contact layers 161, 163, 165, and 169 include semiconductor material, such as the amorphous silicon doped with an n-typed impurity at high concentration.
Data line patterns 171, 173, 175, 177, and 179 are formed on the ohmic contact layers 161, 163, 165, and 169 and the gate insulating film 140. The data line patterns 171, 173, 175, 177, and 179 are substantially perpendicular to the gate line 121. The data line patterns 171, 173, 175, 177, and 179 and the gate line 121 define a plurality of pixel areas. The data line patterns 171, 173, 175, 177, and 179 include a source electrode 173, which is a portion of the data line 171, connected to the ohmic contact layer 163 and a drain electrode 175 spaced apart from the source electrode 173 and being formed on a ohmic contact layer 165 disposed in the opposite side of the source electrode 173 with respect to the gate electrode 124. A terminal 179 of the data line has a widened width for connecting to an external circuit. A storage capacitive electrode 177 overlapping the gate line 121 may be formed and the storage capacitance may be improved.
A first pixel is adjacent to the peripheral area and is formed in a left side of the display area. A dummy data line 1711 is formed between the first pixel and the peripheral area. The dummy data line 1711 is insulated from the gate line 121 and crosses the gate line 121. The dummy data line 1711 and the gate line 121 define a dummy pixel 1900. The dummy pixel 1900 has substantially the same shape as each of the pixels formed in the display area. For example, the dummy pixel 1900 includes the gate line 121, the dummy data line 1711, and a dummy pixel electrode formed in the peripheral area. The dummy pixel 1900 further includes a plurality of dummy thin film transistors formed in the peripheral area. The dummy thin film transistors are connected to the gate line 121, the dummy data line 1711, and the dummy pixel electrode.
A width of the dummy pixel 1900 is smaller than that of each pixel formed in the display area. A conventional TFT substrate does not include the dummy pixel. However, exemplary embodiments of the present invention include the dummy pixel. The width of the dummy pixel may be smaller than that of the pixel formed in the display to allow for a space in which the dummy pixel may be formed.
The dummy pixel 1900 and the dummy data line 1711 are formed in a left side of the display area in
A storage capacitive electrode formed in a first pixel row of the display area may be larger than storage capacitive electrodes formed in the display area, which are not included in the first pixel row. The first pixel row may therefore have the same brightness as each of the other pixel rows. When the storage capacitive electrode of the first pixel row has a broad area, an aperture ratio may be reduced. Therefore, the brightness of the first pixel row is moderated by the storage capacitive electrode's ability to shield light generated by the light source (not shown) disposed under the thin film transistor substrate.
The vertical storage line connection bar 91, substantially parallel to the data line 171, is formed on the gate insulating film 140. The dummy data line 1711 of the dummy pixel is connected to the vertical storage line connection bar 91 through a horizontal storage line connection bar 92.
The data line patterns 171, 173, 175, and 179, the storage capacitive electrode 177, and the dummy data line 1711 include second attaching metal patterns 731, 751, 791, 771 and 7111 and second wiring metal patterns 732, 752, 792, 772 and 7112. The second attaching metal patterns, 731, 751, 791, and 7111 of the data line patterns 171, 173, 175, and 179 strengthen an attachment of the second wiring metal patterns 732, 752 and 792 to the ohmic contact layers 163, 165, 169 and 161. The second attaching metal patterns 731, 751, 791, 771 and 7111 and the second wiring metal patterns 732, 752, 772 and 7112 include the above-mentioned metal. The data line including two layers has been described. However, the data line may include three layers. When the data line includes three layers, a low resistive metal is disposed in a center layer. The low resistive metal includes aluminum (Al), copper (Cu), silver (Ag), etc.
The vertical storage line connection bar 91 includes multi-layers 911 and 912 such as the data line patterns 171, 173, 175, and 179. The horizontal storage line connection bar 92 also includes multiple layers (not shown).
In the present exemplary embodiment, the dummy data line 1711 is formed in an area which is to the left side of the first data line and to the right edge of the display area. The dummy data line 1711 receives a storage signal which is applied to the vertical storage line connection bar 91.
The dummy data line 1711 and a dummy pixel row connected to the dummy data line 1711 may reduce or prevent a difference between the coupling capacitance of an outer pixel row and the coupling capacitance of the other pixel rows.
A portion of the TFT panel where the storage contact assistance member 99 makes contact, with chromium (Cr), for example at a stacking fault, may be undercut. Accordingly, the storage electrode line 131 may be opened and a stripe may be displayed.
The dummy data line 1711 may be used as a repair bar in order to prevent the stripe from being displayed.
For example, a portion where the storage electrode line 131 and the dummy data line 1711 overlaps each other is irradiated with a laser beam to remove the gate insulating film between the storage electrode line 131 and the dummy data line 1711 when a voltage potential is to be applied to the storage electrode line 131 through the dummy data line 1711. As a result, the storage electrode line 131 is connected to the dummy data line 1711. Therefore, even though the undercut portion of the storage electrode line 131 is opened by static electricity or an overcurrent, the open storage electrode line 131 may be repaired.
An overcoat film 180 is formed on the transparent insulating substrate 110. The overcoat film includes a first contact hole 181 exposing the drain electrode 175, a second contact hole 182 exposing a terminal 129 of the gate line, a third contact hole 183 exposing a terminal 179 of the data line, and a fourth contact hole 184 exposing the storage capacitive electrode 177. The overcoat film 180 further includes a fifth contact hole 185 exposing a terminal (not shown) of the storage electrode line.
A pixel electrode 190, a gate contact assistance member 95, and a data contact assistance member 97 are formed on the overcoat film 180. The pixel electrode 190 is connected to the drain electrode 175 through the first contact hole 181. The pixel electrode 190 is also connected to the storage capacitive electrode 177 through the fourth contact holes 184. The gate contact assistance member 95 is connected to the terminal 129 of the gate line through the second contact hole 182. The data contact assistance member 97 is connected to the terminal 179 of the data line through the third contact hole 183. The pixel electrode 190 might not overlap the gate and data lines 121 and 171. However, the pixel electrode 190 may partially overlap the gate and data lines 121 and 171 and an aperture ratio may be increased. The pixel electrode 190 overlapping the data line 171 may increase the aperture ratio. Signal interference between the data line 171 and the pixel electrode 190 can be reduced when the overcoat film 180 includes a material having a low dielectric constant.
The storage contact assistance member 99 is formed on the overcoat film 180. The storage contact assistance member 99 connects the terminal (not shown) of the storage electrode line with the vertical storage line connection bar 91 through the fifth contact hole 185.
As shown in
In the liquid crystal display apparatus, the black matrix 220 is formed at a portion of the color filter substrate, which corresponds to the dummy pixel of the thin film transistor substrate. For example, the black matrix 220 is formed in a portion of the color filter substrate, which corresponds to the pixel electrode of the dummy pixel. Therefore, even though the storage signal is applied to the dummy pixel electrode, light is not transmitted. The dummy pixel electrode forms a coupling capacitance to the first data line. Therefore, a difference of brightness between a first pixel and the other pixels is reduced or prevented.
A dummy pixel 1900 is disposed in the peripheral area adjacent to the display area. A width of the dummy pixel is smaller than that of each pixel disposed in the display area. As shown in
A width of each of a first pixel adjacent to the dummy pixel 1900 and a pixel (not shown) disposed in a right side of the display area is smaller than that of each of the other pixels disposed in the display area.
An area of the storage capacitive electrode formed in one of the first pixel and the pixel disposed in the right side of the display area, is larger than that disposed in each of the other pixels. The storage capacitive electrode may shield light from the light source disposed under the TFT substrate. The storage capacitive electrode includes a non-transparent metal of substantially the same size as the gate line. The storage capacitive electrode may thereby reduce the aperture. Therefore, the amount of light passing through the first pixel and the pixel disposed in the right side of the display area may be reduced. A display defect may cause the first pixel and the pixel disposed in the right side of the display area to be brighter than the other pixels. Such a display defect may be caused by virtue of the first pixel and the pixel disposed in the right side of the display area being disposed adjacent to the black matrix. According to an exemplary embodiment of the present invention, the display defect may be partially or fully corrected for by changing the area of the storage capacitive electrode.
As described above, a coupling capacitance is generated in the first pixel row and a pixel row disposed at a right side of the display area. The coupling capacitance is substantially the same as that of the other pixel when the dummy pixel 1900 and the dummy data line 1711 are formed on the TFT substrate. Therefore, the situation where the outer pixels appear brighter than the other pixels may be reduced or prevented because the coupling capacitance is not generated in the outer pixel.
When an area of the storage capacitive electrode formed in the first pixel row is larger than that formed in the other pixel as shown in
The dummy data line 1711 shown in
The TFT panel according to an exemplary embodiment of the present invention includes a dummy data line formed between the peripheral area and the outer data line formed adjacent to the peripheral area. The TFT panel may reduce or prevent a brightness difference between pixels caused by a difference of coupling capacitance between the data line adjacent to the peripheral area and the other data lines.
When the TFT panel has a shortened storage electrode line, this defect may be repaired by the dummy data line.
While the present disclosure has been particularly shown and described with reference to exemplary embodiments of the present invention, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-88430 | Sep 2006 | KR | national |
