Patent Application
20160306244
This application claims priority to Chinese Patent Application No. 201510177213.6 filed on Apr. 15, 2015 in the China Intellectual Property Office, the contents of which are incorporated by reference herein.
The subject matter herein generally relates to a thin film transistor substrate and a display device using same.
A display device can include a thin film transistor substrate, a counter substrate, and a liquid crystal layer arranged between the thin film transistor substrate and the counter substrate. The thin film transistor substrate can include a plurality of data lines, a plurality of scanning lines, a storage capacitor, and a plurality of common lines. The plurality of common lines are arranged in a peripheral area of the thin film transistor substrate and the storage capacitor is arranged in a display area of the thin film transistor substrate. The plurality of common lines and the storage capacitor are arranged in different layers of the substrate. Each of the plurality of common lines is electrically coupled to the storage capacitor via a conductive bridge. A coupling capacitance may be generated between the conductive bridge and the common line.
Implementations of the present technology will now be described, by way of example only, with reference to the attached figures, wherein:
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features. The description is not to be considered as limiting the scope of the embodiments described herein.
Several definitions that apply throughout this disclosure will now be presented.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
Each of the common lines 114 is located in the peripheral area 102. A common line 114 can include a first common line 1141 and a second common line 1142 located in the base 115. The first common line 1141 surrounds the display area 101. The second common line 1142 is located between the first common line 1141 and an edge of the base 115. The second common line 1142 forms a semi-closed rectangle having an opening which faces the data driver 15. The first common line 1141 can be an enclosed rectangle. The storage capacitor line 110 is directly electrically coupled to the first common line 1141. In the illustrated embodiment, ends of each storage capacitor line 110 extend to connect to the first common line 1141.
Further Referring to
The thin film transistor substrate 11 can further include a passivation layer 118 and the common electrode layer 119. The passivation layer 118 covers the thin film transistor 113 and the second common line 1142. The common electrode layer 119 is located on the passivation layer 118 and covers the passivation layer 118. In the embodiment, the pixel electrode 117 and the common electrode layer 119 are made of the same material, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
The first common line 1141 is located between the gate insulating layer 1132 and the base 115. The first common line 1141 and the gate electrode 1131 are both located in a same layer and can be made in a same manufacturing process. In at least one embodiment, both the first common line 1141 and the gate electrode 1131 are formed on and are in contact with a surface of the base 115 adjacent to the gate insulation layer 1132. The second common line 1142 is located between the gate insulating layer 1132 and the passivation layer 118. The passivation layer 118 can include a contact hole 1181 to expose the second common line 1142. The common electrode layer 119 is electrically coupled to the second common line 1142 via the contact hole 1181. The second common line 1142, the source electrode 1134, and the drain electrode 1135 are located in a same layer and made in a same manufacturing process. In at least one embodiment, the second common 1142, the source electrode 1134, and the drain electrode 1135 are deposited on the gate insulating layer 1132. The storage capacitor line 110 is located between the gate insulating layer 1132 and the base 115. The storage capacitor line 110, the first common line 1141, and the gate electrode 1131 are located in a same layer and made in a same manufacturing process. In at least one embodiment, the storage capacitor line 110, the first common line 1141, and the electrode 1131 are deposited on the base 115.
The thin film transistor substrate 21 can include a plurality of storage capacitor lines 210, a plurality of thin film transistors 213, a common line 214, a base 215, and a pixel electrode 217. The storage capacitor line 210, the thin film transistor 213, the common line 214, and the pixel electrode 217 are arranged on the base 215.
The thin film transistor 213 can further include a gate electrode 2131, a gate insulating layer 2132, a channel layer 2133, a source electrode 2134, and a drain electrode 2135. The gate electrode 2131 is located on the base 215. The gate insulating layer 2132 covers the gate electrode 2131 and the second base 215. The channel layer 2133 is located on the gate insulating layer 2132 corresponding to the gate electrode 2131. The source electrode 2134 and the drain electrode 2135 are arranged at opposite ends of the channel layer 2133. The pixel electrode 217 is located on the gate insulating layer 2132 and electrically coupled to the drain electrode 2135.
The thin film transistor substrate 21 can further include a passivation layer 218 and a common electrode layer 219. The passivation layer 218 is located on the base 215 to cover the gate insulating layer 2132, the channel layer 2133, the source electrode 2134, the drain electrode 2135, and the pixel electrode 217. The common electrode layer 219 is located at the counter substrate 22 adjacent to the liquid crystal layer 23.
The common line 214 can include a first common line 2141 and a second common line 2142. The first common line 2141 and the second common line 2142 are located at the base 215. The first common line 2141 is located between the gate insulating layer 2132 and the base 215. The first common line 2141 and the gate electrode 2131 are located in a same layer and can be made in a same manufacturing process. In one or more embodiment, the first common line 2141 and the gate electrode 2131 are formed on and are in contact with a surface of the base 215 adjacent to the gate insulation layer 2132. The second common line 2142 is located between the gate insulating layer 2132 and the passivation layer 218. The passivation layer 218 can include a contact hole 2181 to expose the second common line 2142. The common electrode layer 219 is electrically coupled to the second common line 2142 via the contact hole 2181. The second common line 2142, the source electrode 2134, and the drain electrode 2135 are located in a same layer and made in a same manufacturing process. In one or more embodiment, the second common line 2142, the source electrode 2134, and the drain electrode 2135 are deposited on the gate insulating layer 2132. The storage capacitor line 210 is located between the gate insulating layer 2132 and the base 215. The storage capacitor line 210, the first common line 2141, and the gate electrode 2131 are located in a same layer and made in a same manufacturing process. In one or more embodiment, the storage capacitor line 210, the first common line 2141, and the electrode 2131 are deposited on the base 215.
The sealant 24 can include conductive particles 241 corresponding to the contact hole 2181. The second common line 2142 is electrically coupled to the common electrode layer 219 via the conductive particles 241.
The first common line and the storage capacitor are located in a same layer, thus a conductive bridge between the first common line and the storage capacitor is not required, and the formation of a coupling capacitance is rendered less likely.
It is to be understood that even though numerous characteristics and advantages of the present embodiments have been set forth in the foregoing description, with details of the structures and functions of the embodiments, the disclosure is illustrative only; and changes may be in detail, especially in the matter of arrangement of parts within the principles of the embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201510177213.6 | Apr 2015 | CN | national |
