Patent Application
20080265257
Substrates provide a substantially flat surface on which to grow or form active devices for decoding arrays of electrically activated elements used to display information and media. Substrates often provide mechanical strength to such displays but can also be flexible. Substrates are usually electrically non-conductive and may vary in thickness depending on the mechanical strength needed and the cost targeted in manufacturing. Processes build active devices by forming layers of semiconductor materials and conductive interconnects on top of each other on the substrate. Usually at least two conductive layers and a via interconnect on a substrate have been needed for building and interconnecting transistor logic devices to implement cross-overs between the semiconductor source/drain interconnect and the gate interconnect. However, optimizing substrate area usually requires adding additional layers and vias above the two layers needed for active devices. Additional layers and vias add considerably to the cost of processing an end product and are therefore less desirable in low-cost products.
Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Alterations and further modifications of the inventive features illustrated herein, and additional applications of the principles of the inventions as illustrated herein, which would occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the invention.
An embodiment of a thin film transistor (TFT) configured to be used in a bi-stable display, has a substrate with a first side and second side configured to be used with the bi-stable material in the bi-stable display. A source and a drain are formed on the first side of the substrate in contact with a semiconductor material between a source connection and the drain connection. A gate is formed on a second side of the substrate opposite the semiconductor material.
A double-sided thin film transistor reduces conductor cross-over by allowing gate routing on a substrate side to be completely independent of the source-drain routing on the other side. The conductor materials may include nickel, aluminum, and indium-tin-oxide (ITO) and the like. A double-sided transistor implementation of the decoder pass transistor logic enables a cost reduction by using a single layer interconnect and also allows an area reduction in interconnect. Therefore, the active thin film transistor decoder implemented in double sided pass gates provides a high performance, low cost advantage for addressing bi-stable displays.
A gate 40 is formed for a second side 20 of the substrate 10 opposite the semiconductor material 35. Gates that are self-aligned to source drain geometries in an embodiment contribute to greater gain for the thin film transistor. The substrate 10 provides an insulator between the gate 40 and the semiconductor material 35. The substrate materials may include polyimide (e.g. kapton), polyetheretherketone (PEEK), polyethersulfone (PES), polyetherimide (PEI), polyethylenenaphthalate (PEN) and the like.
The gate insulator thickness can be controlled by an embossing process or a laser ablation process or both in a further embodiment. In the depicted embodiment, the gate is recessed into an area that has been ablated by a laser or some other substrate removal process. However, the gate may be formed on the second side of the substrate without removing any of the substrate.
Decoders allow activation of single electrically activated elements. Decoding an array is usually accomplished by breaking up the array into column and row addresses and generating true and complement signals for each row and each column address. Therefore decoders may also have the ability to electrically activate entire rows or entire columns in an array at any given instant or simultaneously through multiple decoders. Decoders typically take up a significant amount of area contiguous to an array of electrically activated elements. It is therefore desirable to optimize the area consumed by decoding row and column addresses as well as to minimizing the number of inputs into a decoder. In addition to minimizing the area in a decoder there is also a desire to minimize the number of layers or masks needed to build the decoder. Two conductive layers has generally been the limit on how cheaply a decoder could be implemented because at least two layers and a via interconnect have been needed to implement cross-overs between rows and columns in the array itself. Also where a decoder and an array are built in the same process it is more cost effective to match the number of layers in the decoder with the number of layers in the array.
In a decoder embodiment, a semiconductor formed on the first side is aligned to an opposing gate on the second side. Source and drain interconnections formed on the first side are formed entirely in one conductive layer. Also the gate control lines formed on the second side are formed entirely in one conductive layer. Pass transistors are implemented with double sided transistors where a gate on the second side and a semiconductor on the first side allow source and drain connections entirely on the first side of the substrate insulator. Furthermore, in an embodiment, the decoder is implemented in pass transistors of one type fabricated in materials and processes of one type.
An embodiment of the decoder further comprises a first set of pass transistors connected to a first input and a second set of pass transistors connected to a second input, wherein the second input is channeled to an output mutually exclusive of the first input. Furthermore, control signals for the first and second set of pass transistors are logical complements of each other. Implementing the active thin film transistor decoder in pass transistors allows the gate to source voltage difference to be used as way to control voltage levels seen at the output of the decoder into the pixel electrode array.
The voltage difference applied across pixel element Clc00 is a plus or minus 40 volts as a result of an alternating +20 volts and −20 volts applied through Sel1 and an alternating +20 volts and −20 volts applied on Dat1. The voltage difference applied across pixel element Clc10 is a plus or minus 20 volts as a result of an alternating +20 volts and −20 volts applied through Dat1 and 0 volts applied on Sel2. Accordingly the voltage difference across Clc01 is a plus or minus 30 volts, and the voltage difference across Clc11 is a plus or minus 10 volts. Dat3 is at 0 volts and Sel2 is also at 0 volts so the voltage difference across Clc12 is 0 volts. The voltage across Clc02 is similar to that across Clc10.
A data line Dat1, Dat2, or Dat3 on the second side of the substrate may provide a voltage on a column of pixel elements in a pixel array. A select line Sel1 or Sel2 on the first side of the substrate may provide a voltage on a row of pixel elements in a pixel array. The voltage difference across a pixel element between a select line Sel1 or Sel2 and a data line Dat1, Dat2, or Dat3 may activate a pixel element when it is above the pixel element threshold.
Decoding ambiguous addresses allows time multiplexing of multiple voltage sources to rows or columns of pixel electrodes. In other words, the voltage source is presented to an electrode as a transistor driver source that is switched through the decoder circuitry. Vselect may be present on a particular electrode at one point in time through the decoder and at another point in time Vunselect may be presented on that same electrode through the decoder. Ambiguous addressing allows addressing larger arrays of electronically controlled elements than would be possible with unambiguous addressing. Thus, the voltage difference across a pixel element needed to activate that element can be controlled by multiple sources. The thin film transistor double-sided decoder allows an ambiguous address to be presented on one side of a substrate while the voltages needed to unambiguously activate a row or column in an array are presented on the other side of the substrate.
In an alternative embodiment, a method can use multiple thin film double-sided transistor decoders. The embodied method includes the step of decoding a plurality of voltage supplies of alternating positive and negative polarities onto a first electrode of a pixel element. Additionally, decoding a voltage supply with alternating positive and negative polarities onto the second electrode of the pixel element rather than directly applying a voltage supply to the second electrode is further included. Synchronizing voltage polarity cycles of the decoded voltage and the applied voltages, applies a pre-determined voltage difference across a first electrode to a second electrode. Pixel elements are activated having an applied voltage above the pixel element activation threshold. The multiple voltage supplies may include static sources of various voltage levels including a source having a mean voltage of the alternating positive and negative polarities.
It is to be understood that the above-referenced arrangements are only illustrative of the application for the principles of the present invention. Numerous modifications and alternative arrangements can be devised without departing from the spirit and scope of the present invention. While the present invention has been shown in the drawings and fully described above with particularity and detail in connection with what is presently deemed to be the most practical and preferred embodiment(s) of the invention, it will be apparent to those of ordinary skill in the art that numerous modifications can be made without departing from the principles and concepts of the invention as set forth herein.
