Thread cancellation and recirculation in a computer processor for avoiding pipeline stalls

Abstract

The present invention provides a computer pipeline control mechanism enabling a nonstalling pipeline despite the presence of pipeline hazards. The present invention detects the presence of predetermined pipeline hazard conditions, cancels the thread which contains the instruction encountering such pipeline hazard and then recirculates the program counter of the instruction having hazards for re-execution. The present invention guarantees the deterministic execution of threads in a computer pipeline.

Description

RELATED APPLICATIONS

This application is related to the U.S. patent application Ser. No. 09/888,296, titled “System And Method For Reading And Writing A Thread State In A Multithreaded Central Processing Unit,” filed on Jun. 22, 2001, which is incorporated by reference herein in its entirety.

BACKGROUND OF INVENTION

1. Field of the Invention

This invention relates generally to computer processor pipeline control, and more particularly, to a system and method for controlling the pipeline of a multithreaded computer processor to ensure that deterministic execution of the threads is not affected by pipeline hazards.

2. Description of the Related Art

In a pipelined computer processor, pipeline hazards may reduce the performance of software codes. A typical cause of a pipeline hazard is that an instruction needs to use a result that is not yet available from a preceding instruction that is concurrently executed in the same pipeline. In a single-threaded pipeline, a conventional method of resolving the pipeline hazard is to stall the pipeline at the stage holding the instruction until the preceding instruction completes execution and the result is available.

However, this method, if used in a multi-threaded pipeline processor, can affect the real-time performance of other threads in the pipeline. In one application, a pipelined computer processor schedules the execution of two types of threads: hard-real-time (HRT) threads and non-real-time (NRT) threads. HRT threads require that a minimum number of instructions be executed per second to satisfy hard timing requirements, which may be imposed by standards such as IEEE 802.3 (Ethernet), USB, HomePNA 1.1 or SPI (Serial Peripheral Interface). NRT threads are programmed to perform those tasks having no hard timing requirements. Therefore, they can be scheduled in any clock cycle where there are no HRT threads actively running. Since the allocation of execution time for each HRT thread is set and the time required to execute each HRT thread is known, the deterministic performance of HRT threads is affected when the pipeline is stalled to remove the hazard.

Another method of resolving a pipeline hazard is to delay the instruction that encounters a hazard, and to allow other instructions to complete execution before the delayed instruction. However, this method requires complex and costly hardware to implement.

Accordingly, what is needed is a pipeline control mechanism to cope with pipeline hazard in a pipelined computer processor, for example, a multithreaded processor, to ensure deterministic execution of multiple threads. The pipeline control mechanism should also be easy and less expensive to implement than conventional systems.

SUMMARY OF INVENTION

The present invention is a pipeline control mechanism that maintains deterministic execution of multiple threads in a computer processor pipeline. In one embodiment, the present invention provides a nonstalling computer pipeline that does not delay the execution of threads that do not encounter pipeline hazards. When an instruction of a thread encounters a hazard condition, the instruction as well as other instructions in the pipeline belonging to the same thread is annulled. The cancelled instruction's program counter is recirculated to the fetching stage of the pipeline so that the instruction can be later rescheduled and retried for execution.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an embedded processor according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a RISC core having a recirculating and nonstalling pipeline.

FIG. 3 illustrates a method for controlling a processor pipeline according to one embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to several embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever practicable, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

The features and advantages described in the specification are not all inclusive, and particularly, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims hereof. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter, resort to the claims being necessary to determine such inventive subject matter.

FIG. 1 illustrates an embedded processor 100 according to one embodiment of the present invention. The embedded processor 100 is typically a processor that is used for specific functions, and may have some memory and peripheral functions integrated on-chip. As shown in FIG. 1, the embedded processor 100 includes a RISC CPU core 101 and an instruction memory 103. In addition, the embedded processor 100 can include peripheral blocks, such as a phase locked loop (PLL) 107 or a watchdog timer 109, and input/output (IO) support logic 111, e.g., virtual peripheral support logic. The embedded processor 100 has a pipelined architecture that is capable of executing multiple program threads, as described below.

The CPU core 101 is coupled to the instruction memory 103 through a signal line 106. In one implementation, the instruction memory 103 is a conventional flash memory device. The CPU core 101 can fetch instructions from the flash memory device without experiencing wait-states and without stalling the instruction pipeline. In an alternative embodiment, the instruction memory 103 may also include a conventional SRAM (static RAM) device. Accessing data, e.g., instructions, from SRAM is significantly faster than accessing the same data or instruction from a flash memory device.

In one embodiment, the embedded processor 100 executes multiple instructions from multiple threads in its pipeline simultaneously, each at a different stage. The appearance of concurrent execution of multiple threads is achieved by time-division multiplexing of the processor pipeline between the available threads. The details of conventional computer pipeline processing are known to persons of ordinary skill in the art.

In one preferred embodiment, the embedded processor 100 provides a pipeline control mechanism to guarantee a deterministic execution of threads even though software programmers may not be aware of the impacts of pipeline hazards upon the compiled software threads. As will be described below in detail with reference to FIG. 3, the embedded processor 100 detects if an instruction of a thread encounters a pipeline hazard. Upon the presence of pipeline hazard, the embedded processor 100 can cancel the execution of the instruction encountering the hazard and later instructions in the same thread in the pipeline. The embedded processor 100 will later reschedule execution of the canceled instructions. By doing so, the pipeline operation of the embedded processor 100 will not be stalled and the timing requirements of executing other threads in the pipeline will not be impacted by the hazard.

FIG. 2 illustrates a pipelined CPU core 101 according to an embodiment of the present invention. FIG. 2 shows a pipeline 200 running in the CPU core 101 with a plurality of pipeline stages, such as an instruction fetching stage 205, a decoding stage 207, an operand fetching stage 209, an execution stage 211 and a writeback stage 213.

Each stage of the pipeline 200 can be implemented through various hardware, perhaps with associated firmware. For ease of illustration, the pipeline 200 is fairly simple. In alternate embodiments, the pipeline 200 may be longer. For example, in one alternate embodiment, the pipeline 200 includes two stages for each of the fetch, decode, operand fetch, and writeback stages.

The CPU core 101 includes a scheduler 215, a thread cancellation module 201, a program counter recirculation module 202 and a hazard detection module 203. The hazard detection module 203 is coupled to hardware that is used in each pipeline stage 205-213. The thread cancellation module 201 is also coupled to the hardware that is used in each pipeline stage and is coupled to the hazard detection module 203 through a signal line 240. The recirculation module 202 is coupled to the hazard detection module 203 through a signal line 242.

In one embodiment, the scheduler 215 includes a scheduling table where the schedule of HRT threads and NRT threads are provided to fetch corresponding instructions from the instruction memory 103. The scheduler 215 may use a pointer to control which thread is fetched from the instruction memory 103 into the pipeline 200 at the instruction fetch stage 205. In one embodiment, each thread is associated with an independent program counter. The program counter contains identification information for the thread and the address of an instruction in the instruction memory 103 from which the instruction is to be fetched in the next clock cycle and scheduled for that thread. Each time the scheduler 215 instructs to fetch an instruction belonging to a particular thread, the scheduler 215 then obtains a program counter and sends it to the hardware of the CPU core 101 at the fetching stage 205. Additional details about multi-threaded scheduling is set forth in U.S. patent application Ser. No. 09/888,296 that is incorporated by reference herein in its entirety.

After the CPU core 101 fetches an instruction by using a program counter for a particular thread, the program counter value and the thread identification number are kept and saved in registers associated with the instruction while the instruction continues to be processed in different stages of the pipeline 200. As an instruction progresses through the pipeline its program counter and thread identification number are moved or associated with each succeeding pipeline stage. As shown in FIG. 2, the values of the program counters (PCs) and thread identifiers (TIDs) 216-223 correspond to each instruction being held to execute at each stage 205-212.

While the CPU core 101 processes the instructions in its pipeline 200, the hazard detection module 203 monitors each stage of the pipeline 200 and detects whether any instruction encounters a hazard. If the hazard detection module 203 detects the presence of a hazard, it sends a hazard detection signal to the thread cancellation module 201 and the recirculation module 202 via the signal line 240 and 241 respectively. This hazard detection signal includes the pipeline stage and thread identification number, or the program counter value of the instruction or any other information to identify the instruction encountering the hazard and the related instructions. The thread cancellation module 201 then uses this signal to annul the instructions of the thread in the pipeline 200. The cancellation of the instruction having a hazard and all subsequent instructions in the same thread in the pipeline avoids the need for pipeline stalling. As a result, other threads, including HRT threads that are concurrently executed in the pipeline 200, are not affected by the pipeline hazard.

In addition, the recirculation module 202 receives the program counter value of the instruction that encountered the hazard and forwards it to the scheduler 215. The scheduler 215 reschedules the execution of the cancelled instructions beginning with the instruction encountering the hazard.

FIG. 3 is a flow chart further illustrating a method for imposing the pipeline control according to an embodiment of the present invention.

During the operation of computer processor 100, the hazard detection module 203 detects 301 the presence of pipeline hazard at each stage of the pipeline 200. The techniques of detecting the hazard are well known in the art and may vary depending on types of the software threads. In one example, the hazard detection module 203 may determine that an instruction encounters a hazard condition if its source address is the same as the destination address of a preceding instruction of the same thread. In this scenario, since the preceding instruction may not have been completed, the current instruction cannot obtain the result from the preceding instruction to proceed, i.e., a potential pipeline hazard occurs.

Upon detecting the presence of the pipeline hazard, the hazard detection module 201 deploys a hazard resolution procedure. The hazard detection module 203 sends a hazard detection signal to the thread cancellation module 201. The thread cancellation module 201 then cancels 307 the instruction encountering the hazard and subsequent instructions in the same thread. As indicated above, the hazard detection signal may include the program counter or the pipeline stage and thread identification number associated with the instruction encountering the hazard or the thread can be determined in another manner, e.g., by checking the value stored with the PCs or the TIDs 216-223. In particular, the thread ID specifies to which thread this instruction belongs. The thread cancellation module 201 then uses the thread ID to identify all the instructions in the pipeline 200 that belong to the same thread. In one approach, the thread cancellation module 201 cancels all these instructions by sending an invalidation signal to the hardware at each pipeline stage to disable the operation of the identified instructions. For example, the operands of these instructions will not be fetched or the data to be operated by these instructions will not be latched into data registers. The result of the cancellation is to annul the thread without delaying the pipeline 200. In an alternative embodiment, the invalidation signal does not stop the execution of these instructions in the pipeline 200. Instead, the invalidation signals are used by the thread cancellation module 201 to annul the instructions by preventing the writing back of the results of such instruction during the write back stage of the pipeline 200 and results are also not used by other threads.

While the thread cancellation module 201 cancels the instructions encountering a hazard, the recirculation module 201 also receives the hazard detection signal from the hazard detection module 203 and recirculates 308 the program counter value associated with the cancelled instruction to the scheduler 215. The scheduler 215 retries the cancelled thread by using the program counter value. In one implementation, the scheduler 215 is programmed to recognize the program counter value and to refetch the instructions of the cancelled thread at a new clock cycle. The details of one scheduling process that can be used in accordance with the present invention are described in the U.S. patent application Ser. No. 09/748,098, entitled “System and Method for Instruction Level Multithreading in an Embedded Processor Using Zero-time Context Switching,” filed on Dec. 21, 2000, which is incorporated by reference in its entirety.

Accordingly, in the present invention, the real-time performance of other threads is not affected by pipeline hazards and the cancelled thread can also be re-executed. This aids in the deterministic execution of HRT threads.

The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

Claims

1. A method of controlling a computer processor for processing a first and a second thread in a pipeline, each thread having one or more sequential instructions to perform in the pipeline, the method comprising the steps of: identifying a first instruction as being part of the first thread using a thread identifier, the first instruction associated with a program counter which includes information identifying the first thread and an address of the first instruction in a memory;responsive to said first instruction encountering the presence of a pipeline hazard, retrieving the program counter associated with the first instruction, canceling the first instruction and all subsequent instructions associated with the thread identifier in the pipeline in the first thread before a subsequent instruction from the first thread is processed in the pipeline while continuing to execute instructions from another thread and identifying the second thread from a scheduling table, the scheduling table specifying a predefined temporal order in which the first thread and second thread are retrieved to be processed;processing the second thread in the pipeline, wherein instructions of said first and second threads may be simultaneously processed in said pipeline; andrefetching the cancelled instructions using the program counter and the thread identifier associated with the first instruction to re-execute the cancelled instructions of the first thread in the pipeline while said second thread is processed in said pipeline.

2. The method of claim 1, wherein canceling the instruction encountering the pipeline hazard and all subsequent instructions in the pipeline belonging to the first thread, comprises the step of: andgenerating an invalidation signal for the instruction encountering the pipeline hazard and for the subsequent instructions in the pipeline belonging to the first thread.

3. The method of claim 2, wherein the invalidation signal enables an instruction to not store the result of executing the instruction.

4. The method of claim 1, wherein the processing of the second thread continues uninterrupted while the first instruction is cancelled.

5. The method of claim 1, wherein the processing of the second thread is not impacted by the presence of a pipeline hazard in the first thread.

6. The method of claim 2, wherein the invalidation signal annuls the instruction encountering the pipeline hazard and the subsequent instructions in the pipeline belonging to the first thread.

7. The method of claim 2, further comprising sending the invalidation signal to a plurality of pipeline stages in the pipeline.

8. A pipeline computer processor, comprising: a memory, for storing instructions multiple software threads to be executed, each thread comprising a plurality of sequential instructions, each instruction associated with a program counter value which includes information identifying a thread associated with an instruction and an address of the instruction in the memory; anda processing unit, coupled to the memory, for processing said instructions using multiple threads in a pipeline, wherein the processing unit comprises:a scheduler for scheduling instructions to fetch, the scheduler including a scheduling table specifying a predefined temporal order in which the a plurality of threads are retrieved to be processed;a hazard detection module, detecting if an instruction encounters a predetermined pipeline hazard condition and generating a hazard detection signal in response to the presence of the pipeline hazard condition, wherein the hazard detection signal includes the program counter value of the instruction encountering the predetermined pipeline hazard condition;a thread cancellation module, coupled to the hazard detection module, for canceling the instruction encountering the hazard condition and all subsequent instructions in the same thread before a subsequent instruction in the same thread is processed while continuing to execute instructions from another thread upon receiving the hazard detection signal and for identifying a different thread for processing as the instruction encountering the hazard condition and all subsequent instructions in the same thread are canceled; anda recirculation module, coupled to the hazard detection module, for receiving the hazard detection signal and for recirculating the program counter value of the instruction encountering the predetermined pipeline hazard condition to the scheduler, wherein the recirculated program counter value is used by the scheduler to re-execute the instructions of the cancelled thread while said different thread is processed in said pipeline.

9. The computer processor of claim 8, wherein the program counter of the instruction comprises: an address of the instruction in the memory; anda thread identifier that identifies the thread to which the instruction is associated.

10. A system for controlling a computer processor for processing a first and a second thread in a pipeline, each thread having one or more sequential instructions to perform in the pipeline, the means comprising: means for identifying a first instruction as being part of the first thread using a thread identifier, the first instruction associated with a program counter which includes information identifying the first thread and an address of the first instruction in a memory;means for responsive to said first instruction encountering the presence of a pipeline hazard, retrieving the program counter associated with the first instruction, canceling the first instruction and all subsequent instructions associated with the thread identifier in the pipeline in the first thread before a subsequent instruction from the first thread is processed in the pipeline while continuing to execute instructions from another thread and identifying the second thread from a scheduling table, the scheduling table specifying a predefined temporal order in which the first thread and second thread are retrieved to be processed;means for processing the second thread in the pipeline, wherein instructions of said first and second threads may be simultaneously processed in said pipeline; andmeans for refetching the cancelled instructions using the program counter and the thread identifier associated with the first instruction to re-execute the cancelled instructions of the first thread in the pipeline while said second thread is processed in said pipeline.

11. The system of claim 10, wherein the means for processing the second thread continue uninterrupted while the first instruction is cancelled.

12. The system of claim 10, wherein the processing of the second thread is not impacted by the presence of a pipeline hazard in the first thread.

13. The system of claim 10, wherein the means for canceling the instruction encountering the pipeline hazard and all subsequent instructions in the pipeline belonging to the first thread, comprises: means for generating an invalidation signal for the instruction encountering the pipeline hazard and for the subsequent instructions in the pipeline belonging to the first thread.

14. The system of claim 13, wherein the invalidation signal enables an instruction to not store the result of executing the instruction.

15. The system of claim 13, wherein the invalidation signal annuls the instruction encountering the pipeline hazard and the subsequent instructions in the pipeline belonging to the first thread.

16. The system of claim 13, further comprising means for sending the invalidation signal to a plurality of pipeline stages in the pipeline.