This disclosure relates generally to nonvolatile memory and programmable logic array structures and operation. More particularly, this disclosure relates to a NAND based NOR flash nonvolatile memory circuit and array structure and operation and a NAND based NOR flash nonvolatile programmable logic circuit and array and operation. Even more particularly, this disclosure relates to a NAND based NOR flash nonvolatile memory circuit and array structure and operation and a NAND based NOR flash nonvolatile programmable logic circuit and array and operation formed three-dimensionally on a substrate.
Nonvolatile memory is well known in the art. The different types of nonvolatile memory cells and cell arrays include the Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memories and nonvolatile programmable logic circuits that includes the programmable logic devices (PLD) for regular “AND” and “OR” arrays and the low-resistance switch clusters for the field programmable gate array (FPGA) fast connection applications.
In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the two-dimensional NAND-based Flash Memory and Logic has become one of the more popular types of nonvolatile memory. This market requires an extremely high density that approaches 256 Gb on a single die that has a size of approximately 100 mm2. When the density-level requirement exceeds 1 Tb for instance in a Disk Drive storage with an acceptable die size and cost, the small die size of 3-dimensional Flash Memory and Logic is becoming the trend. This provides the combined advantages of the extremely high density of more than 1 Tb, extremely small silicon area, low cost, and repeated programmability and erasability. Further, the technology will allow a single low-voltage power supply voltage source of approximately 1.2V without any on-chip high current voltage boosting circuits. This allows the full integration of flash memory and flash-based combination system on chip (SOC) designs. This has a large advantage for the future mobile integrated circuit design.
There are two kinds of two-dimensional planar storage mechanisms for today's Flash Memory cell and Flash-based Logic cells. The storage structures known in the art employ a charge-retaining mechanism such as a double-polycrystalline silicon floating-gate type charge storage and a single-polycrystalline silicon charge-trapping type storage. The charge storage mechanism, as with a floating gate nonvolatile memory, the charge representing digital data is stored on a floating gate of the device. The stored charge modifies the threshold voltage of the floating gate memory cell determine that digital data stored. In a charge-trapping mechanism, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge-trapping layer between two insulating layers. The charge-trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such Silicon Nitride (SiNx).
a-1e, 2a-2b, 3, and 4 describes the structure of U.S. Pat. Nos. 7,940,573 and 7,940,574 (Masuoka, et al.). Masuoka et al. provides a 3D NOR-type nonvolatile semiconductor memory cell and array that can inject electric charge into a charge accumulation layer through the use of an FN tunnel current.
A metal layer 13 is the bit line BL that is placed on top of the three-dimensional NMOS NOR flash transistor 100 to connect to the drain N+ active diffusion layer 5. The bit line BL is connected to the column control circuitry (not shown). The three-dimensional NMOS NOR flash transistor 100 is structured to store a single bit and is referred as one-transistor/one-bit NOR cell.
b is a schematic diagram of single 3D NMOS NOR flash transistor 100 in accordance with the layout shown in
c is a 3D cross sectional view of single one-transistor/one-bit three-dimensional NMOS NOR flash transistor 100 in 1c-1c′ axis shown in
d is a cross sectional view of single one-transistor/one-bit 3D NMOS NOR flash transistor 100 shown in 1d-1d′ axis in
e and 1f are respectively a cross sectional view and a top plan view of a 3D switching transistor 105 of the prior art. The bottom source N+ active layer 8 is connected to a diffusion layer 2 to form the local source line SL. A bulk region is a P− silicon cylinder 9 formed on the bottom source N+ active diffusion layer 8. An N+ active diffusion layer 10 is formed on the bulk region P− silicon cylinder 9 to make the drain. The drain N+ active layer 10 is connected to metal layer 12 is the common source line CSL that connected to the row decoder. A polycrystalline cylindrical ring 11 is formed around the bulk P− silicon cylinder 9 to create a gate for the 3D switching transistor 105. The activating of the 3D switching transistor 105 is controlled by activation signal R connected to the polycrystalline cylindrical ring 11.
a is a top plan layout view of a 3D one-transistor/one-bit NMOS NOR flash memory cell array of the prior art.
The array of the one-transistor/one-bit 3D NMOS NOR flash transistors 100 includes two rows of switching transistors 105. One of the switching transistors 105 on each row of the two rows of switching transistors 105 has its source diffusion 8 connected to the source line diffusion area associated with each column of the one-transistor/one-bit 3D NMOS NOR flash transistors 100. The drain diffusion 10 of the switching transistors 100 is connected to a metal common source diffusion line CSL. The polycrystalline silicon gate 11 of each of the switching transistors 105 is connected to the activation signal R.
In a program of a page of an array, a very large programming voltage of approximately 18.0V is applied to the word line WL of the selected page. The ground reference voltage level is applied to the unselected word lines WL of the unselected pages of the array. The activation signal R is set to the ground reference voltage level (0.0V) to prevent the common source line CSL from being connected to the source lines SL. The common source line CSL is set to a common source line program voltage level of approximately 4.5V. The program inhibit voltage level of 9.0V is applied to the bit lines BL and is coupled to the source lines SL of the unselected 3D NMOS NOR flash transistors 100. The ground reference voltage level is applied to the bit lines BL and coupled to the source lines SL of the selected 3D NMOS NOR flash transistors 100 to initiate a Fowler-Nordheim tunneling phenomenon to program the selected 3D NMOS NOR flash transistors 100.
In a mass or total erase of an array of the 3D NMOS NOR flash transistors 100, all the word lines are connected to the ground reference voltage level (0.0V). The common source line CSL and the activate signal R are set to the very large positive erase voltage level of 18.0V. This couples the very large positive erase voltage level of 18.0V to the source lines SL. The very large positive erase voltage level of 18.0V is transferred to all the bit lines BL. The Fowler-Nordheim tunneling phenomenon is initiated to remove the electrical charges from the 3D NMOS NOR flash transistors 100.
When the 3D NMOS NOR flash transistors 100 on one word line WL are selected to be erased, the selected word line WL has the ground reference voltage level (0.0V) applied to it. An erase inhibit voltage of 9.0V is applied to the unselected word lines WL. The common source line CSL and the activate signal R are set to the very large positive erase voltage level of 18.0V. This couples the very large positive erase voltage level of 18.0V to the source lines SL. The very large positive erase voltage level of 18.0V is transferred to all the bit lines BL. The Fowler-Nordheim tunneling phenomenon is initiated to remove the electrical charges from the 3D NMOS NOR flash transistors 100 of the selected word line WL.
When one column of the 3D NMOS NOR flash transistors 100 is selected to be erased, all the word lines WL have the ground reference voltage level (0.0V) applied to it. An erase inhibit voltage of 9.0V is applied to the unselected bit lines BL. The common source line CSL is set to an intermediate erase voltage level of approximately 13.5V. The activate signal R are set to the erase inhibit voltage. This couples the erase inhibit voltage to the unselected source lines SL. The very large positive erase voltage level of 18.0V is transferred to the selected bit line BL and source lines SL. The Fowler-Nordheim tunneling phenomenon is initiated to remove the electrical charges from the 3D NMOS NOR flash transistors 100 of the selected bit line BL.
When selected single 3D NMOS NOR flash transistors 100 are selected to be erased, the word lines WL of the selected 3D NMOS NOR flash transistors 100 have the ground reference voltage level (0.0V) applied to it. The erase inhibit voltage is applied to the word lines WL of the unselected 3D NMOS NOR flash transistors 100 and to the unselected bit lines BL. The common source line CSL is set to an intermediate erase voltage level of approximately 13.5V. The activate signal R are set to the erase inhibit voltage. This couples the erase inhibit voltage to the unselected source lines SL. The very large positive erase voltage level of 18.0V is transferred to the selected bit line BL and is coupled to the selected source lines SL. The Fowler-Nordheim tunneling phenomenon is initiated to remove the electrical charges from the selected 3D NMOS NOR flash transistors 100 of the selected bit line BL.
An object of this application is to provide a very compact three-dimensional one level polycrystalline silicon, charge-trapping, SONGS-type, three-dimensional NAND-based NOR nonvolatile memory cell for constructing very high density nonvolatile memory arrays. Each three-dimensional a three-dimensional NAND-based NOR nonvolatile memory cell consists of two highly scalable three-dimensional SONOS-type charge-retaining transistors connected in series employing three-dimensional low-current NAND-based. NOR cell structure and operation. The three-dimensional two-transistor/two-bit NOR cell is arranged in a series string such that one of the charge-retaining transistors functions as a select gate transistor to prevent leakage current through the charge-retaining transistors when the charge-retaining transistors is not selected for determining a data state of the three-dimensional NAND-based NOR nonvolatile memory cell. The preferable threshold voltage levels Vt1 and Vt0 are chosen to totally eliminate the long-held over-erase concern and achieve a factor of ten faster write speed over the traditional one transistor/one bit NOR flash array.
In various embodiments of the three-dimensional charge-retaining transistors, the first voltage threshold level (Vt1) is approximately +1.0V and second voltage threshold (Vt0) is approximately −2.0V for each three-dimensional two-transistor/two-bit NOR flash cells. These voltage levels achieve the faster and lower power-consumption of the NOR operation with a power supply voltage level (VDD) that is at or below 1.5V. With a power supply voltage level less than or equal to the 1.5V, an on-chip voltage boost generation circuit is not required to generate the selected word line voltages higher than the power supply voltage source.
In some embodiments of this application, a compact one level polycrystalline silicon, charge-trapping, SONOS-type, a three-dimensional NAND-based NOR nonvolatile memory cell array is constructed of a three-dimensional NAND-based NOR nonvolatile memory cell arrange in rows and columns. Each column of the a three-dimensional NAND-based NOR nonvolatile memory cell has with a local bit line and a local source line formed as two parallel N+ active layers diffused below each of the three-dimensional charge-retaining transistors of the NAND-based NOR cell. A source of a first of the two three-dimensional charge-retaining transistors is connected to a second of the two three-dimensional charge-retaining transistors to connect the two three-dimensional charge-retaining transistors in series. The two three-dimensional charge-retaining transistors are offset from one another such that the first three-dimensional charge-retaining transistor is placed above the local bit line and the second three-dimensional charge-retaining transistor is placed above the local source line. The control gates of the two series connected three-dimensional charge-retaining transistors are each coupled to one of two paired word lines that are associated with a row of the NAND-based NOR cells. The control gates polycrystalline silicon formed to be connected with each of the three-dimensional charge-retaining transistors.
In various embodiments, a write flow achieves a fast program and erase operation by setting the values of the first threshold voltage level (Vt0) and the second threshold voltage level (Vt1) to eliminate and over-erase and bit line punch-through the two-transistor/two-bit three-dimensional NAND-based NOR cell array. In some embodiments, the first threshold voltage level (Vt0) is the programmed voltage level and the second threshold voltage level (Vt1) is the erased voltage level. To program the selected row of charge-retaining transistors of two-transistor/two-bit three-dimensional NAND-based NOR cells on a row of the array, the word line attached to the selected row of three-dimensional charge-retaining transistors is set to a very large programming voltage level of approximately 18.0V. The word line connected to the unselected three-dimensional charge-retaining transistors of the selected row of the two-transistor/two-bit three-dimensional NAND-based NOR cells is set to a charge-retaining transistor activation voltage level of approximately 4.5V. The paired word lines of the unselected two-transistor/two-bit three-dimensional NAND-based NOR cells on a row of the array are set to the charge-retaining transistor activation voltage level. The bit lines and source lines of the selected charge-retaining transistors are set to the ground reference voltage level (0.0V). The bit lines and the source lines of the unselected charge-retaining transistors are set to a programming inhibit voltage level of approximately (9.0V).
To erase the two-transistor/two-bit three-dimensional NAND-based NOR cells on a row of the array, the paired word lines of the charge-retaining transistors of the two-transistor/two-bit three-dimensional NAND-based NOR cells are set to the ground reference voltage level (0.0V). The unselected row paired word lines of the two-transistor/two-bit three-dimensional NAND-based NOR cells are set to an erase inhibit voltage level of approximately 9.0V. The bit lines and the source lines of the two-transistor/two-bit three-dimensional NAND-based NOR cells on a row of the array are set to a very large erase voltage level of approximately 18.0V.
In other embodiments, the first threshold voltage-level (Vt0) is the erased voltage level and the second threshold voltage level (Vt1) is the programmed voltage level. To program the selected row of charge-retaining transistors of two-transistor/two-bit three-dimensional NAND-based NOR cells on a row of the array, the word line attached to the selected row of three-dimensional charge-retaining transistors is set to the ground reference voltage level (0.0V). The word line connected to the unselected three-dimensional charge-retaining transistors of the selected row of the two-transistor/two-bit three-dimensional NAND-based NOR cells is set to a charge-retaining transistor activation voltage level of approximately 9.0V. The paired word lines of the unselected two-transistor/two-bit three-dimensional NAND-based NOR cells on a row of the array are set to the charge-retaining transistor activation voltage level. The bit lines and source lines of the selected charge-retaining transistors are set to the a very large programming voltage level of approximately 18.0V. The bit lines and the source lines of the unselected charge-retaining transistors are set to the ground reference voltage level.
To erase the two-transistor/two-bit three-dimensional NAND-based NOR cells of the entire array, the paired word lines of the charge-retaining transistors of the two-transistor/two-bit three-dimensional NAND-based NOR cells are set to a very large erase voltage level of approximately 18.0V. The bit lines and the source lines of the two-transistor/two-bit three-dimensional NAND-based NOR cells on a row of the array are set to the ground reference voltage level (0.0V).
Another object of this application is to provide a very compact three-dimensional single level polycrystalline silicon, charge-retaining, three-transistor/one-bit EEPROM cell for constructing very high density multi-gigabit nonvolatile memory arrays. Each three-dimensional three-transistor/one-bit EEPROM cell consists of one highly scalable three-dimensional charge-retaining transistor with storage capability and two three-dimensional regular high voltage NMOS gating transistors connected in series with the charge-retaining transistor. In various embodiments a first threshold voltage level (Vt0) is the program threshold voltage level and has a voltage value of approximately −2.0V. The second threshold voltage level (Vt1) is the erase threshold voltage level and has a voltage value of approximately value of approximately +3.0V. With the charge-retaining transistor in series between the two gating transistors, the three-transistor/one-bit EEPROM cell has no over-erase concern. This allows a fast erase and program to be achieved within 1 mS to meet the EEPROM write specifications of current EEPROM cells.
In some embodiments of this application, a very compact one level polycrystalline silicon, charge-retaining, three-dimensional EEPROM cell array constructed of three-transistor/one-bit three-dimensional EEPROM cells arranged in rows and columns. Local bit lines and local source lines are formed parallel with their associated columns of the three-dimensional EEPROM cells. The local bit lines and the local source lines are N+ active layers diffused in the surface of the substrate under the charge-retaining transistor and the two three-dimensional high voltage NMOS gating transistors.
The drain of a first of the two gating transistors is connected to a local bit line diffusion that is connected to the drain of the three-dimensional charge-retaining transistor. The source of a second of the two gating transistors is connected to the local source line diffusion that connects to the source of the three-dimensional charge-retaining transistor. The source of the second gating transistors is connected to a metal source line formed in a superior position to the second gating transistor. The gates of the two gating transistors are connected to a selected gating line. The select gating line is a first polycrystalline silicon layer formed parallel with each row of the three-dimensional EEPROM cells. The control gate of the three-dimensional charge-retaining transistors on each row of is connected to a word line. The word line for each row of the three-dimensional charge-retaining transistors is formed of a second polycrystalline silicon layer placed parallel to the associated row of the three-dimensional charge-retaining transistors.
In various embodiments, a write operation achieves a fast program and erase by setting the values of the first threshold voltage level (Vt0) and the second threshold voltage level (Vt1) to eliminate an over-erase and bit line punch-through the three-transistor/one-bit three-dimensional EEPROM array. The first threshold voltage level (Vt0) is the programmed voltage level and the second threshold voltage level (Vt1) is the erased voltage level. To program the selected row of charge-retaining transistors of three-transistor/one-bit three-dimensional EEPROM cells on a row of the array, the ground reference voltage level (0.0V) is applied to the global bit line(s) of the selected and unselected sub-array block(s). The select gating line(s) for the selected sub-array block(s) have a select gating voltage level that is applied to the word line biasing transistor and the gates of the first and second three-dimensional switching transistors. The word line biasing transistor(s) is activated to apply the ground reference voltage level (0.0V) to the word lines, and thus to the gates of the charge-retaining transistors of the selected three-transistor/one-bit three-dimensional EEPROM cells. The select gating biasing voltage level is approximately 18.0V.
The bit lines, and source lines, of the selected sub-array block(s) are all set to the very large programming voltage level to initiate a Fowler-Nordheim Tunneling phenomenon to extract negative charges from the insulating SONOS layer of the charge-retaining transistor shown to decrease the threshold voltage level of the selected three-transistor/one-bit three-dimensional EEPROM cells to the programmed threshold voltage level (Vt0) that is approximately −1.5V. In various embodiments, the bit lines of the selected sub-array block(s) are all set to the very large programming voltage level. The source lines of the selected sub-array block(s) are disconnected and allowed to float or are set to the ground reference voltage level (0.0V) to initiate a hot carrier (hole) injection phenomenon to extract negative charges from the insulating SONOS layer of the charge-retaining transistor. In other embodiments, the source lines of the selected sub-array block(s) are all set to the very large programming voltage level. The bit lines of the selected sub-array block(s) are disconnected and allowed to float or set to the ground reference voltage level (0.0V) to initiate a hot carrier (hole) injection phenomenon to extract negative charges from the insulating SONOS layer of the charge-retaining transistor. The unselected bit lines and source lines of the selected sub-array block(s) are set to the ground reference voltage level (0.0V) to inhibit programming the unselected three-transistor/one-bit three-dimensional EEPROM cells. The very large programming voltage level is approximately 18.0V.
To erase a selected row containing a byte or page of charge-retaining transistors of three-transistor/one-bit three-dimensional EEPROM cells or an entire chip of charge-retaining transistors of three-transistor/one-bit three-dimensional EEPROM cells, a very large erasing voltage level is applied to the global bit line(s) of the array or selected sub-array block(s). The very large erasing voltage level is approximately 18.0V. The select gating line(s) for the selected sub-array block(s) have a select gating voltage level that is applied to the gate of the word line biasing transistor and to the gates of the first and second three-dimensional switching transistors. The word line biasing transistor(s) is activated to apply the very large erasing voltage level to the word lines and thus to the gates of the charge-retaining transistors of the selected three-transistor/one-bit three-dimensional EEPROM cells. The select gating biasing voltage level is approximately 18.0V. The global bit line(s) of the unselected sub-array blocks are set to the ground reference voltage level (0.0V) to deactivate the word line biasing transistor to inhibit erasure.
The bit lines and source lines are all set to the ground reference voltage level (0.0 v) to initiate a Fowler-Nordheim Tunneling phenomenon to attract negative charges to the insulating SONOS layer of the charge-retaining transistor to increase the threshold voltage level of the selected three-transistor/one-bit three-dimensional EEPROM cells to the erased threshold voltage level Vt1 that is approximately 2.0V. If the entire array of three-transistor/one-bit three-dimensional EEPROM cells is to be erased, there are no unselected global bit lines, bit lines or source lines.
Further another object of this application is to provide a very compact three-dimensional, single level polycrystalline silicon, charge-trapping, two transistor/two-bit, NAND-based programmed logic device (PLD) circuit for constructing very high density nonvolatile PLD arrays. Each three-dimensional two transistor/two-bit NAND-based PLD cell consists of two highly scalable three-dimensional SONOS-type charge-retaining transistors connected in series employing a three-dimensional low-current NAND-based PLD cell that is similar in structure and operation to the NAND-based NOR nonvolatile memory cell described above. The three-dimensional two-transistor/two-bit PLD cell is arranged in a series string such that the threshold voltage levels of each of the charge-retaining transistors of the three-dimensional two-transistor/two-bit PLD cell have complementary threshold voltage levels. The threshold voltage levels of each of the charge-retaining transistors of the three-dimensional two-transistor/two-bit PLD cell are selected such that the first threshold voltage level (Vt0) is set to be less than approximately −1.0V and the second threshold voltage level (Vt1) is set to be approximately 0.7V.
In a logic operation the threshold voltage levels of each of the charge-retaining transistors of the three-dimensional two-transistor/two-bit PLD cell are programmed to be complementary such that if one of the charge-retaining transistors is the first threshold voltage value (Vt0), the other charge-retaining transistor is programmed to the second threshold voltage level (Vt1). Each three-dimensional two-transistor/two-bit PLD cell has two inputs that are coupled to two complementary logic input signals I[N] and I[NB].
In various embodiments, an array is formed of rows and columns of the three-dimensional two-transistor/two-bit PLD cells. Each column of the three-dimensional two-transistor/two-bit PLD cells is associated and parallel with a local bit line and a local source line. The local bit lines and a local source lines are formed as two parallel N+ diffusion layer below each column of the three-dimensional two-transistor/two-bit PLD cells. The source of one of the charge-retaining transistors is connected to the drain of a second of the charge-retaining transistors with a local metal layer above the top surface of the charge-retaining transistors of each of the three-dimensional two-transistor/two-bit PLD cells of the array. The two gates of each of the charge-retaining transistors of each of the three-dimensional two-transistor/two-bit PLD cells are coupled to two adjacent paired word lines associated with a row of the three-dimensional two-transistor/two-bit PLD cell. Each of the paired word lines is formed of a single polycrystalline conductor connected to row decoding circuitry for controlling selection of a row of the charge-retaining transistors of the three-dimensional two-transistor/two-bit PLD cells.
In a various embodiments, a write operation achieves a fast program and erase by setting the values of the first threshold voltage level (Vt0) and the second threshold voltage level (Vt1) to eliminate an over-erase and bit line punch-through of the three-dimensional two-transistor/two-bit PLD cell. The first threshold voltage level (Vt0) is the erased voltage level and the second threshold voltage level (Vt1) is the programmed voltage level. The write process begins with a pre-program operation where the entire array of the three-dimensional two-transistor/two-bit PLD cells is programmed to have their threshold voltage levels established at greater than the second threshold or programmed threshold voltage level. To accomplish this, the word lines of the array are placed at the very large positive program voltage and the local source lines and the local bit lines are set to the ground reference voltage level (0.0V). This initiates the Fowler-Nordheim tunneling phenomenon to attract negative charges to the charge-trapping region of the charge-trapping transistors of the three-dimensional two-transistor/two-bit PLD cells.
The write process continues with erasing the first charge-retaining transistors of all of the three-dimensional two-transistor/two-bit PLD cells. The word lines connected to the control gates of the first charge-retaining transistors of all the three-dimensional two-transistor/two-bit PLD cells of the array are set to the ground reference voltage level. The word lines connected to the second charge-retaining transistors of all of the three-dimensional two-transistor/two-bit PLD cells are set to an erase inhibit voltage level of approximately 9.0V. The local bit line and the local source lines are coupled to a very large positive erase voltage of approximately 18V. This initiates the Fowler-Nordheim tunneling phenomena to lower the threshold voltage level of the first charge-retaining transistors of all the three-dimensional two-transistor/two-bit PLD cells of the array to the first threshold voltage level (Vt0) to initiate the Fowler-Nordheim tunneling phenomena.
Selected first charge-retaining transistors of selected pages or rows of the three-dimensional two-transistor/two-bit PLD cells of the array are then programmed. In the page program process, the word lines connected to the selected page(s) are connected to a very large positive programming voltage level of approximately 18.0V. The word lines connected to the unselected pages or rows are connected to an intermediate positive program inhibit voltage level of approximately 9.0V. The unselected pages of the charge-retaining transistors include the unselected word line of the paired word lines of the selected three-dimensional two-transistor/two-bit PLD cells and the paired word lines of the unselected three-dimensional two-transistor/two-bit PLD cells. The local bit lines and the local source lines are set the ground reference voltage level (0.0V) to initiate the Fowler-Nordheim tunneling phenomena.
The write process continues with erasing the second charge-retaining transistors of all of the three-dimensional two-transistor/two-bit PLD cells. The word lines connected to the control gates of the second charge-retaining transistors of all the three-dimensional two-transistor/two-bit PLD cells of the array are set to the ground reference voltage level. The word lines connected to the first charge-retaining transistors of all of the three-dimensional two-transistor/two-bit PLD cells are set to an erase inhibit voltage level of approximately 9.0V. The local bit line and the local source lines are coupled to a very large positive erase voltage of approximately 18V. This initiates the Fowler-Nordheim tunneling phenomena to lower the threshold voltage level of the second charge-retaining transistors of all the three-dimensional two-transistor/two-bit PLD cells of the array to the second threshold voltage level (Vt0) to initiate the Fowler-Nordheim tunneling phenomena.
Selected second charge-retaining transistors of selected pages or rows of the three-dimensional two-transistor/two-bit PLD cells of the array are then programmed. In the page program process, the word lines connected to the selected page(s) are connected to a very large positive programming voltage level of approximately 18.0V. The word lines connected to the unselected pages or rows are connected to an intermediate positive program inhibit voltage level of approximately 9.0V. The unselected pages of the charge-retaining transistors include the unselected word line of the paired word lines of the selected three-dimensional two-transistor/two-bit PLD cells and the paired word lines of the unselected three-dimensional two-transistor/two-bit PLD cells. The local bit lines and the local source lines are set the ground reference voltage level (0.0V) to initiate the Fowler-Nordheim tunneling phenomena.
Another object of the present application is to provide a three-dimensional single level polycrystalline silicon, charge-trapping, SONOS-type, four-transistor/one-bit fast programmable switch cell for a low-resistance switching application for fast connections in an FPGA application. The four-transistor/one-bit cell comprises two three-dimensional charge-retaining transistors connected in a NAND-based series string. The control gate of the first charge-retaining transistor is connected to a primary input line to receive an in-phase logic input signal and the control gate of the second charge-retaining transistor is connected to an inverse primary input line to receive an out-of-phase input signal. The drain of a first of the charge-retaining transistors is connected to a write bit line and the source of a second of the charge-retaining transistors is connected to a write source line. The source of the first charge-retaining transistor and the drain of the second charge-retaining transistor are connected to a gate of a three-dimensional NMOS isolation transistor. The drain of the isolation transistor is connected to read word line that is connected to a gate of a three-dimensional NMOS low-resistance switch transistor. The drain of the low-resistance read transistor is connected to a read bit line and the source of the read transistor is connected to a read source line.
In a logic operation the threshold voltage levels of each of the charge-retaining transistors of the three-dimensional four-transistor/one-bit fast switch cell are programmed to be complementary such that if one of the charge-retaining transistors is the first threshold voltage value (Vt0), the other flash transistor's is programmed to the second threshold voltage level (Vt1). Each three-dimensional four-transistor/one-bit fast switch cell two inputs that are coupled to a primary input line and an inverse primary input line that provide two complementary input signals. The threshold voltage levels are chosen such that a first of the threshold voltage levels (Vt0) is negative with a voltage level of approximately −2.0V and a second threshold voltage level (Vt1) that is positive with a voltage level of approximately +1.0V.
The local write bit line and local source line are an N+ diffusion buried layers running in parallel with and beneath a column of the three-dimensional four-transistor/one-bit fast switch cells. The three-dimensional NMOS isolation transistor is placed as closely as possible to two charge-retaining transistors to form a very compact size of the three-dimensional four-transistor/one-bit fast switch cell.
In a various embodiments, a write operation achieves a fast program and erase by setting the values of the first threshold voltage level (Vt0) and the second threshold voltage level (Vt1) to eliminate an over-erase and bit line punch-through of the four-transistor/one-bit fast programmable switch cell. The first threshold voltage level (Vt0) is the erased voltage level and the second threshold voltage level (Vt1) is the programmed voltage level. The write process begins with a pre-program operation where the entire array of the four-transistor/one-bit fast programmable switch cell is programmed to have their threshold voltage levels established at greater than the second threshold or programmed threshold voltage level. To accomplish this, the primary input and inverse primary input lines of the array are placed at the very large positive program voltage and the local source lines and the local bit lines are set to the ground reference voltage level (0.0V). This initiates the Fowler-Nordheim tunneling phenomenon to attract negative charges to the charge-trapping region of the charge-trapping transistors of the four-transistor/one-bit fast programmable switch cell.
The write process continues with erasing the first charge-retaining transistors of all of the four-transistor/one-bit fast programmable switch cells. The primary input lines connected to the control gates of the first charge-retaining transistors of all the four-transistor/one-bit fast programmable switch cell of the array are set to the ground reference voltage level. The inverse primary input lines connected to the second charge-retaining transistors of all of the four-transistor/one-bit fast programmable switch cells are set to an erase inhibit voltage level of approximately 9.0V. The local bit line and the local source lines are coupled to a very large positive erase voltage of approximately 18V. This initiates the Fowler-Nordheim tunneling phenomena to lower the threshold voltage level of the first charge-retaining transistors of all the four-transistor/one-bit fast programmable switch cells of the array to the first threshold voltage level (Vt0) to initiate the Fowler-Nordheim tunneling phenomena.
Selected first charge-retaining transistors of selected pages or rows of the four-transistor/one-bit fast programmable switch cells of the array are then programmed. In the page program process, the primary input and inverse primary input lines connected to the selected page(s) are connected to a very large positive programming voltage level of approximately 18.0V. The primary input and inverse primary input lines connected to the unselected pages or rows are connected to an intermediate positive program inhibit voltage level of approximately 9.0V. The unselected pages of the charge-retaining transistors include the unselected word line of the paired word lines of the selected four-transistor/one-bit fast programmable switch cells and the paired word lines of the unselected three-dimensional two-transistor/two-bit PLD cells. The local bit lines and the local source lines are set the ground reference voltage level (0.0V) to initiate the Fowler-Nordheim tunneling phenomena.
The write process continues with erasing the second charge-retaining transistors of all of the four-transistor/one-bit fast programmable switch cells. The primary input and inverse primary input lines connected to the control gates of the second charge-retaining transistors of all the four-transistor/one-bit fast programmable switch cells of the array are set to the ground reference voltage level. The primary input and inverse primary input lines connected to the first charge-retaining transistors of all of the four-transistor/one-bit fast programmable switch cells are set to an erase inhibit voltage level of approximately 9.0V. The local bit line and the local source lines are coupled to a very large positive erase voltage of approximately 18V. This initiates the Fowler-Nordheim tunneling phenomena to lower the threshold voltage level of the second charge-retaining transistors of all the four-transistor/one-bit fast programmable switch cells of the array to the second threshold voltage level (Vt0) to initiate the Fowler-Nordheim tunneling phenomena.
Selected second charge-retaining transistors of selected pages or rows of the four-transistor/one-bit fast programmable switch cells of the array are then programmed. In the page program process, the primary input and inverse primary input lines connected to the selected page(s) are connected to a very large positive programming voltage level of approximately 18.0V. The primary input and inverse primary input lines connected to the unselected pages or rows are connected to an intermediate positive program inhibit voltage level of approximately 9.0V. The unselected pages of the charge-retaining transistors include the unselected primary input and inverse primary input lines of the paired primary input and inverse primary input lines of the selected four-transistor/one-bit fast programmable switch cells and the paired word lines of the unselected four-transistor/one-bit fast programmable switch cells. The local bit lines and the local source lines are set the ground reference voltage level (0.0V) to initiate the Fowler-Nordheim tunneling phenomena.
In some embodiments, a three-dimensional combination nonvolatile memory integrated circuit that includes any number of the three-dimensional NAND-based NOR nonvolatile memories including a three-dimensional two-transistor/two-bit NOR array for the block-alterable code storage, a three-dimensional three-transistor/one-bit byte-alterable EEPROM array for byte-alterable data storage, a three-dimensional NAND-based NOR two-transistor/two-bit block-alterable PLD's “AND and OR” logic arrays and a three-dimensional four-transistor/one-bit fast switch block-alterable array for a powerful memory and logic system-on-chip structure.
a is a top plan view of a three-dimensional nonvolatile memory cell of the prior art.
b is a schematic diagram of a three-dimensional nonvolatile memory cell of the prior art.
c-1d are a cross-sectional views of a three-dimensional nonvolatile memory cell of the prior art.
e is a cross-sectional view of a three-dimensional transistor of the prior art.
f is a top plan view of a three-dimensional transistor of the prior art.
a is a top plan view of a three-dimensional nonvolatile memory array of the prior art.
b is a cross-sectional view of a three-dimensional nonvolatile memory array of the prior art.
a is a top plan view of a three-dimensional NAND-based NOR nonvolatile memory cell embodying the principles of the present application.
b is a schematic diagram of a three-dimensional NAND-based NOR nonvolatile memory cell embodying the principles of the present application.
c-5d are cross-sectional views of a three-dimensional NAND-based NOR nonvolatile memory cell embodying the principles of the present application.
a is a cross-sectional view of a three-dimensional switching transistor embodying the principles of the present application.
b is a top plan view of a three-dimensional switching transistor embodying the principles of the present application.
a-7h are plots of the distributions of program and erase threshold voltage levels for the three-dimensional charge-retaining transistors of the three-dimensional NAND-based NOR nonvolatile memory cells of
a is a schematic of an array of three-dimensional NAND-based NOR nonvolatile memory cells embodying the principles of the present application.
b is a top plan view of an array of three-dimensional NAND-based NOR nonvolatile memory cells embodying the principles of the present application.
c-8d are cross-sectional views of an array of three-dimensional NAND-based NOR nonvolatile memory cells embodying the principles of the present application.
a and 9b are flowcharts for two methods of operation of a three-dimensional NAND-based NOR nonvolatile memory array embodying the principles of the present application.
a and 10b are charts of voltage levels for the operating an array of three-dimensional NAND-based NOR nonvolatile memory cells of
a is a top plan view of a three-dimensional NAND-based NOR nonvolatile PLD cell embodying the principles of the present application.
b is a schematic diagram of a three-dimensional NAND-based NOR nonvolatile PLD cell embodying the principles of the present application.
c is a plot of the program and erase threshold voltage distributions of three-dimensional NAND-based NOR nonvolatile PLD cell embodying the principles of the present application.
a is a schematic diagram of an array of three-dimensional NAND-based NOR nonvolatile PLD cells embodying the principles of the present application.
b is a block diagram of multiple arrays of the three-dimensional NAND-based NOR nonvolatile PLD cells embodying the principles of the present application of
c is a flowchart for a method of operation of a three-dimensional NAND-based NOR nonvolatile PLD array of
d is a chart of voltage levels for operating with the method of
a is a schematic diagram of a three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit for a low-resistance switching application for fast connections in an FPGA application embodying the principles of the present application.
b is a top plan view of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
c is a plot of the program and erase threshold voltage distributions of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
d is a diagram of an application within an FPGA of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
e is a chart for the voltage levels for functional operation of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
a is a flow chart for a method for programming and erasing the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
b is a chart of programming and erasing voltage levels of the operating voltage level of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
a is a schematic diagram of a three-transistor/one-bit three-dimensional EEPROM cell embodying the principles of the present application.
b is a top plan view of a three-transistor/one-bit three-dimensional EEPROM cell embodying the principles of the present application.
c-15e are cross-sectional views of the transistors of a three-transistor/one-bit three-dimensional EEPROM cell of
f is a plot of the program and erase threshold voltage distributions of a three-transistor/one-bit three-dimensional EEPROM cell embodying the principles of the present application.
a is a schematic diagram of an array of three-transistor/one-bit three-dimensional EEPROM cells embodying the principles of the present application.
b is a top plan view of an array of three-transistor/one-bit three-dimensional EEPROM cells embodying the principles of the present application
c is a is a cross-sectional view of a interlayer plug of an array of three-transistor/one-bit three-dimensional EEPROM cells embodying the principles of the present application.
d and 16e are cross sectional views of an array of three-transistor/one-bit three-dimensional EEPROM cells embodying the principles of the present application.
a is a top plan view of a three-dimensional NAND-based NOR nonvolatile memory cell 200.
The three-dimensional charge-retaining transistors M0 and M1 are formed similar to the single one-transistor/one-bit three-dimensional NMOS NOR flash transistor 100 of
A metal layer 213 is a connector strap that joins the source N+ active diffusion layer 205a of the three-dimensional charge-retaining transistor M0 and drain N+ active diffusion layer 205b of the three-dimensional charge-retaining transistor M1. The three-dimensional NAND-based NOR nonvolatile memory cell 200 is structured to store two bits.
Referring to
a is a cross-sectional view of a three-dimensional switching transistor.
a-7h are plots of the distributions of program and erase threshold voltage levels for the three-dimensional charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200 of
In
In
Referring now to
Refer now to table 1 for one embodiment of the programming of the internal logic states of the three-dimensional charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cell 200. The threshold voltage assignments for the three-dimensional charge-retaining transistors M0 and M1 are illustrated in
a is a schematic of the array 300 of three-dimensional NAND-based NOR nonvolatile memory cells 200a, . . . , 200n.
Each row of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm is associated with a pair of word lines WL0, WL1, . . . , WLn. One of the paired word lines WL0, WL1, . . . , WLn is connected to the control gate of the first of the three-dimensional charge-retaining transistors M0 and the second of the paired word lines WL0, WL1, . . . , WLn is connected to the control gate of the three-dimensional charge-retaining transistors M1. The paired word lines WL0, WL1, WLn are connected to row control circuitry (not shown) that provides the necessary voltages for reading, programming, erasing, and verifying the programming or erasing of selected three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm.
Each of the local bit lines BL0, . . . , BLm are connected to the source of one of the select gating transistors 205a0, . . . , 205am. Each drain of select gating transistors 205a0, . . . , 205am are connected to a global bit line GBL0, . . . , GBLm associated with each column of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm. Each of the local source lines SL0, . . . , SLm are connected to the source of one of the select gating transistors 205b0, . . . , 205bm. Each drain of select gating transistors 205b0, 205bm are connected to a global source line GSL0, . . . , GSL associated with each column of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm. The global bit lines GBL0, . . . , GBL and the global source lines GSL0, . . . , GSL are connected to a column control circuit that provides the circuitry for generating the necessary voltage levels necessary for reading, programming, erasing and verifying the programming and erasing of selected three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm. The gate of the select gating transistor 205a is connected to a select bit line gating signal generated by the row control circuitry (not shown) to activate the select gating transistor 205a. The gate of the select gating transistor 205b is connected to a select bit line gating signal generated by the row control circuitry (not shown) to activate the select gating transistor 205b.
Refer now to
One end of the local bit line N+ active diffusion layer 302a is connected to the source of the select gating transistor 205a. Similarly, one end of the local source line N+ active diffusion layer 302b is connected to the source of the select gating transistor 205b. The select gating transistors 205a and 205b are structured as described in
a and 9b are flowcharts for two methods of operation of a three-dimensional NAND-based NOR nonvolatile memory array embodying the principles of the present application.
The charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are pre-program verified as part of the pre-programming (Box 402). Each word line is set to the minimum voltage level of the third threshold voltage level (Vt2min) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are pre-programmed with the global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS being set as shown in the row for the array pre-program verify of
The write process begins with erasing (Box 404) a selected paired row of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm on a selected row to the first threshold voltage level (Vt0). This is accomplished by setting the voltage levels for the word lines WL, the global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS are shown in the row for the paired erase of
The paired row of charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are erase verified as part of the erasing (Box 404). Each paired word line is set to the ground reference voltage level (0.0V) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are erased with the unselected word lines WL, global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS being set as shown in the row for the paired erase verify of
The write process continues with programming (Box 406) a selected paired row of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm on a selected row to the second threshold voltage level (Vt1). This is accomplished by setting the voltage levels for the selected and unselected word lines WL, the global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS are shown in the row for the paired erase of
The paired row of charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are program verified as part of the programming (Box 406). Each paired word line is iteratively set to the minimum value of the second threshold voltage level (Vt1 min) followed by minimum value of the third threshold voltage level (Vt2 min) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are programmed with the unselected word lines WL, global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS being set as shown in the row for the paired erase verify of
The process examines (Box 408) if the last paired row of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm have been written. If they have not been written, the next paired row of the charge-retaining transistors M0 and M1 are selected (Box 410) and written as described above. When all the selected charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are written the process ends (Box 412).
The chart of
Referring to
The charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are erase verified as part of the erasing (Box 402). Each word line is set to the minimum voltage level of the third threshold voltage level (Vt2 min) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are erased with the global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS being set as shown in the row for the array pre-program verify of
A two page program (Box 416) of a selected paired row of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm on a selected row to the first threshold voltage level (Vt0) and the second threshold voltage level (Vt1). This is accomplished by setting the voltage levels for the word lines WL, the global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS are shown in the row for the paired erase of
The page programming (Box 416) continues with programming the selected paired row of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm on a selected row to the first threshold voltage level (Vt0). This is accomplished by setting the voltage levels for the selected and unselected word lines WL, the global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS are shown in the row for the paired program of
The paired row of charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are program verified as part of the programming (Box 416). Each paired word line is ground reference voltage level (0.0V) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are programmed to the first threshold voltage level (0.0V). The unselected word lines WL, global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS being set as shown in the row for the page program verify of
The process examines (Box 418) if the last paired row of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm have been written. If they have not been written, the next paired row of the charge-retaining transistors M0 and M1 are selected (Box 420) and written as described above. When all the selected charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are written the process ends (Box 422).
The chart of
a is a top plan view of a three-dimensional NAND-based NOR nonvolatile PLD cell employing the three-dimensional NAND-based NOR nonvolatile PLD cell as described above for
c is a plot of the program and erase threshold voltage levels for the three-dimensional charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile memory cells 200 of
a is a schematic diagram of an array 300 of three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm as described above for
As in
Each of the local bit lines BL0, . . . , BLm are connected to the source of one of the select gating transistors 205a0, . . . , 205am. Each drain of select gating transistors 205a0, . . . , 205am are connected to a global bit line GBL0, . . . , GBLm associated with each column of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm. Each of the local source lines SL0, . . . , SLm are connected to the source of one of the select gating transistors 205b0, . . . , 205bm. Each drain of select gating transistors 205b0, . . . , 205bm are connected to a global source line GSL0, . . . , GSLm associated with each column of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm. The global bit lines GBL0, . . . , GBLm and the write source lines GSL0, . . . , GSLm are connected to a column control circuit that provides the circuitry for generating the necessary voltage levels necessary for reading, programming, erasing and verifying the programming and erasing of selected three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm. Each of the global bit lines GBL0, . . . , GBLm are connected to a sense amplifier 515a, . . . , 515m. In a read operation where a logic operation being performed with the primary inputs I[0], . . . , I[n] and inverse primary inputs
The gates of the select gating transistors 205a1, . . . , 205am are connected to a select bit line gating signal SGD generated by the row control circuitry (not shown) to activate the select gating transistors 205a1, . . . , 205am. The select gating transistors 205a1, . . . , 205am control connecting the drains of the charge-retaining transistors M0 of the columns of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm to the column control circuitry including the sense amplifiers 515a, . . . , 515m. The gates of the select gating transistors 205b1, . . . , 205bm is connected to a select source line gating signal SGS generated by the row control circuitry (not shown) to activate the select gating transistors 205a1, . . . , 205am. The select gating transistors 205b1, . . . , 205bm control connecting the sources of the charge-retaining transistors M1 of the columns of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm to the column control circuitry.
b is a block diagram of multiple arrays 600-00, . . . , 600-0K, . . . , 600-J0, . . . , 600-JK of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm of
Each row of the blocks 600-00, . . . , 600-0K, . . . , 600-J0, . . . , 600-JK of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm is connected to receive the select bit line gating signals SGD[0], . . . , SGD[J] and the select source line gating signals SGS[0], . . . , SCS[J]. The rows of blocks 600-00, . . . , 600-0K, . . . , 600-J0, . . . , 600-JK each have primary inputs I[00], . . . , I[0n], . . . , I[J0], . . . , I[Jn] and inverse primary inputs
The global bit lines GBL[00], . . . , GBL[0m], . . . , GBL[K0], . . . , GBL[Km] originating with each column of the blocks the blocks 600-00, . . . , 600-0K, . . . , 600-J0, . . . , 600-JK of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, 200am, . . . , 200na, . . . , 200nm is connected to a page buffer 620 to retain the logic states determined by the columns of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm of each of the blocks 600-00, . . . , 600-0K, . . . , 600-J0, . . . , 600-JK.
c is a flowchart for a method of operation of a three-dimensional NAND-based NOR nonvolatile PLD array 300 of
The charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are pre-program verified as part of the pre-programming operation (Box 602). Each word line is set to the minimum voltage level of the third threshold voltage level (Vt2min) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, 200nm are pre-programmed with the global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS being set as shown in the row for the array pre-program verify of
The write process begins with erasing (Box 604) a selected upper row of the charge-retaining transistors M0 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm on a selected row to the first threshold voltage level (Vt0). This is accomplished by setting the voltage levels for the primary input I[N], inverse primary input
The upper row of charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are erase verified as part of the erasing (Box 604). Each paired word line is set to the ground reference voltage level (0.0V) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are erased with the unselected primary input I[N], inverse primary input
The write process continues with programming (Box 606) selected charge-retaining transistors M0 of a selected upper row of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm to the second threshold voltage level (Vt1). This is accomplished by setting the voltage levels for the selected and unselected primary input I[N], inverse primary input
The upper row of charge-retaining transistors of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are program verified as part of the programming (Box 606). Each paired word line is iteratively set to the minimum value of the second threshold voltage level (Vt1min) followed by minimum value of the third threshold voltage level (Vt2min) for determining that each of the charge-retaining transistors M0 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are programmed with the unselected primary input I[N], inverse primary input
The write process continues with erasing (Box 608) a selected lower row of the charge-retaining transistors M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm on a selected row to the first threshold voltage level (Vt0). This is accomplished by setting the voltage levels for the primary input I[N], inverse primary input I[N], the global bit lines GBL, the global bit lines GBL, the global source lines GSL, the bit line select gating lines SGB, and the source line select gating lines SGS are shown in the row for the paired erase of
The lower row of charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are erase verified as part of the erasing (Box 608). Each paired word line is set to the ground reference voltage level (0.0V) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are erased with the unselected primary input I[N], inverse primary input
The write process continues with programming (Box 610) selected charge-retaining transistors M1 of a selected lower row of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm to the second threshold voltage level (Vt1). This is accomplished by setting the voltage levels for the selected and unselected primary input I[N], inverse primary input
The lower row of charge-retaining transistors of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are program verified as part of the programming (Box 610). Each paired word line is iteratively set to the minimum value of the second threshold voltage level (Vt1min) followed by minimum value of the third threshold voltage level (Vt2min) for determining that each of the charge-retaining transistors M0 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are programmed with the unselected primary input I[N], inverse primary input
The process examines (Box 612) if the last paired row of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm have been written. If they have not been written, the next paired row of the charge-retaining transistors M0 and M1 are selected (Box 614) and written as described above. When all the selected charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR nonvolatile PLD cells 200aa, . . . , 200am, . . . , 200na, . . . , 200nm are written the process ends (Box 616).
The chart of
a is a schematic diagram of a three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700 for a low-resistance switching application for fast connections in an FPGA application. The three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit has a switching transistor M3 having a drain connected to a read bit line RBL and a source connected to a read source line RSL to selectively connect the read bit line RBL to the read source line RSL for transferring a logic value signal between the read bit line RBL to the read source line RSL. A switch control circuit 705 connected through a read word line RWL to a gate of the switching transistor M3 turns on or turns off the switching transistor M3 to selectively connect the read bit line RBL to the read source line RSL based on a program state of the switch control circuit. If the switching transistor M3 is activated, a logic value signal from the read source line RSL is connected to the logic function circuit connected to the read bit line RBL. Alternately, if the switching transistor M3 is deactivated, the logic value signal from the read source line RSL is not connected to the logic function circuit connected to the read bit line RBL. It should be noted that the logic value signal may in fact be transferred from the read bit line RBL to the read source line RSL and still be in keeping with the principles of this invention.
The switch control circuit 705 is formed of a NAND-based NOR flash memory cell 710 having a pair of serially connected charge-retaining transistors M0 and M1 connected such that a drain a first charge-retaining transistor M0 is connected to a write bit line WBL. A source of a second charge-retaining transistor M1 is connected to a write source line WSL. The source of the first charge-retaining transistor M0 and the drain of the second charge-retaining transistors M1 are merged together. A select gating transistor M2 has a drain connected to the merged source of the first charge-retaining transistor M0 and the drain of the second charge-retaining transistors M1. A source of the select gating transistor M2 is connected to read word line RWL and thus to a gate of the switching transistor M3. A gate of the select gating transistor M2 is connected to an Isolation gating terminal ISO. The select gating transistor M2 is used to prevent damage from high voltage applied to the switching transistor M3 during program/erase operations. The high speed requirement in the read mode forces the switching transistor M3 to be made of a low voltage device with thinner oxide thickness. A gate of the first charge-retaining transistor M0 is connected to a primary input I[N] and the gate of the second charge-retaining transistor M1 is connected to an inverse primary input
b is a top plan view of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
A metal layer 213 is connector strap that joins the source N+ active diffusion layer 205a of the three-dimensional charge-retaining transistor M0 and drain N+ active diffusion layer 205b of the three-dimensional charge-retaining transistor M1. The metal layer 213 has a metal extension 713 that connects to the drain of the select gating transistor M2. The gate of the select gating transistor M2 is formed of the polycrystalline silicon layer 715 that is connected to external circuitry (not shown) to receive the isolation signal ISO. The source of the select gating transistor M2 is connected to the read word line 720. The read word line is a polycrystalline silicon layer 720 that extends to form the gate of the switching transistor M3. The drain of the switching transistor M3 is connected to the metal layer 725 that forms the read bit line RBL. The source of the switching transistor M3 is connected to the metal layer 730 that forms the read source line RSL.
c is a plot of the program and erase threshold voltage distributions of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
d is a diagram of an application within an FPGA of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
Each of the input conductors V0, V1, V2, V0′, VV, V2′ and the output conductors H0, H1, H2, H0′, H1′, H2′ at one intersection are connected to a cluster switch 750. One of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuits 700a, 700b, . . . , 700f is connected from one of the input conductors V0, V1, V2, V0′, VV, V2′ to its complementary input conductor V0, V1, V2, V0′, VV, V2′ and the associated output conductors H0, H1, H2, H0′, H1′, H2′. For example, with the input conductors V1, V1′ and the output conductors H1, H1′ that are connected to the cluster switch 750b, the input conductor V1 is connected through the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuits 700a to the output conductor H1. The input conductor V1 is connected through the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuits 700d to the output conductor H1′. The input conductor V1 is connected through the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuits 700e to the input conductor VV. The input conductor V1′ is connected through the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuits 700b to the output conductor H1. The input conductor V1 is connected through the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuits 700c to the output conductor H1′. The output conductor H1 is connected through the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuits 700f to the output conductor H1′. This structure enable any of the input conductors V0, V1, V2, V0′, VV, V2′ and the output conductors H0, H1, H2, H0′, H1′, H2′ to be interconnected with their associated input conductors V0, V1, V2, V0′, VV, V2′ and the output conductors H0, H1, H2, H0′, H1′, H2′.
In order to insure a connection that is sufficiently low in resistance, the switching transistor M3 must be turned on to pass the full swing of the voltage levels of the power supply voltage source VDD or the ground reference voltage VSS. To accomplish this, the voltage at the read word lines RWL0, RWL1, . . . , RWL5 connected to the input conductors V0, V1, V2, V′0, V′1, V′2 and the output conductors H0, H1, H2, H′0, H′1, H′2 must be greater than the power supply voltage source VDD by a differential voltage dv of from approximately 1.5V to approximately 2.0V. For those of the input conductors V0, V1, V2, V′0, V′1, V′2 and the output conductors H0, H1, H2, H′0, H′1, H′2 that are not to be connected, the switching transistor M3 completely turned off. Therefore, the read word lines RWL0, RWL1, . . . , RWL5 are connected to the ground reference voltage level VSS. This insures that the deactivated switching transistor M3 are non-conducting with a very large mega-ohm impedance.
e is a chart for the voltage levels for functional operation of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700 of
a is a flow chart for a method for programming and erasing the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit of
Referring to
The charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are pre-program verified as part of the pre-programming operation (Box 752). Each word line is set to the minimum voltage level of the programmed threshold voltage level (Vt1min) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are pre-programmed with the write bit lines WBL, the write source lines WSL, bit line and the isolation signal ISO being set as shown in the row for the array pre-program verify of
The write process begins with erasing (Box 754) a selected upper row of the charge-retaining transistors M0 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm on a selected row to the first threshold voltage level (Vt0). This is accomplished by setting the voltage levels for the primary input I[N], inverse primary input
The upper row of charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are page erase verified as part of the erasing (Box 754). Each paired word line is set to the ground reference voltage level (0.0V) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are erased with the unselected primary input I[N], inverse primary input
The write process continues with programming (Box 756) selected charge-retaining transistors M0 of a selected upper row of the three-dimensional NAND-based NOR nonvolatile PLD cells 700aa, . . . , 700am, . . . , 700na, . . . , 700nm to the second threshold voltage level (Vt1). This is accomplished by setting the voltage levels for the selected and unselected primary input I[N], inverse primary input
The upper row of charge-retaining transistors of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are program verified as part of the programming (Box 756). Each paired word line is iteratively set to the minimum value of the second threshold voltage level (Vt1min) for determining that each of the charge-retaining transistors M0 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are programmed with the unselected primary input I[N], inverse primary input
The write process continues with erasing (Box 758) a selected lower row of the charge-retaining transistors M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm on a selected row to the first threshold voltage level (Vt0). This is accomplished by setting the voltage levels for the primary input I[N], inverse primary input
The lower row of charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are page erase verified as part of the erasing (Box 758). Each paired word line is set to the ground reference voltage level (0.0V) for determining that each of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are erased with the selected and unselected primary input I[N], inverse primary input
The write process continues with programming (Box 760) selected charge-retaining transistors M1 of a selected lower row of the three-dimensional NAND-based NOR nonvolatile PLD cells 700aa, . . . , 700am, . . . , 700na, . . . , 700nm to the second threshold voltage level (Vt1). This is accomplished by setting the voltage levels for the selected and unselected primary input I[N], inverse primary input
The lower row of charge-retaining transistors of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are program verified as part of the programming (Box 760). Each paired word line is iteratively set to the minimum value of the second threshold voltage level (Vt1min) followed by minimum value of the third threshold voltage level (Vt2min) for determining that each of the charge-retaining transistors M0 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are programmed with the selected and unselected primary input I[N], inverse primary input
The process examines (Box 762) if the last paired row of the charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm have been written. If they have not been written, the next paired row of the charge-retaining transistors M0 and M1 are selected (Box 764) and written as described above. When all the selected charge-retaining transistors M0 and M1 of the three-dimensional NAND-based NOR flash nonvolatile reconfigurable switching circuit 700aa, . . . , 700am, . . . , 700na, . . . , 700nm are written the process ends (Box 766).
a is a schematic diagram of a three-transistor/one-bit three-dimensional EEPROM cell 800.
The drain N+ active diffusion layer 805 of the three-dimensional NMOS NOR flash transistor M1 is connected to a metal layer 813 that is connected to a source a first three-dimensional switching transistor M0. The first three-dimensional switching transistor M0 in
The source N+ active diffusion layer 803 of the three-dimensional NMOS NOR flash transistor M1 is connected to a drain of a second three-dimensional switching transistor M2 through the local source line N+ active diffusion local source line 818. The drain of the second three-dimensional switching transistor M2 is a N+ active diffusion 810b layer formed on the local source line N+ active diffusion local source line 818. A bulk region is a P− diffusion cylinder 809b formed on top of the source N+ active diffusion layer 810b. The drain of the three-dimensional NMOS NOR flash transistor M1 is formed of a N+ active diffusion layer 808b formed on the bulk P− diffusion region 809b. The drain N+ active diffusion layer 808b is connected to the metal plug layers 812 and 814 to a metal layer 815 that forms the source line SL.
A polycrystalline silicon layer 817 forms the gate of the first and second three-dimensional switching transistors M0 and M2. The polycrystalline silicon layer 817 is extended to the row control circuitry (not shown) to form the select gating line SG. The gates 817 of the first and second three-dimensional switching transistors M0 and M2 are commonly connected because the signals applied to the gates are identical for read, program and erase operations.
f is a plot of the program and erase threshold voltage distributions of a three-transistor/one-bit three-dimensional EEPROM cell 800. The erase threshold voltage level (Vt1) is assigned to be a positive threshold voltage level of approximately 0.7V with a variation of +/−0.5V for applications having voltage level of the power supply voltage source (VDD) of approximately 1.2V. If the voltage level of the power supply voltage source (VDD) is approximately 1.5V, the positive threshold voltage level (Vt1) is assigned to be approximately 1.0V with a variation of +/−0.5V. The program threshold voltage level (Vt0) is assigned a negative threshold voltage level of approximately −2.0V nominally with a maximum negative threshold voltage level of −1.5V. If it is any more negative, the negative threshold voltage level is a “don't care” state. The three-dimensional NMOS NOR flash transistor M1 is programmed and erased using the Fowler-Nordheim tunneling phenomenon. The first and second three-dimensional switching transistors M0 and M2 insure that there will be no current leakage during programming with the program state is the negative threshold voltage level Vt0. Therefore, there is no need for a program verification operation with the protection of the first and second three-dimensional switching transistors M0 and M2.
a is a schematic diagram of an array 850 of three-transistor/one-bit three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n. Multiple three-transistor/one-bit three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n are arranged in rows and columns. A select gating line SG0, SG1, . . . , SGm is connected to the first and second three-dimensional switching transistors M0 and M2 of each row of the three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n. A word line WL0, WL1, WLm is connected to each of the three-dimensional NMOS NOR flash transistor M1 of each row of the three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n. A bit line Bt0, BL1, . . . , BLn is connected to the drain of the first three-dimensional switching transistors M0 of each column of the three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n. Similarly, a source line SL0, SL1, . . . , SLm is connected to the source of the second three-dimensional switching transistors M2 of each column of the three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n. The bit lines BL0, BL1, . . . , BLn and the source lines SL0, SL1, . . . , SLm are connected to a column control circuit (not shown) to provide the necessary voltages to the bit lines BL0, BL1, . . . , BLn and the source lines SL0, SL1, . . . , SLm for programming, erasing, and reading selected three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n.
A word line biasing transistor MS0, MS1, . . . , MSm is associated with each of the rows of the three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, 800n. The drain of each word line biasing transistor MS0, MS1, MSm is connected to a global bit line GBL that is connected to a column control circuit (not shown). The global bit line GBL transfers the word line biasing voltages for programming, erasing, and reading selected three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n. The source of each word line biasing transistor MS0, MS1, MSm is connected to the associated word line WL0, WL1, . . . , WLm of the row of the three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n. The gate of each word line biasing transistor MS0, MS1, . . . , MSm is connected to the associated select gating line SG0, SG1, . . . , SGm of each row of the three-dimensional EEPROM cells 800aa, . . . , 800am, . . . , 800na, . . . , 800n.
b is a top plan view of an array 850 of three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m.
The structure of three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m is as described for
The source N+ active diffusion layers 803a, 803b, . . . , 803m are connected through the local source line diffusion layers 818a, 818b, . . . , 818m to the drain N+ active diffusion layers 810b-1, 810b-2, . . . , of the second three-dimensional switching transistor M2-a, M2-b, . . . . The bulk P− regions 809a-1, 809a-2, . . . , are formed on the drain N+ active diffusion layers 810b-1, 810b-2, . . . , and the source N+ active diffusion layers 808b-1, 808b-2, . . . , are formed one the bulk P− regions 809a-1, 809a-2, . . . . The metal layers 812 and 814 connect the source N+ active diffusion layers 808b-1, 808b-2, . . . , to the metal layer 815 that forms the source line SLn. The source line SLn is connected to the column control circuit (not shown) that provides the biasing voltages for programming, erasing, and reading to the selected the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m. The source line SLn and the bit line BLn is associated and parallel with one of the columns of the array 850 of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m.
Each row of the blocks 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m is connected to receive the select gating lines SG[0], . . . , SG[J]. The select gating lines SG[0], . . . , SG[J] provide the activating signal for control the application of operating voltage levels to the word lines WL0, WL1, . . . , WLm for programming, erasing, and reading as above described.
The global bit lines GBL0, . . . , GBLK, the bit lines BL[00], . . . , BL[0m], . . . , BL[K0], . . . , BL[Km] and the source lines SL[00], . . . , SL[0m], . . . , SL[K0], . . . , SL[Km] originating with each column of the blocks the blocks 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m is connected to a column control circuit 855 and from the column control circuit 855 to the page buffer 860. The column control circuit 855 generates the necessary operating voltage levels that are to be applied to the global bit lines GBL0, . . . , GBLK, the bit lines BL[00], . . . , BL[0m], . . . , BL[K0], . . . , BL[Km] and the source lines SL[00], . . . , SL[0m], . . . , SL[K0], . . . , SL[Km] for the programming, erasing, and reading of three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m. The page buffer 860 retains the logic states determined during a read operation of selected three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m of each of the blocks 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK. The page buffer 860 further provides the logic states during a write operation of selected three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m of each of the blocks 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK.
In various embodiments, each row of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m defined as a page and each page is further divided into byte units (eight three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m). As illustrated each of the array blocks 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK represent one byte of the page of each row of the array. Each of the byte blocks 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK includes its own global bit lines GBL0, . . . , GBLK, bit lines BL[00], . . . , BL[0m], . . . , BL[K0], . . . , BL[Km] and source lines SL[00], . . . , SL[0m], . . . , SL[K0], . . . , SL[Km]. This permits the programming, erasing, and reading of the array of three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m in groups of byte blocks 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK. These may be a single byte block 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK, a full page of the byte blocks 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK, or the entire array of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m.
The bit lines BL[00], . . . , BL[0m], . . . , BL[K0], . . . , BL[Km] and source lines SL[00], . . . , SL[0m], . . . , SL[K0], . . . , SL[Km] are all set to the ground reference voltage level (0.0 v) to initiate a Fowler-Nordheim Tunneling phenomenon to attract negative charges to the insulating SONOS layer 806 of the charge-retaining transistor M1 shown in
In a programming operation, the ground reference voltage level (0.0V) is applied to the global bit line(s) GBL0, . . . , GBLK of the selected and unselected sub-array block(s) 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK. The select gating line(s) SG[0], . . . , SG[J] for the selected sub-array block(s) 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK have a select gating voltage level that is applied to the word line biasing transistor MS0, MS1, . . . , MSm and the gates of the first and second three-dimensional switching transistors M0 and M2. The word line biasing transistor(s) MS0, MS1, . . . MSm is activated to apply the ground reference voltage level (0.0V) to the word lines WL0, WL1, . . . , WLm and thus to the gates of the charge-retaining transistors M1 of the selected three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m. The select gating biasing voltage level is approximately 18.0V.
The bit lines BL[00], . . . , BL[0m], . . . , BL[K0], . . . , BL[Km] and source lines SL[00], . . . , SL[0m], . . . , SL[K0], . . . , SL[Km] of the selected sub-array block(s) 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK are alt set to the very large programming voltage level to initiate a Fowler-Nordheim Tunneling phenomenon to extract negative charges from the insulating SONOS layer 806 of the charge-retaining transistor M1 shown in
The structure of the each column of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m being associated with is own bit lines BL[00], . . . , BL[0m], . . . , BL[K0], . . . , BL[Km] and source lines SL[00], . . . , SL[0m], . . . , SL[K0], . . . , SL[Km] placed in parallel provides a secure programming operation with no concern for punch through with the charge-retaining transistors M1 of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m. Further the separate select gating line(s) SG[0], . . . , SG[J] for the selected sub-array block(s) 850-00, . . . , 850-0K, . . . , 850-J0, . . . , 850-JK isolates the selected page of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m from the remaining pages of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m to avoid program disturbances and insure that the array of three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m can meet a specification for 1M endurance cycles. The time for writing (programming and erasing) a byte or page of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m is from approximately 1.0 ms to approximately 2.0 ms with a wide power supply voltage range of from 1.8V to 5.5V. An advantage of the three-transistor/one-bit three-dimensional EEPROM cells 800a, 800b, . . . , 800m is the relatively large channel width of the charge-retaining transistor M1 to insure a read speed that is faster than the comparable two-dimensional EEPROM cells.
In some embodiments, a three-dimensional combination nonvolatile memory integrated circuit that includes any number of the three-dimensional flash-based memories including a three-dimensional two-transistor/two-bit NOR array as described in
In various embodiments of the three-dimensional NAND-based NOR nonvolatile memory cell, the three-dimensional charge-retaining transistors are formed as a single cylindrical doped silicon structure. The first drain/source of one of the three-dimensional charge-retaining transistors is formed on an N+ active diffusion layer that may be the source line or bit line of the circuit. The bulk of the one three-dimensional charge-retaining transistor is formed of a first P− diffusion layer that is formed immediately above the first drain/source N+ active diffusion of the one three-dimensional charge-retaining transistor. The merged drain/source of the two three-dimensional charge-retaining transistors as a second N+ active diffusion layer on the first bulk P− diffusion layer. A second bulk P− diffusion layer is formed on the merged drain/source N+ active diffusion layer. A drain/source for the second charge-retaining transistor is formed on the second bulk P− diffusion layer. The drain source of the second charge-retaining transistor is connected to a metal layer that may be the bit line or source line of the circuit depending on the function of the lower N+ active diffusion layer.
Two insulating SONOS layers are formed such that one surrounds the first bulk P− diffusion layer and the other surrounds the second bulk P− diffusion layer to form the charge-retaining layers for the three-dimensional NAND-based NOR nonvolatile memory cell. Two polycrystalline silicon layers are formed such that one of the polycrystalline silicon layer is in line with the first bulk P− diffusion layer and the second polycrystalline silicon layer is in line with the second bulk P− diffusion layer. The two polycrystalline silicon layers are extended to form the word lines for the circuit.
This integration of the three-dimensional NAND-based NOR nonvolatile memory cell as a single cylindrical doped silicon structure allows the three-dimensional charge-retaining transistors to be serially connected to avoid the over-erase during a block-erase operation of an array of the three-dimensional NAND-based NOR nonvolatile memory cells.
While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure.
This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application U.S. Provisional Patent Application Ser. 61/575,126, filed on Aug. 15, 2011, assigned to the same assignee as the present disclosure, and incorporated herein by reference in its entirety.
Number | Date | Country | |
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61575126 | Aug 2011 | US |