Patent Application
20240164100
The present disclosure relates to three-dimensional (3D) memory devices and fabrication methods thereof.
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuits for controlling signals to and from the memory array.
The present disclosure describes embodiments of 3D memory devices and methods for forming the 3D memory devices, as well as systems that include a 3D memory device.
In one example, a method for forming a 3D memory device includes: providing a semiconductor structure, wherein the semiconductor structure comprises a multi-layer stacked structure, a first semiconductor layer over the multi-layer stacked structure, a dielectric layer over the first semiconductor layer, and a substrate over the dielectric layer, wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers and dielectric layers, wherein the semiconductor structure further comprises a plurality of channel structures penetrating the multi-layer stacked structure, the first semiconductor layer, the dielectric layer, and the substrate; removing the substrate to expose the dielectric layer; removing the dielectric layer and a portion of each of the channel structures; and depositing a second semiconductor layer over the first semiconductor layer, wherein the channel structures are electrically coupled to the second semiconductor layer.
In another example, a 3D memory device includes: a multi-layer stacked structure, wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers and dielectric layers; a semiconductor layer over the multi-layer stacked structure; a plurality of channel structures penetrating the multi-layer stacked structure and the semiconductor layer, wherein a first end of each channel structure is located within the semiconductor layer, and wherein the first ends of the channel structures are substantially aligned with one another.
In yet another example, a system includes a controller and a 3D memory device coupled to the controller. The 3D memory device includes: a multi-layer stacked structure, wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers and dielectric layers; a semiconductor layer over the multi-layer stacked structure; and a plurality of channel structures penetrating the multi-layer stacked structure and the semiconductor layer, wherein a first end of each channel structure is located within the semiconductor layer, and wherein the first ends of the channel structures are substantially aligned with one another.
Other aspects, features and various advantages present in some implementations will be readily apparent from the following detailed description, the accompanying drawings, and the claims.
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.
Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but other embodiments may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only conveys the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.
As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.
As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within the value.
As used herein, the term “3D memory device” refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND memory strings) on a laterally oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of the substrate.
As the feature size of the semiconductor manufacturing process becomes smaller, the storage density of the storage device becomes higher, and the application of the 3D memory is born. To increase the storage capacity of the 3D memory, the number of stacked layers and the number of initial channel structures of the stacked structure of the 3D memory are continuously increasing. However, as the number of stacked layers increases, the depth of the channel holes also increases, making it difficult to ensure that the extension depths of each channel hole are the same during the process of etching the channel holes, which in turn leads to increased complexity of the fabrication process and reduced product yield.
In the present disclosure, the portion of each channel structure penetrating into the semiconductor layer can be processed such that an upper end of each channel structure can be aligned horizontally, and a top surface of the semiconductor layer formed over the channel structure is planarized. Therefore, some implementations of the present disclosure can not only make the dielectric layer formed over the semiconductor layer thinner, but can also reduce the aspect ratio of the lead-out contacts that are subsequently formed, penetrating the semiconductor layer, which can expand the range of materials for the lead-out contact, thereby eliminating an additional step of forming connection for the lead-out contact. In some implementations, such features can also lift the restriction on the formation position of the lead-out contacts due to the different depths of gate slit lines, and reduce the difficulty of a subsequent chemical mechanical polishing (CMP) process. As a result, the complexity and cost of the fabrication process can be reduced, and the product yield can be increased in some cases.
In the present disclosure, the 3D memory device can further include a sealing structure disposed at an upper end of each channel structure. The sealing structure can be formed in a channel structure to seal a top portion of the channel structure to prevent other material used in subsequent processes from entering into the channel structure, which may adversely affect an electrical property of the channel structure. As a result, the performance of the device can be improved in some cases.
3D memory device 110 can include a first semiconductor structure 102 including peripheral circuits. The peripheral circuits can be implemented, for example, with advanced logic processes (e.g., technology nodes of 90 nm, 80 nm, 65 nm, 55 nm, 45 nm, 40 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, etc.) to achieve high speed. In some embodiments, the peripheral circuits in first semiconductor structure 102 are implemented using complementary metal-oxide-semiconductor (CMOS) technology. In some embodiments, peripheral circuits in first semiconductor structure 102 can include a controller configured to control the 3D NAND memory device.
In some embodiments, the peripheral circuits include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device 110. For example, the peripheral circuits can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors).
3D memory device 110 can also include a second semiconductor structure 104 including an array of 3D NAND memory strings. Second semiconductor structure 104 can be, for example, a NAND flash memory in which memory cells are provided in the form of an array of NAND memory strings. In some embodiments, depending on the NAND technology (e.g., the number of levels/tiers in the memory stack), a 3D NAND memory string typically consists of 32 to 256 NAND memory cells. 3D NAND memory strings can be organized into pages which are then organized into blocks in which each 3D NAND memory string is connected to a separate line called a bit line (BL). All cells with the same position in the 3D NAND memory string can be connected through the control gates by a word line (WL). In some embodiments, a plane contains a certain number of blocks that are connected through the same bit line. Second semiconductor structure 104 can include one or more planes, and the peripheral circuits that are needed to perform all the read/write/erase operations can be included in first semiconductor structure 102.
3D memory device 110 can further include a bonding interface (not shown) between first and second semiconductor structures 102 and 104. First and second semiconductor structures 102 and 104 can be fabricated separately (and in parallel in some embodiments) such that the thermal budget of fabricating one of first and second semiconductor structures 102 and 104 does not limit the processes of fabricating another one of first and second semiconductor structures 102 and 104. Moreover, a large number of interconnects (e.g., bonding contacts via hybrid bonding) can be formed through the bonding interface to make direct, short, electrical connections between first semiconductor structure 102 and second semiconductor structure 104, as opposed to the long-distance chip-to-chip data bus on the circuit board, thereby eliminating chip interface delay and achieving high-speed I/O throughput with reduced power consumption. Data transfer between the array of 3D NAND memory strings in second semiconductor structure 104 and the peripheral circuits in first semiconductor structure 102 can be performed through the interconnects (e.g., bonding contacts via hybrid bonding) across the bonding interface. Furthermore, by vertically integrating first and second semiconductor structures 102 and 104, the chip size can be reduced, and the memory cell density can be increased.
The relative positions of stacked first and second semiconductor structures 102 and 104 are not limited.
In some embodiments, first structure 202 can include peripheral circuits, and the peripheral circuits can be configured to control signals to and from the memory array of 3D memory device 200. The peripheral circuits can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device 200 including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits can include transistors formed “on” a substrate (not shown), in which the entirety or part of the transistors are formed in the substrate and/or directly on the substrate. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in the substrate as well. The transistors are high-speed with advanced logic processes, according to some embodiments. In some embodiments, the peripheral circuit(s) may further include other circuits compatible with the advanced logic processes including logic circuits, such as processors and programmable logic devices (PLDs), or memory circuits, such as static random-access memory (SRAM) and dynamic RAM (DRAM).
In some embodiments, first structure 202 further includes an interconnect layer (not shown) to transfer electrical signals to and from the peripheral circuits. The interconnect layer can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term “interconnects” can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also known as “intermetal dielectric (IMD) layers”) in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.
First structure 202 can further include a bonding layer (not shown) above the interconnect layer and peripheral circuits. The bonding layer can include bonding contacts and dielectrics electrically isolating the bonding contacts. Bonding contacts can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts and surrounding dielectrics in the bonding layer can be used for hybrid bonding.
Second structure 203 can also include a bonding layer that includes a plurality of bonding contacts and dielectrics electrically isolating bonding contacts. The bonding contacts of second structure 203 can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of the bonding layer of the second structure 203 can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts and surrounding dielectrics in the bonding layer of second structure 203 can be used for hybrid bonding.
Second structure 203 can be bonded on top of first structure 202 in a face-to-face manner. In some embodiments, first and second structures 202 and 203 can be bonded by hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously.
In some embodiments, second structure 203 further includes an interconnect layer (not shown) to transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.
In some embodiments, 3D memory device 200 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in
In some embodiments, second structure 203 includes dielectric layer 218 over multi-layer stacked structure 204. Dielectric layer 218 can include dielectric materials, for example, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, dielectric layer 218 and dielectric layers 208 are composed of the same material. In some embodiments, dielectric layer 218 can be a part of multi-layer stacked structure 204.
As shown in
In some embodiments, referring to
Referring back to
As further shown in
As shown in
3D memory device 200 can include lead-out contacts 222, as shown in
Second structure 203 can further include dielectric layer 224 disposed over semiconductor layer 210. Lead-out contacts 222 can be electrically separated by dielectric layer 224. In some embodiments, lead-out contacts 222 penetrate and extend vertically through dielectric layer 224. In some embodiments, the lower end of a source contact 222 does not extend downwardly beyond the bottom surface of dielectric layer 224. In some embodiments, a portion of dielectric layer 224 penetrates through semiconductor layer 210, and a lead-out contact 222 can penetrate through the portion of dielectric layer 224 that penetrates through semiconductor layer 210 to be connected with word line contact 220. Dielectric layer 224 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.
In the present disclosure, the portion of each channel structure 212 penetrating the semiconductor layer 210 can be processed such that an upper end of each channel structure 212 is aligned horizontally, and a top surface of the semiconductor layer 210 formed over the channel structure 212 is planarized. Therefore, in some cases, the processing can not only make the dielectric layer 224 formed over the semiconductor layer 210 thinner, but can also reduce the aspect ratio of the lead-out contacts 222 that are subsequently formed, penetrating dielectric layer 224 and semiconductor layer 210, which can increase the range of materials that can be used for lead-out contacts 222, thereby eliminating an additional step of forming connection for the lead-out contacts 222. In some cases, such features can also lift the restriction on the formation position of the lead-out contacts 222 due to the different depths of gate slit lines 214, and reduce the difficulty of a subsequent CMP process. As a result, the complexity and cost of the fabrication process can be reduced, and the product yield can be increased in some cases.
As shown in
3D memory device 400 further includes semiconductor plug 428 disposed at an upper end of channel structure 412. In some embodiments, semiconductor plugs 428 are formed by depositing semiconductor layer 410, such that semiconductor plugs 428 are a part of the semiconductor layer 410. Semiconductor plugs 428 can be composed, for example, of polysilicon.
3D memory device 400 further includes sealing structures 430 disposed at an upper end of channel structure 412. Sealing structure 430 is formed in channel structure 412 to seal a top portion of channel structure 412 to prevent other material used in subsequent processes from entering into channel structure 412, which could adversely affect an electrical property of channel structure 412. In some embodiments, sealing structure 430 includes a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
In some embodiments, narrow portion 426 can be used for facilitating formation of sealing structures 430 in channel structure 412. In some embodiments, sealing structure 430 can be formed in channel structure 412 without formation of narrow portion 426.
Referring to
Second structure 503 can be bonded on top of first structure 502 in a face-to-face manner. In some embodiments, first and second structures 502 and 503 can be bonded by hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously.
In general, second structure 503 includes a multi-layer stacked structure 504, a first semiconductor layer 510 over the multi-layer stacked structure 504, a dielectric layer 512 over the first semiconductor layer 510, and a substrate 522 over the dielectric layer 512. The multi-layer stacked structure 504 includes a plurality of alternately stacked conductive layers 506 and dielectric layers 508. Semiconductor structure 500 further includes a plurality of channel structures 514 penetrating multi-layer stacked structure 504, first semiconductor layer 510, dielectric layer 512, and substrate 522.
As shown in
In some embodiments, second structure 503 includes dielectric layer 518 over multi-layer stacked structure 504. Dielectric layer 518 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, dielectric layer 518 can be a part of multi-layer stacked structure 504.
Second structure 503 further includes semiconductor layer 510 above multi-layer stacked structure 504, such that dielectric layer 518 is disposed between multi-layer stacked structure 504 and semiconductor layer 510. In some embodiments, semiconductor layer 510 can be an amorphous silicon layer formed using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, semiconductor layer 510 can be an undoped semiconductor layer. In some embodiments, semiconductor layer 510 can be a doped semiconductor layer (e.g., N-type doped). Semiconductor layer 510 can be doped with any suitable dopants, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contribute free electrons and increase the conductivity of the intrinsic semiconductor. For example, semiconductor layer 510 may be a polysilicon layer doped with N-type dopant(s), such as P, Ar, or Sb.
In some embodiments, channel structures 514 are similar to channel structures 212, such that each channel structure 514 includes a channel hole filled with a dielectric filler layer 312, a semiconductor channel layer 310, and a channel film 302. In some embodiments, the dielectric filler layer 312 includes dielectric materials, such as silicon oxide. The semiconductor channel layer 310 can include silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, the channel film 302 is a composite layer including a tunneling layer 308, a storage layer 306 (also known as a “charge trap layer”), and a blocking layer 304. Channel structure 514 can have a cylinder shape (e.g., a pillar shape). The dielectric filler layer 312, semiconductor channel layer 310, tunneling layer 308, storage layer 306, and blocking layer 304 can be arranged radially from the center of channel structure 514 toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer 308 can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 306 can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer 304 can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, the channel film 302 can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
In some embodiments, channel structure 514 further includes channel plug 520 in the bottom portion (e.g., at the lower end) of channel structure 514. Channel plug 520 can include semiconductor materials (e.g., polysilicon). In some embodiments, channel plug 520 functions as the drain of the NAND memory string.
As shown in
Second structure 503 can further include word line contact 516. Word line contact 516 can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).
At operation 3804 as shown in
At operation 3806 as shown in
After the channel film 302 of a portion of each channel structure 514 is removed, the semiconductor channel layer 310 of the portion of each channel structure 514 that extends beyond the remaining portion of dielectric layer 512 is removed (
Referring to
At operation 3808 as shown in
In some embodiments, laser annealing is performed on semiconductor layer 1002 and semiconductor layer 510 to generate composite semiconductor layer 1102 (
After forming composite semiconductor layer 1102 and etching channel structures 514 to shorten channel structures 514 and align the top surface of each channel structure 514, another dielectric layer may be deposited over the composite semiconductor layer 1102 and lead-out contacts may be formed penetrating the deposited dielectric layer, as described with reference to
Referring to
Then, as indicated by
Next, as indicated by
After planarizing the top surface of dielectric layer 1402, photoresist layer 1502 is deposited over dielectric layer 1402, and trenches 1504 are formed penetrating through photoresist layer 1502 (
Referring to
In some implementations, the manufacturing process as described herein can make the dielectric layer formed over the semiconductor layer (e.g., composite semiconductor layer 1102) thinner. Further, in some implementations, it also can reduce the aspect ratio of the lead-out contacts that are subsequently formed penetrating the semiconductor layer, which can expand the range of materials for the lead-out contact, thereby eliminating an additional step of forming connection for the lead-out contact. In some cases, such features can also lift the restriction on the formation position of the lead-out contacts due to the different depths of gate slit lines, and reduce the difficulty of a subsequent CMP process. As a result, the complexity and cost of the fabrication process can be reduced, and the product yield can be increased in some cases.
In some embodiments, a sealing structure can be formed in a channel structure at a top portion of the channel structure to prevent other material used in subsequent processes from entering into the channel structure, which otherwise may adversely affect an electrical property of the channel structure. A manufacturing process including forming such a seal structure is described below with reference to
The structure in
As shown, multi-layer stacked structure 1804 including alternately stacked conductive layers 1806 and dielectric layers 1808 is disposed over structure 1802. In some embodiments, structure 1802 can include peripheral circuits. Channel structure 1814 penetrating multi-layer stacked structure 1804 can each include a narrow portion 1822. In some embodiments, narrow portion 1822 can be located within semiconductor layer 1810 such that narrow portion 1822 is laterally surrounded by semiconductor layer 1810. Note that each channel structure 1814 in
Referring to
Then, the semiconductor channel layer 310 of a portion of each channel structure 1814 that extends beyond semiconductor layer 1810 is removed (
Next, dielectric layer 2102 is deposited over semiconductor layer 1810 (
Referring to
After forming sealing structure 2202, semiconductor layer 2302 is deposited over semiconductor layer 1810 (
Then, laser annealing can be performed on semiconductor layer 2302 and semiconductor 1810 to form composite semiconductor layer 2404 (
In some embodiments, semiconductor plug 2402 is formed at an upper end of channel structure 1814. In some embodiments, semiconductor plug 2402 is formed as a result of depositing semiconductor layer 2302 and forming composite semiconductor layer 2404, such that semiconductor plug 2402 is a part of composite semiconductor layer 2404.
The structure as shown in
The manufacturing process as described herein can include forming a sealing structure in a channel structure at a top portion of the channel structure to prevent other material used in subsequent processes from entering into channel structure, which otherwise may adversely affect an electrical property of the channel structure. As a result, the complexity and cost of the fabrication process can be reduced, the product yield can be increased, and the performance of the product can be improved in some cases.
In some embodiments, during the manufacturing process, e.g., when etching the channel films of the channel structure, some channel structures may have a risk of collapsing due to their height. To mitigate the risk of collapsing, etching the channel structures to remove a portion of the channel structures that extends beyond the semiconductor layer can be done in multiple stages. In general, in a first stage, after removing the substrate, a blocking layer can be deposited over the dielectric layer which is over the multi-layer stacked structure. The blocking layer can be used as a stop layer to etch the channel structures such that only a portion of each channel structure that extends beyond the blocking layer can be removed. In a second stage, the blocking layer can be removed, and the remaining portion of each channel structure that extends beyond the dielectric layer can be removed. The multi- (e.g., two-) stage etching process is discussed in greater detail with reference to
The structure in
Referring to
Then, blocking layer 2702 is deposited over dielectric layer 2512 (
Next, channel film 302 of a portion of each channel structure 2514 that extends beyond blocking layer 2702 is removed (
Referring to
Then, the dielectric filler layer 312 of a portion of each channel structure 2514 that extends beyond blocking layer 2702 is removed (
Next, the remaining portion of blocking layer 2702 can be removed to expose dielectric layer 2512 (
Referring to
Then, dielectric layer 3202 is etched (
Next, the semiconductor channel layer 310 of a portion of each channel structure 2514 that extends beyond semiconductor layer 2510 is removed (
Referring to
Then, semiconductor layer 3602 is deposited over semiconductor layer 2510 (
In some embodiments, after dielectric layer 3202 is etched as shown in
Next, laser annealing can be performed on semiconductor layer 3602 and semiconductor 2510 to generate composite semiconductor layer 3702 (
The structure as described in
The manufacturing process as described herein can include a multi- (e.g., two-) stage etching process on the channel structures, which reduces a risk of collapsing the channel structures due to their height. As a result, the complexity and cost of the fabrication process can be reduced, the product yield can be increased, and the performance of the product can be improved in some cases.
Memory device 3904 can be any memory device disclosed in the present disclosure, such as 3D memory devices 110, 120, 200, 400. In the present disclosure, memory device 3904 can include channel structures penetrating into a semiconductor layer, where the channel structures can be processed such that an upper end of each channel structure can be aligned horizontally, and a top surface of the semiconductor layer formed over the channel structure is planarized. Therefore, in some implementations, it not only makes the dielectric layer formed over the semiconductor layer thinner, but can also reduce the aspect ratio of the lead-out contacts that are subsequently formed, penetrating the semiconductor layer, which can expand the range of materials for the lead-out contact, thereby eliminating an additional step of forming connection for the lead-out contact. Such features can also lift the restriction on the formation position of the lead-out contacts due to the different depths of gate slit lines, and reduce the difficulty of a subsequent chemical mechanical polishing (CMP) process. As a result, the complexity and cost of the fabrication process can be reduced, and the product yield can be increased in some cases. Furthermore, the 3D memory device 3904 can include a sealing structure disposed at an upper end of each channel structure. The sealing structure can be formed in a channel structure to seal a top portion of the channel structure to prevent other material used in subsequent processes from entering into the channel structure, which may adversely affect an electrical property of the channel structure. As a result, the performance of the device can be improved in some cases.
Memory controller 3906 is coupled to memory device 3904 and host 3908 and is configured to control memory device 3904, according to some embodiments. Memory controller 3906 can manage the data stored in memory device 3904 and communicate with host 3908. In some embodiments, memory controller 3906 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 3906 is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller 3906 can be configured to control operations of memory device 3904, such as read, erase, and program operations.
Memory controller 3906 can also be configured to manage various functions with respect to the data stored or to be stored in memory device 3904 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device 3904. Any other suitable functions may be performed by memory controller 3906 as well, for example, formatting memory device 3904. Memory controller 3906 can communicate with an external device (e.g., host 3908) according to a particular communication protocol. For example, memory controller 3906 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.
Memory controller 3906 and one or more memory devices 3904 can be integrated into various types of storage devices, for example, and can be included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, memory system 3902 can be implemented and packaged into different types of end electronic products. In one example as shown in
According to one aspect of the present disclosure, a method for forming a three-dimensional (3D) memory device includes: providing a semiconductor structure, wherein the semiconductor structure comprises a multi-layer stacked structure, a first semiconductor layer over the multi-layer stacked structure, a dielectric layer over the first semiconductor layer, and a substrate over the dielectric layer, wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers and dielectric layers, wherein the semiconductor structure further comprises a plurality of channel structures penetrating the multi-layer stacked structure, the first semiconductor layer, the dielectric layer, and the substrate; removing the substrate to expose the dielectric layer; removing the dielectric layer and a portion of each of the channel structures; and depositing a second semiconductor layer over the first semiconductor layer, wherein the channel structures are electrically coupled to the second semiconductor layer.
In some embodiments, the method further includes processing each of the channel structures to form a narrow portion in each particular one of the channel structures, wherein the narrow portion of each particular one of the channel structures has a smaller critical dimension than other portions of the particular one of the channel structures.
In some embodiments, the method further includes forming a respective semiconductor plug within the narrow portion of each particular one of the channel structures.
In some embodiments, each of the channel structures comprises a dielectric filler layer, a semiconductor channel layer, and a channel film, where the channel film comprises a tunneling layer, a storage layer, and a blocking layer.
In some embodiments, removing the dielectric layer and the portion of each of the channel structures includes: etching the channel structures and the dielectric layer to remove a portion of the dielectric layer and a portion of the channel film of each channel structure; and removing a portion of the semiconductor channel layer of each channel structure that extends beyond a remaining portion of the dielectric layer.
In some embodiments, removing the dielectric layer and the portion of each of the channel structures further includes: etching the dielectric filler layer of each channel structure and the remaining portion of the dielectric layer, such that a remaining portion of the semiconductor channel layer of each channel structure extends beyond the first semiconductor layer.
In some embodiments, removing the dielectric layer and the portion of each of the channel structures further includes etching the dielectric filler layer of each channel structure and the remaining portion of the dielectric layer, such that a top surface of a remaining portion of the dielectric filler layer of each channel structure is below a top surface of the first semiconductor layer.
In some embodiments, removing the dielectric layer and the portion of each of the channel structures includes: depositing a blocking layer over the dielectric layer, wherein a portion of one or more of the channel structures extends beyond the coating layer; and removing a portion of the one or more of the channel structures that extends beyond the blocking layer.
In some embodiments, removing the dielectric layer and the portion of each of the channel structures further includes: removing the blocking layer to expose the dielectric layer; removing the dielectric layer to expose the first semiconductor layer; and etching a remaining portion of each of the channel structures such that the remaining portion of the semiconductor channel layer of each channel structure extends beyond the first semiconductor layer.
In some embodiments, depositing the second semiconductor layer over the first semiconductor layer comprises depositing the second semiconductor layer using a chemical vapor deposition (CVD) method.
In some embodiments, before depositing the second semiconductor layer over the first semiconductor layer, the method further includes: depositing a dielectric layer over the first semiconductor layer such that a dielectric material of the dielectric layer partially fills each of the channel structures; and etching the dielectric layer and the dielectric material partially filling each of the channel structures to form a dielectric sealing structure in each of the channel structures.
In some embodiments, the method further includes performing laser annealing of the first semiconductor layer and the second semiconductor layer to generate a composite semiconductor layer, wherein a remaining portion of each of the channel structures penetrates into the composite semiconductor layer.
According to another aspect of the present disclosure, a 3D memory device includes: a multi-layer stacked structure, wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers and dielectric layers; a semiconductor layer over the multi-layer stacked structure; a plurality of channel structures penetrating the multi-layer stacked structure and the semiconductor layer, wherein a first end of each channel structure is located within the semiconductor layer, and wherein the first ends of the channel structures are substantially aligned with one another.
In some embodiments, each particular one of the channel structures comprises a narrow portion, wherein the narrow portion of each particular one of the channel structures is disposed at the first end of the particular one of the channel structures and is surrounded laterally by the semiconductor layer, wherein the narrow portion of each particular one of the channel structures has a smaller critical dimension than other portions of the particular one of the channel structures.
In some embodiments, the 3D memory device further comprises a plurality of first semiconductor plugs disposed at a second end of each particular one of the channel structures.
In some embodiments, each of the channel structures comprises a dielectric filler layer, a semiconductor channel layer, and a channel film, and the channel film comprises a tunneling layer, a storage layer, and a blocking layer.
In some embodiments, a top surface of the dielectric filler layer of each channel structure is below a top surface of the semiconductor channel layer and the channel film of each channel structure.
In some embodiments, a dielectric sealing structure is disposed within each of the channel structures at the first end of each of the channel structures, and wherein a respective second semiconductor plug is disposed over the dielectric sealing structure in each of the channel structures.
According to another aspect of the present disclosure, a system includes a peripheral circuit and a 3D memory device coupled to the peripheral circuit. The 3D memory device includes: a multi-layer stacked structure, wherein the multi-layer stacked structure comprises a plurality of alternately stacked conductive layers and dielectric layers; a semiconductor layer over the multi-layer stacked structure; and a plurality of channel structures penetrating the multi-layer stacked structure and the semiconductor layer, wherein a first end of each channel structure is located within the semiconductor layer, and wherein the first ends of the channel structures are substantially aligned with one another.
In some embodiments, each particular one of the channel structures comprises a narrow portion, wherein the narrow portion of each particular one of the channel structures is disposed at the first end of the particular one of the channel structures and is surrounded laterally by the semiconductor layer, wherein the narrow portion of each particular one of the channel structures has a smaller critical dimension than other portions of the particular one of the channel structures.
In some embodiments, the 3D memory device further comprises a plurality of first semiconductor plugs disposed at a second end of each particular one of the channel structures.
In some embodiments, the peripheral circuit comprises a complementary metal-oxide-semiconductor (CMOS) circuitry.
In some embodiments, each of the channel structures comprises a dielectric filler layer, a semiconductor channel layer, and a channel film, where the channel film comprises a tunneling layer, a storage layer, and a blocking layer.
In some embodiments, a top surface of the dielectric filler layer of each channel structure is below a top surface of the semiconductor channel layer and the channel film of each channel structure.
In some embodiments, a dielectric sealing structure is disposed within each of the channel structures at the first end of each of the channel structures, and wherein a respective second semiconductor plug is disposed over the dielectric sealing structure in each of the channel structures.
The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, and/or without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The Summary and Abstract sections may set forth one or more but not all examples of embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.
The breadth and scope of the present disclosure should not be limited by any of the above-described example embodiments. Accordingly, other implementations also are within the scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211461085.4 | Nov 2022 | CN | national |
This application is a continuation of International Application No. PCT/CN2023/079247, filed on Mar. 2, 2023, which claims priority to Chinese Patent Application No. 202211461085.4, filed on Nov. 16, 2022. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2023/079247 | Mar 2023 | US |
| Child | 18296222 | US |
