Patent Application
20060012931
1. Field of the Invention
This invention pertains generally to electrical switching apparatus and, more particularly, to three-pole circuit interrupters responsive to arcing faults.
2. Background Information
Circuit interrupters, such as molded case circuit breakers, include at least one set of separable contacts per pole. For example, a first contact is fixed within the molded case housing and a second movable contact is coupled to an operating mechanism. These separable contacts are in electrical communication with either the line or the load coupled to the circuit breaker. The operating mechanism moves the movable contact between a first, open position wherein the movable contact is spaced from the fixed contact, and a second, closed position wherein the fixed and movable contacts are in contact and electrical communication. The operating mechanism may be operated manually or automatically by a trip mechanism.
Circuit breaker protective trip units may provide about four levels of protection: overload, short delay, instantaneous and ground protection. The most serious type of fault within a three-phase switchgear assembly is an arcing fault. The energy absorbed by the resulting gas plasma caused by the product of arc voltage times arc current over time can result in a rapid build up of internal pressure. This pressure can compromise the switchgear assembly's ability to contain the resulting gas without rupturing. The instantaneous protection, which has no deliberate delay, is intended to minimize equipment damage due to such an arcing fault. However, if the electrical system is such that during a phase-to-phase or phase-to-ground arcing fault the resulting current is below the instantaneous trip level, then a short delay trip will occur. In this instance, the corresponding non-instantaneous, short delay is very undesirable.
Accordingly, there is room for improvement in three-pole circuit interrupters.
These needs and others are met by the present invention, which provides an additional protective function, namely, “intelligent” instantaneous protection, that responds to an arcing fault, such as a phase-to-phase or phase-to-ground arcing fault.
In accordance with one aspect of the invention, a three-pole circuit interrupter for a three-phase load circuit including three phases and a line cycle comprises: three poles, each of the poles comprising: a set of separable contacts for a corresponding one of the phases of the three-phase load circuit, and a current sensor adapted to determine a plurality of current samples for the corresponding one of the phases during the line cycle; an operating mechanism adapted to open and close the sets of separable contacts; and a trip mechanism cooperating with the operating mechanism, the trip mechanism adapted to determine three current values from the current samples of the three poles during at least about one half of the line cycle and to analyze differences among the current values of the poles, in order to detect a phase-to-phase arcing fault or a phase-to-ground arcing fault, and to responsively trip open the sets of separable contacts.
The trip mechanism may include a processor and a routine determining that at least one of the current values is above a first reference, and responsively analyzing the differences among the current values of the poles during the at least about one half of the line cycle. The routine may determine magnitudes of the current samples of the poles and sum the magnitudes to provide a sum as a corresponding one of the current values for each of the poles for the at least about one half of the line cycle.
The routine may be adapted to detect the phase-to-phase arcing fault between a pair of the phases of the three-phase load circuit associated with the two of the poles and to responsively trip open the sets of separable contacts due to the detected phase-to-phase arcing fault.
The trip mechanism may include a processor and a routine adapted to determine magnitudes of the current samples, to sum the magnitudes to provide a sum as a corresponding one of the current values for each of the poles for about one half of the line cycle, and to examine the sum for each of the poles after the about one half of the line cycle. The routine may be adapted to detect the phase-to-phase arcing fault between a pair of the phases of the three-phase load circuit and to responsively trip open the sets of separable contacts due to the detected phase-to-phase arcing fault.
The three-phase load circuit may further include a ground. The routine may be adapted to detect the phase-to-ground arcing fault between one of the phases of the three-phase load circuit and the ground and to responsively trip open the sets of separable contacts due to the detected phase-to-ground arcing fault.
The routine may integrate or sum absolute values of the current samples of the poles to provide the current values during the at least one half of the line cycle. The current values may be sums, and the routine may analyze differences among the sums during one half of the line cycle.
Each of the current values may be a sum of a plurality of absolute values of corresponding ones of the current samples during at least about one half of the line cycle, an average of a sum of a plurality of absolute values of corresponding ones of the current samples during at least about one half of the line cycle, a peak value of corresponding ones of the current samples during at least about one half of the line cycle, an RMS value of corresponding ones of the current samples during at least about one half of the line cycle, or a sum of the squares of corresponding ones of the current samples during at least about one half of the line cycle.
A full understanding of the invention can be gained from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which:
The present invention is described in association with a three-pole circuit breaker, although the invention is applicable to a wide range of circuit interrupters having three or more poles. Examples of circuit breakers are disclosed in U.S. Pat. Nos. 4,752,853; 5,270,898; and 5,875,088, which are incorporated by reference herein.
Referring to
At least about six current samples may be determined per half-cycle of the line cycle 8 for each of the three phases 6. In this example, the current samples may be taken every about 30 degrees as referenced to one or more of the phases 6.
As another example, if four current samples are taken per half-cycle of the line cycle 8, then the current samples may be taken every about 45 degrees as referenced to one of the phases 6. The current samples are taken about simultaneously with respect to one of the three phases 6. The current samples need not be synchronized to zero crossings of any of the three phases. They are, however, synchronized to the line frequency.
Continuing to refer to
The three sets of separable contacts 12A,12B,12C are electrically interconnected between three line terminals 20 and three load terminals 22 for movement between a closed position (not shown) and an open position (as shown in
The trip circuit 18 interfaces the CTs 14A, 14B, 14C for sensing the line electrical currents. Although not required, the trip circuit 18 may also interface a sensor, such as current transformer (CT) 14G, for sensing the ground electrical current. The trip circuit 18 includes a suitable current-to-voltage (I/V) interface 26 for receiving the sensed current signals 28 from the CTs 14A,14B,14C,14G, the processor 15 (e.g., including a microprocessor (μP)) and a trip coil 30 controlled by such processor. The sensed current signals 28 include a sensed ground current 28G and the sensed phase currents 28A,28B,28C, which may represent both normal and fault currents in the load circuit 4. In the event that the ground fault trip function is not employed, then the CT 14G for the signal 28G is removed and a jumper or switch (not shown) is employed to ground signal 28G.
The processor 15 employs a multiplexer (MUX) to select the sensed signals from the interface 26; an analog-to-digital (A/D) converter to convert the sensed signals to corresponding digital values; the microprocessor (μP) to receive the digital values from the A/D; and a digital input/output circuit (I/O) to input or output various signals, such as trip signal 32 at output port 34.
The operating mechanism 16 has a first state (e.g., closed) and a second state (e.g., open or tripped) which corresponds to the open position of the separable contacts 12A,12B,12C. The CTs 14A,14B,14C sense the electrical current, such as current 24, flowing through those separable contacts. The μP of the processor 15 employs the digital values of the sensed signals from the A/D to generate the trip signal 32 at output 34 for tripping the operating mechanism 16 through trip coil 30 to the tripped state to move the separable contacts 12A,12B,12C to the open position.
Referring to
In this example, the normalized or per unit rated current (e.g., normally expressed as an RMS value) of the CB 2 is 1.000RMS or 1.414PEAK. The fast acting, intelligent, instantaneous trip function algorithm is as follows. If an instantaneous current sample of the three-phase currents Ia 46, Ib 48 or Ic 50 is greater than about 3 (which is greater than the peak value of a 2RMS per unit sinusoidal wave), then the magnitudes of each of the three-phase currents Ia 46, Ib 48 and Ic 50 are summed for about one half-cycle (i.e., about one half the time of the line cycle 8 of
In this example, sampling is done about every 30 degrees of the line cycle 8 (e.g., about 12 times per line cycle or about 6 times per one half-cycle). Then, after one half-cycle, the three sums are examined. If two of the sums are about equal and above a first reference (e.g., about 14), and the other remaining sum is below a second reference (e.g., about 7), then the CB 2 is tripped due to a detected phase-to-phase arcing fault, such as 42 (
Table 1, below, shows the three sums for six samples during a one half-cycle period. Here, after the sixth current sample, both of the |Ia| sum and the |Ib| sum are equal (e.g., 32.29) and are above the first reference (e.g., about 14), and the other remaining sum |Ic| (e.g., 5.28) is below a second reference (e.g., about 7). Hence, the CB 2 is tripped due to a detected phase-to-phase arcing fault, such as 42 of
The detection of a phase-to-ground arcing fault, such as 44 (
Table 2, below, shows the three sums for six samples during a one half-cycle period. Here, after the sixth current sample, both of the |Ib| sum and the |Ic| sum are equal (e.g., 5.28) and are below the second reference (e.g., about 7), and the other remaining sum |Ia| (e.g., 31.67) is above the first reference (e.g., about 14). Hence, the CB 2 is tripped due to the detected phase-to-ground arcing fault 44.
Referring to
After 85B, at 86, an auction8 routine finds the largest sum of eight squared current values for the three phases 6, and any data that needs written to non-volatile random access memory (NVRAM) (not shown) is written at this time. Next, at 90, an instantaneous protection routine is executed. This routine compares the highest sum of squared current values for the phases 6 with a corresponding instantaneous setpoint value. Then, at 92 and 94, a short delay interlock and protection routine and a ground protection routine, respectively, are executed. The short delay routine 92 compares the highest sum of squared current values for the phases 6 with the short delay setpoint and, if exceeded, a pickup occurs and a tally value is added to a short time tally (STALLY) value which is, in turn, compared with the short time setting and, if greater, a short flag is set for eventual tripping. A similar set of sequences occurs for the ground fault routine 94. At 96, a trip routine is executed which generates the trip signal 32 at output 34 of
At 99A, a flag (FLG8) is tested to determine if eight current samples are completed. If not, then step 84 is repeated. Otherwise, at 99B, a phase 14T long delay protection routine is executed. This is followed by a phase IEC/IEEE long delay protection routine, at 99C of
Next, at 102, a flag (FLG64) is tested to determine if 64 current samples are completed. If not, then step 84 is repeated. Otherwise, at 104, the STATUS/LDPU or long delay pickup LED (not shown) is serviced by driving a latch (not shown) external to the μP of processor 15. Next, at 106, if self calibration is selected by a jumper (not shown) at the factory, then a self calibration routine, at 108, calculates calibration values for the phase and ground sensed current signals 28 and stores these in NVRAM (not shown). The calibration procedure employs precision current sources (three phases and ground) (not shown) and is automatically performed by the trip circuit 18. After the self calibration routine is executed at 108, the initialization is repeated at 80. Otherwise, if there is no self calibration, then at 110 and 112, auction64 and long delay protection routines, respectively, are executed. These routines find the highest sum of 64 squared current values for the phases 6 and use this value for long delay pickup and long time tally developed values. At 114, a trip routine is executed which generates the trip signal 32 at output 34 of
Next, at 118, a flag (FLG256) is tested to determine if 256 current samples are completed. If not, then step 84 is repeated. Otherwise, at 120, the STATUS/LDPU LED is again updated as at 104. Then, at 122, 123 and 124, refresh routines, a LED4 routine and over-temperature protection routines, respectively, are executed. The refresh routines refresh key protection parameters such as switch settings. At 126, a trip routine is executed which generates the trip signal 32 at output 34 of
Referring to
In this example, the routine 132 executes about every 45 degrees of the line cycle 8 of
At 140, miscellaneous routines (e.g., an accessory bus INCOM routine, SPI_Master communications, read jumper routine, read interlock-in and increment COUNT256) are executed which read an interlock input signal (not shown) at an input port (not shown) of
Next, at 142, if a multiple of four current samples has not been obtained, as determined from the value of the counter (COUNT256) of step 140, then a return from interrupt (RTI) is executed at 172 (
Next, at 156, a sum, Sum64, is set equal to the previous value of that sum plus the sum, Sum8, of step 152. Then, at 157 (
Next, at 160, if a multiple of 64 current samples have not been obtained, as determined from the value of the counter (COUNT256) of step 140, then a return from interrupt (RTI) is executed at 172. Otherwise, at 162, the flag FLG64 is set. Then, at 163A, the SPI output buffer of a serial port (not shown) is prepared and, at 163B, the SPI input of that serial port is buffered. At 164, if a multiple of 256 current samples have not been obtained, as determined from the value of the counter (COUNT256) of step 140, then a return from interrupt (RTI) is executed at 172. Otherwise, at 166, the flag FLG256 is set. At 168, a counter COUNT8 is incremented (for use by units with a multiplexed display (not shown)) after which, at 170, a flag (BLINKFLG), which is used to control a status LED (not shown), is complemented. Finally, at 172, the return from interrupt (RTI) is executed.
If either of the tests at 184 or 186 failed, then execution resumes at 200. If the test at 182 failed, then, at 188, the value ARCSUMA is compared to the value ARCSUMC. If these values are about equal (e.g., as discussed above in connection with step 182), then, at 190, it is determined if the value ARCSUMA is greater than or equal to a reference (e.g., as discussed above in connection with step 184). If so, then, at 192, it is determined if the value ARCSUMB is less than a reference (e.g., as discussed above in connection with step 186). If so, then a trip is generated at 216 by setting the trip signal 32 at output 34 of
If either of the tests at 190 or 192 failed, then execution resumes at 200. If the test at 188 failed, then, at 194, the value ARCSUMB is compared to the value ARCSUMC. If these values are about equal (e.g., as discussed above in connection with step 182), then, at 196, it is determined if the value ARCSUMB is greater than or equal to a reference (e.g., as discussed above in connection with step 184). If so, then, at 198, it is determined if the value ARCSUMA is less than a reference (e.g., as discussed above in connection with step 186). If so, then a trip is generated at 216 by setting the trip signal 32 at output 34 of
If any of the tests at 194, 196 or 198 failed, then execution resumes at 200 for the arc flash phase-to-ground portion 200 of the Arc Flash routine 85. At 202, it is determined if the value ARCSUMA is greater than a suitable first reference (e.g., about three times rated current in this example). If so, then, at 204, it is determined if the values ARCSUMB and ARCSUMC are both less than a second reference (e.g., about one times rated current in this example). If so, then a trip is generated at 216 by setting the trip signal 32 at output 34 of
If the test at 202 failed, then execution resumes at 206, which determines if the value ARCSUMB is greater than the first reference (e.g., as discussed above in connection with step 202). If so, then, at 208, it is determined if the values ARCSUMA and ARCSUMC are both less than a second reference (e.g., as discussed above in connection with step 204). If so, then a trip is generated at 216 by setting the trip signal 32 at output 34 of
If the test at 206 failed, then execution resumes at 210, which determines if the value ARCSUMC is greater than the first reference (e.g., as discussed above in connection with step 202). If so, then, at 212, it is determined if the values ARCSUMA and ARCSUMB are both less than the second reference (e.g., as discussed above in connection with step 204). If so, then a trip is generated at 216 by setting the trip signal 32 at output 34 of
The routine 220 begins at 222 after which it is determined, at 224, if four current samples for pole 10A (
Although a three-pole circuit breaker 2 (
Although a phase-to-ground fault 44 (
Although a grounded power source 38 (
Although a grounded WYE power source 38 (
As a refinement of step 139 of the interrupt routine 132 of
As shown in
Referring to
As shown in
As shown in
As shown in
As an alternative to Examples 3 and 4, in which a first reference (e.g., about 7) and a second reference (e.g., about 14) are employed with six samples per half cycle, if, for example, eight samples per half cycle were employed, then the first and second references would be adjusted by a factor of 8/6 to provide the first reference (e.g., about 9.33) and the second reference (e.g., about 18.67) for this example.
As an alternative to Examples 3, 4 and 15, if the average value of the sum was employed, then the first and second references would be adjusted by the count of the samples (i.e., 6 for Examples 3 and 4; 8 for Example 15). In this example, the first and second references are independent of the count of samples, such that the first reference is about 1.167 (e.g., about 7/6 or about 9.33/8) and the second reference is about 2.33 (e.g., about 14/6 or about 18.67/8).
As an alternative to Examples 3, 4, 15 and 16, any suitable values of the first and second references and/or counts of the samples and/or period of the sampling may be employed.
Although the trip circuit 18 includes a processor 15, it will be appreciated that a combination of one or more of analog, digital and/or processor-based circuits may be employed.
While specific embodiments of the invention have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the invention which is to be given the full breadth of the claims appended and any and all equivalents thereof.
