Patent Application
20130133713
The subject matter disclosed herein relates generally to terminal configurations of a thin film photovoltaic module having a plurality of thin film photovoltaic cells. More particularly, the subject matter disclosed herein relates to a three terminal configuration of a thin film photovoltaic device.
Thin film photovoltaic (PV) modules (also referred to as “solar panels”) based on cadmium telluride (CdTe) paired with cadmium sulfide (CdS) as the photo-reactive components are gaining wide acceptance and interest in the industry. CdTe is a semiconductor material having characteristics particularly suited for conversion of solar energy to electricity. For example, CdTe has an energy bandgap of about 1.45 eV, which enables it to convert more energy from the solar spectrum as compared to lower bandgap semiconductor materials historically used in solar cell applications (e.g., about 1.1 eV for silicon). Also, CdTe converts radiation energy in lower or diffuse light conditions as compared to the lower bandgap materials and, thus, has a longer effective conversion time over the course of a day or in cloudy conditions as compared to other conventional materials. The junction of the n-type layer and the p-type layer is generally responsible for the generation of electric potential and electric current when the CdTe PV module is exposed to light energy, such as sunlight. Specifically, the cadmium telluride (CdTe) layer and the cadmium sulfide (CdS) form a p-n heterojunction, where the CdTe layer acts as a p-type layer (i.e., an electron accepting layer) and the CdS layer acts as a n-type layer (i.e., an electron donating layer).
The photovoltaic modules are typically deployed in the field by connected a plurality of modules in series to form a “string” of PV modules. The fewer strings that can be used, the lower the total balance of the system costs. However, the number of solar modules in each string are limited in total voltage per string. With respect to CdTe PV modules, which have relatively high voltage per cell due to the relatively high band gap of CdTe, fewer modules can be linked together in each string than may be desired.
Thus, a need exists for photovoltaic devices having lower voltages, particularly with respect to CdTe photovoltaic devices.
Aspects and advantages of the invention will be set forth in part in the following description, or may be obvious from the description, or may be learned through practice of the invention.
Thin film photovoltaic devices are generally provided according to one embodiment. The device can include, for example, a first submodule is defined by a first plurality of photovoltaic cells between a first bus bar and a joint bus bar and a second submodule is defined by a second plurality of photovoltaic cells between a second bus bar and the joint bus bar. A common insulation layer can be positioned over first submodule to extend from the joint bus bar to the first bus bar. A first lead can be positioned on the common insulation layer and electrically connected to the first bus bar. A second lead can be positioned on the common insulation layer and electrically connected to the joint bus bar. A linking insulation layer can be positioned over the first submodule, the second submodule, and the joint bus bar such that the linking insulation layer extends from the first bus bar to the second bus bar. A conductive link can be positioned on the linking insulation layer and electrically connected to the first bus bar and the second bus bar, but is electrically isolated from the joint bus bar.
Methods are also generally provided for forming a pair of electrical leads on a thin film photovoltaic device having a first submodule defined by a first plurality of photovoltaic cells on a transparent superstrate and a second submodule defined by a second plurality of photovoltaic cells on the transparent superstrate. In one embodiment, the method can include applying a common insulation layer over the first plurality of photovoltaic cells such that the common insulation layer extends from a common terminal cell to a first terminal cell. A common lead can then be applied onto the common insulation layer from the common terminal cell to the first terminal cell such that the common lead is electrically isolated from the thin film stack. A joint bus bar can be applied onto the common terminal cell such that the joint bus bar is electrically connected to the common lead and to the common terminal cell. A linking insulation layer can be applied over the first plurality of photovoltaic cells, the second plurality of photovoltaic cells, and the joint bus bar such that the linking insulation layer extends from the first terminal cell to the second terminal cell. A conductive link can then be applied on the linking insulation layer from the first terminal cell to the second terminal cell such that the conductive link is electrically isolated from the thin film stack and the joint bus bar. A first bus bar can be applied on the first terminal cell such that the first bus bar is electrically connected to the first terminal cell, the conductive link, and the common lead. A second bus bar can be applied on the second terminal such that the second bus bar is electrically connected to the second terminal cell and the conductive link such that the conductive link electrically connects the first terminal to the second terminal. And, the common lead can be severed to form a first lead and a second lead, with the first lead being electrically connected to the first terminal and the second terminal, and the second lead being electrically connected to the common terminal.
These and other features, aspects and advantages of the present invention will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
A full and enabling disclosure of the present invention, including the best mode thereof, directed to one of ordinary skill in the art, is set forth in the specification, which makes reference to the appended figures, in which:
Repeat use of reference characters in the present specification and drawings is intended to represent the same or analogous features or elements.
Reference now will be made in detail to embodiments of the invention, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation of the invention, not limitation of the invention. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the invention. For instance, features illustrated or described as part of one embodiment can be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present invention covers such modifications and variations as come within the scope of the appended claims and their equivalents.
In the present disclosure, when a layer is being described as “on” or “over” another layer or substrate, it is to be understood that the layers can either be directly contacting each other or have another layer or feature between the layers, unless otherwise stated. Thus, these terms are simply describing the relative position of the layers to each other and do not necessarily mean “on top of” since the relative position above or below depends upon the orientation of the device to the viewer. Additionally, although the invention is not limited to any particular film thickness, the term “thin” describing any film layers of the photovoltaic device generally refers to the film layer having a thickness less than about 10 micrometers (“microns” or “μm”).
It is to be understood that the ranges and limits mentioned herein include all ranges located within the prescribed limits (i.e., subranges). For instance, a range from about 100 to about 200 also includes ranges from 110 to 150, 170 to 190, 153 to 162, and 145.3 to 149.6. Further, a limit of up to about 7 also includes a limit of up to about 5, up to 3, and up to about 4.5, as well as ranges within the limit, such as from about 1 to about 5, and from about 3.2 to about 6.5.
Thin film photovoltaic devices are generally provided having three terminals, along with methods of making the same. Generally, the device includes a joint bus bar electrically connected to a terminal cell(s) of both a first submodule and a second submodule, such that the two submodules can simultaneously utilize the joint bus bar. As such, the device can utilize the joint bus bar to minimize the surface area dedicated to the center terminal cell(s) in the device. Additionally, splitting the PV device into two submodules can decrease the module voltage when compared to a same size module using a single module over the entire PV device. The two submodules can be, in one particular embodiment, connected in parallel.
For example,
As stated, the device 10 defines individual photovoltaic cells 11 separated by scribes 26 to collectively form the first plurality 32 and second plurality 42 of serially connected cells 11 of, respectively, the first submodule 30 and the second submodule 40. Specifically, the individual photovoltaic cells 11 are electrically connected together in series in each submodule 30, 40. Each plurality 32, 42 of serially connected photovoltaic cells 11 are between a terminal cell 36, 46 and dead cells 34, 44, respectively. As show, the dead cells 34, 44 are adjacent to each other and are electrically connected to the joint bus bar 52, while the terminal cells 36, 46 are located on opposite edges of the device 10. It is noted that the dead cells 34, 44 may be combined together to form a single cell, in certain embodiments. However, it may be desired to reverse the terminals such that the terminal cells are located adjacent to each other and electrically connected to the joint bus bar with the dead cells located on opposite edges of the device.
Additionally, a common insulation layer 64 extends from the first terminal cell 36 to the joint bus bar 52. A first conductive lead 66 is positioned on the common insulation layer 64 and is electrically connected to the first terminal 38, and a second conductive lead 68 is positioned on the common insulation layer 64 and is electrically connected to the joint bus bar 52. Thus, the common insulation layer 64 electrically isolates the conductive leads 66, 68 from the underlying photovoltaic cells 11. The first and second conductive leads 66, 68 respectively terminate at the first and second leads 67, 69 for collection of the DC current produced by the device 10 from both the first and second submodules 30, 40.
As stated, the conductive link 62 is electrically connected to the first terminal 38 and the second terminal 48. In the embodiment shown, for example, the conductive link 62 extends over the first terminal 38 and the second terminal 48 and is connected thereto. However, in other embodiments, the first terminal 38 and the second terminal 48 can be applied onto and positioned over the conductive link 62 that extends over the terminal cells 36, 46, respectively. Likewise, the first conductive lead 66 is electrically connected to the first terminal 38, and a second conductive lead 68 is electrically connected to the joint bus bar 52. In the embodiment shown, for example, the first conductive lead 66 extends over the first terminal 38 to be connected thereto, and the second conductive lead 68 extends over the second terminal 48 to be connected thereto. However, in other embodiments, the first terminal 38 and the second terminal 48 can be applied onto and positioned over the first conductive lead 66 and the second conductive lead 68, respectively.
The insulating layers 60, 64 generally include any insulating material that can prevent electrical conductivity therethrough. In one embodiment, each of the insulating layers 60, 64 can be an insulating polymeric film coated on both of its surfaces with an adhesive coating. The adhesive coating can allow for adhesion of the insulating layer 60, 64 to the underlying layers of the device (e.g., the photovoltaic cells 11) and for the adhesion of the conductive strips 62, 66, 68 to its respective insulating layer 60, 64. For example, each of the insulating layers 60, 64 can include a polymeric film of polyethylene terephthalate (PET) having an adhesive coating on either surface. The adhesive coating can be, for example, an acrylic adhesive, such as an acrylic adhesive.
Each of the insulating layers 60, 64 can have a thickness in the z-direction suitable to prevent electrical conductivity from the underlying thin film layers, particularly the back contact 22, to any subsequently applied layers.
The first and second conductive leads 66, 68, in one embodiment, can be applied as a continuous strip over the common insulating layer 64, and then severed to produce the first lead 67 and a second lead 69, as shown in
Through the configuration shown in
For example, the leads (i.e., the first and second leads 66, 68) and the conductive link 62 can be spaced apart a distance that is at least about 10% of the total longitudinal length of the device 10 (i.e., if the longitudinal length of the device is 1 meter, then the leads 66, 68 and the conductive link 62 can be 10 cm apart or more in the longitudinal direction), such as about 25% to about 90%.
A junction box (not shown) can also be included in the device and can be configured to electrically connect the photovoltaic device 10 by completing the DC circuit, such as by connected to the first and second leads 67, 69.
As stated, the joint bus bar can electrically connect adjacent terminal cells (e.g., the dead cells 34, 44) or a single cell 34, 44 acting as a terminal cell for both the first submodule 30 and second submodule 40.
In the embodiments of
Referring specifically now to the embodiments of
The first terminal 38 is electrically connected to the first terminal cell 36 of the first submodule 30, and a second terminal 48 is electrically connected to the second terminal cell 46 of the second submodule 40. As such, the first terminal 38 and the second terminal 48 serve as the opposite terminals to the joint bus bar 52 in the device 10.
As stated,
In the embodiment shown in
In the embodiment shown in
Like the embodiment of
In the embodiment shown in
As shown in
For example, the laser scribing process can entail defining a first isolation scribe 21 (also know as a “P1 scribe”) from the substrate 12 through the photo reactive layers (i.e., the n-type window layer 18 and the absorber layer 20), including the underlying layers (i.e., through the TCO layer 14). For example, the first isolation scribe 21 can be formed via laser scribing through the transparent substrate 12 to remove the TCO layer 14, the RTB layer 16, the n-type window layer 18, and the absorber layer 20 prior to application of the back contact layer 22. The first isolation scribe line 21 can then filled with a nonconductive material before application of the back contact layer 22 in order to ensure that the TCO layer 14 is electrically isolated between adjacent photovoltaic cells 11. For example, the first isolation scribe 21 can be filled using a photoresist development process wherein a liquid negative photoresist (NPR) material is coated onto the absorber layer 20 by spraying, roll coating, screen printing, or any other suitable application process. The substrate 12 is then exposed to light from below such that the NPR material in the first isolation scribes 21 (and any pinholes in the absorber layer 20) are exposed to the light, causing the exposed NPR polymers to crosslink and “harden.” The substrate 12 can then be “developed” in a process wherein a chemical developer is applied to the absorber layer 20 to dissolve any unhardened NPR material. In other words, the NPR material that was not exposed to the light is washed away from the absorber layer 20 by the developer, leaving the first isolation scribes 21 filled with the NPR material.
In one embodiment, after filling the first isolation scribes 21, a graphite layer can be applied onto the absorber layer 20 for form part of the back contact layer 22.
A series connecting scribe 23 (also known as a “P2 scribe”) can then be laser formed from the graphite layer (if present) through absorber layer 20 to the TCO layer 14 and filled with the conductive metallic material of the back contact layer 22 to electrically connect adjacent cells to each other in series. Of course, any conductive material can be included in the series connecting scribes 23. Specifically, the series connecting scribe 23 can allow the back contact layer 22 to contact the TCO layer 14 providing a direct electrical connection between the back contact 22 (e.g., a combination of the optional graphite layer and a metal layer) and the front contact material (i.e., the TCO layer 14).
Finally, a second isolation scribe 26 can be laser cut through the back contact (e.g., the optional graphite layer and the metal layer) and photo reactive layers (i.e., the n-type window layer 18 and the absorber layer 20) to isolate the back contact into individual cells.
As stated, the exemplary devices 10 of
The transparent conductive oxide (TCO) layer 14 is shown on the superstrate 12 of the exemplary device 10. The TCO layer 14 allows light to pass through with minimal absorption while also allowing electric current produced by the device 10 to travel sideways to opaque metal conductors. For instance, the TCO layer 14 can have a sheet resistance less than about 30 ohm per square, such as from about 4 ohm per square to about 20 ohm per square (e.g., from about 8 ohm per square to about 15 ohm per square). The TCO layer 14 generally includes at least one conductive oxide, such as tin oxide, zinc oxide, or indium tin oxide, or mixtures thereof. Additionally, the TCO layer 14 can include other conductive, transparent materials. The TCO layer 14 can also include zinc stannate and/or cadmium stannate.
The TCO layer 14 can be formed by sputtering, chemical vapor deposition, spray pyrolysis, or any other suitable deposition method. In one particular embodiment, the TCO layer 14 can be formed by sputtering, either DC sputtering or RF sputtering, on the substrate 12. For example, a cadmium stannate layer can be formed by sputtering a hot-pressed target containing stoichiometric amounts of SnO2 and CdO onto the substrate 12 in a ratio of about 1 to about 2. The cadmium stannate can alternatively be prepared by using cadmium acetate and tin (II) chloride precursors by spray pyrolysis.
In certain embodiments, the TCO layer 14 can have a thickness between about 0.1 μm and about 1 μm, for example from about 0.1 μm to about 0.5 μm, such as from about 0.25 μm to about 0.35 μm.
The optional resistive transparent buffer layer 16 (RTB layer) is shown on the TCO layer 14 on the exemplary thin film photovoltaic device 10. The RTB layer 16 is generally more resistive than the TCO layer 14 and can help protect the device 10 from chemical interactions between the TCO layer 14 and the subsequent layers during processing of the device 10. For example, in certain embodiments, the RTB layer 16 can have a sheet resistance that is greater than about 1000 ohms per square, such as from about 10 kOhms per square to about 1000 MOhms per square. The RTB layer 16 can also have a wide optical bandgap (e.g., greater than about 2.5 eV, such as from about 2.7 eV to about 3.0 eV).
Without wishing to be bound by a particular theory, it is believed that the presence of the RTB layer 16 between the TCO layer 14 and the n-type window layer 18 can allow for a relatively thin n-type window layer 18 to be included in the device 10 by reducing the possibility of interface defects (i.e., “pinholes” in the n-type window layer 18) creating shunts between the TCO layer 14 and the absorber layer 22. Thus, it is believed that the RTB layer 16 allows for improved adhesion and/or interaction between the TCO layer 14 and the absorber layer 22, thereby allowing a relatively thin n-type window layer 18 to be formed thereon without significant adverse effects that would otherwise result from such a relatively thin n-type window layer 18 formed directly on the TCO layer 14.
The RTB layer 16 can include, for instance, a combination of zinc oxide (ZnO) and tin oxide (SnO2), which can be referred to as a zinc tin oxide layer (“ZTO”). In one particular embodiment, the RTB layer 16 can include more tin oxide than zinc oxide. For example, the RTB layer 16 can have a composition with a stoichiometric ratio of ZnO/SnO2 between about 0.25 and about 3, such as in about an one to two (1:2) stoichiometric ratio of tin oxide to zinc oxide. The RTB layer 16 can be formed by sputtering, chemical vapor deposition, spraying pyrolysis, or any other suitable deposition method. In one particular embodiment, the RTB layer 16 can be formed by sputtering, either DC sputtering or RF sputtering, on the TCO layer 14. For example, the RTB layer 16 can be deposited using a DC sputtering method by applying a DC current to a metallic source material (e.g., elemental zinc, elemental tin, or a mixture thereof) and sputtering the metallic source material onto the TCO layer 14 in the presence of an oxidizing atmosphere (e.g., O2 gas). When the oxidizing atmosphere includes oxygen gas (i.e., O2), the atmosphere can be greater than about 95% pure oxygen, such as greater than about 99%.
In certain embodiments, the RTB layer 16 can have a thickness between about 0.075 μm and about 1 μm, for example from about 0.1 μm to about 0.5 μm. In particular embodiments, the RTB layer 16 can have a thickness between about 0.08 μm and about 0.2 μm, for example from about 0.1 μm to about 0.15 μm.
The n-type window layer 18 is shown on resistive transparent buffer layer 16 of the exemplary device 10. In one particular embodiment, the n-type window layer 18 can generally include cadmium sulfide (CdS) but may also include other materials, such as zinc sulfide, cadmium zinc sulfide, etc., and mixtures thereof as well as dopants and other impurities. As such, the n-type window layer 18 may be referred to as a cadmium sulfide layer, when primarily composed of cadmium sulfide. In one particular embodiment, the cadmium sulfide layer may include oxygen up to about 25% by atomic percentage, for example from about 5% to about 20% by atomic percentage. The n-type window layer 18 can have a wide band gap (e.g., from about 2.25 eV to about 2.5 eV, such as about 2.4 eV) in order to allow most radiation energy (e.g., solar radiation) to pass. As such, the n-type window layer 18 is considered a transparent layer on the device 10.
The n-type window layer 18 can be formed by sputtering, chemical vapor deposition, chemical bath deposition, and other suitable deposition methods. In one particular embodiment, the cadmium sulfide layer 18 can be formed by sputtering, either direct current (DC) sputtering or radio frequency (RF) sputtering, on the resistive transparent buffer layer 16. Sputtering deposition generally involves ejecting material from a target, which is the material source, and depositing the ejected material onto the substrate to form the film. DC sputtering generally involves applying a voltage to a metal target (i.e., the cathode) positioned near the substrate (i.e., the anode) within a sputtering chamber to form a direct-current discharge. The sputtering chamber can have a reactive atmosphere (e.g., an oxygen atmosphere, nitrogen atmosphere, fluorine atmosphere) that forms a plasma field between the metal target and the substrate. The pressure of the reactive atmosphere can be between about 1 mTorr and about 20 mTorr for magnetron sputtering. When metal atoms are released from the target upon application of the voltage, the metal atoms can react with the plasma and deposit onto the surface of the substrate. For example, when the atmosphere contains oxygen, the metal atoms released from the metal target can form a metallic oxide layer on the substrate. Conversely, RF sputtering generally involves exciting a capacitive discharge by applying an alternating-current (AC) or radio-frequency (RF) signal between the target (e.g., a ceramic source material) and the substrate. The sputtering chamber can have an inert atmosphere (e.g., an argon atmosphere) having a pressure between about 1 mTorr and about 20 mTorr.
Due to the presence of the resistive transparent buffer layer 16, the n-type window layer 18 can have a thickness that is less than about 0.1 μm, such as between about 10 nm and about 100 nm, such as from about 50 nm to about 80 nm, with a minimal presence of pinholes between the resistive transparent buffer layer 16 and the n-type window layer 18. Additionally, a n-type window layer 18 having a thickness less than about 0.1 μm reduces any adsorption of radiation energy by the n-type window layer 18, effectively increasing the amount of radiation energy reaching the underlying absorber layer 20.
The absorber layer 20 is a p-type layer that interacts with the n-type window layer 18 (e.g., a cadmium sulfide layer) to produce current from the adsorption of radiation energy by absorbing the majority of the radiation energy passing into the device 10 due to its high absorption coefficient and creating electron-hole pairs. In one particular embodiment, the absorber layer 20 generally includes cadmium telluride (CdTe) but may also include other materials (also referred to as a cadmium telluride layer). For example, the absorber layer 20 can generally be formed from cadmium telluride and can have a bandgap tailored to absorb radiation energy (e.g., from about 1.4 eV to about 1.5 eV, such as about 1.45 eV) to create the maximum number of electron-hole pairs with the highest electrical potential (voltage) upon absorption of the radiation energy. Electrons may travel from the absorber layer 20 (e.g., a cadmium telluride layer) across the junction to the n-type window layer 18 (e.g., a cadmium sulfide layer 18) and, conversely, holes may pass from the n-type window layer 18 to the absorber layer 20. Thus, the p-n junction formed between the n-type window layer 18 and the absorber layer 20 forms a diode in which the charge imbalance leads to the creation of an electric field spanning the p-n junction. Conventional current is allowed to flow in only one direction and separates the light induced electron-hole pairs.
The absorber layer 20 can be formed by any known process, such as vapor transport deposition, chemical vapor deposition (CVD), spray pyrolysis, electro-deposition, sputtering, close-space sublimation (CSS), etc. In one particular embodiment, the n-type window layer 18 is deposited by a sputtering and the absorber layer 20 is deposited by close-space sublimation. In particular embodiments, the absorber layer 20 can have a thickness between about 0.1 μm and about 10 μm, such as from about 1 μm and about 5 μm. In one particular embodiment, the absorber layer 20 can have a thickness between about 2 μm and about 4 μm, such as about 3 μm.
A series of post-forming treatments can be applied to the exposed surface of the absorber layer 20. For example, when the absorber layer 20 includes cadmium telluride, these treatments can tailor the functionality of the cadmium telluride layer 20 and prepare its surface for subsequent adhesion to the back contact layer 22. For example, the cadmium telluride layer 20 can be annealed at elevated temperatures (e.g., from about 350° C. to about 500° C., such as from about 375° C. to about 424° C.) for a sufficient time (e.g., from about 1 to about 10 minutes) to create a quality p-type layer of cadmium telluride. Without wishing to be bound by theory, it is believed that annealing the cadmium telluride layer 20 (and the device 10) converts the normally n-type cadmium telluride layer 20 to a p-type cadmium telluride layer 20 having a relatively low resistivity. Additionally, the cadmium telluride layer 20 can recrystallize and undergo grain growth during annealing.
Annealing the cadmium telluride layer 20 can be carried out in the presence of cadmium chloride in order to dope the cadmium telluride layer 20 with chloride ions. For example, the cadmium telluride layer 20 can be washed with an aqueous solution containing cadmium chloride then annealed at the elevated temperature.
In one particular embodiment, after annealing the cadmium telluride layer 20 in the presence of cadmium chloride, the surface can be washed to remove any cadmium oxide formed on the surface. This surface preparation can leave a Te-rich surface on the cadmium telluride layer 20 by removing oxides from the surface, such as CdO, CdTeO3, CdTe2O5, etc. For instance, the surface can be washed with a suitable solvent (e.g., ethylenediamine also known as 1,2 diaminoethane or “DAE”) to remove any cadmium oxide from the surface.
Additionally, copper can be added to the cadmium telluride layer 20. Along with a suitable etch, the addition of copper to the cadmium telluride layer 20 can form a surface of copper-telluride on the cadmium telluride layer 20 in order to obtain a low-resistance electrical contact between the cadmium telluride layer 20 (i.e., the p-type layer) and the back contact layer(s). Specifically, the addition of copper can create a surface layer of cuprous telluride (Cu2Te) between the cadmium telluride layer 20 and the back contact layer 22. Thus, the Te-rich surface of the cadmium telluride layer 20 can enhance the collection of current created by the device through lower resistivity between the cadmium telluride layer 20 and the back contact layer 22.
Copper can be applied to the exposed surface of the cadmium telluride layer 20 by any process. For example, copper can be sprayed or washed on the surface of the cadmium telluride layer 20 in a solution with a suitable solvent (e.g., methanol, water, or the like, or combinations thereof) followed by annealing. In particular embodiments, the copper may be supplied in the solution in the form of copper chloride, copper iodide, or copper acetate. The annealing temperature is sufficient to allow diffusion of the copper ions into the cadmium telluride layer 20, such as from about 125° C. to about 300° C. (e.g. from about 150° C. to about 200° C.) for about 5 minutes to about 30 minutes, such as from about 10 to about 25 minutes.
The back contact 22 can be, in one particular embodiment, formed from an optional graphite layer and a metal contact layer on the absorber layer 20 and generally serves as the back electrical contact, in relation to the opposite, TCO layer 14 serving as the front electrical contact. The back contact is formed on, and in one embodiment is in direct contact with, the cadmium telluride layer 20.
The graphite layer can include a polymer blend or a carbon paste and can be applied to the semiconductor device by any suitable method for spreading the blend or paste, such as screen printing, spraying or by a “doctor” blade. After the application of the graphite blend or carbon paste, the device 10 can be heated to convert the blend or paste into the conductive graphite layer. The graphite layer can be, in particular embodiments, from about 0.1 μm to about 10 μm in thickness, for example from about 1 μm to about 5 μm.
The metal contact layer can be made from one or more highly conductive materials, such as elemental nickel, chromium, copper, tin, aluminum, gold, silver, technetium or alloys or mixtures thereof. The metal contact layer, if made of or comprising one or more metals, is suitably applied by a technique such as sputtering or metal evaporation. The back contact layer 22 can be from about 0.1 μm to about 1.5 μm in thickness.
Other layers may also be present in the thin film stack, although not specifically shown in the embodiments of
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they include structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
