Patent Application
20060203114
The invention relates generally to the field of CMOS image sensors and, more particularly, to such CMOS image sensors having a three-transistor design with substantially the same sensitivity of a four-transistor design.
With the size of image sensors (the number of pixels) increasing rapidly, smaller pixel size is highly desired. The typical pixels of a CMOS image sensor are either the three- or four-transistor design. The three-transistor design has the desired smaller size but with an undesirable noise level as compared to the four-transistor design. The four-transistor design has higher sensitivity than the three-transistor design, but it obviously occupies a larger spatial area, which is undesirable, and the additional couplings inherent in such a design creates more noise as the pixel size shrinks.
Consequently, a need exists for a pixel of a CMOS transistor to have the sensitivity of the four-transistor design and the size of the three-transistor design.
The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides in a CMOS image sensor comprising a plurality of pixels defining an imaging area each pixel comprising (a) a photosensitive area that converts incident light into a charge; (b) a first transistor having a transfer gate that transfers charge from the photosensitive area to a charge-to-voltage region; (c) a second transistor that resets the voltage of the charge-to-voltage region; (d) a third transistor that amplifies voltage from the charge-to-voltage region; and a select mechanism positioned outside the imaging area on the image sensor that selects a predefined number of pixels for readout from the third transistor.
These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.
Advantageous Effect of the Invention
The present invention has the following advantage of a three-transistor CMOS image sensor with the sensitivity of a four-transistor design.
Referring to
Referring to
A reset transistor 110 is electrically connected to the node of the floating diffusion 90 for resetting the voltage of the floating diffusion 90. In this regard, to reset the voltage of the floating diffusion 90, the row select switch 40 is closed to enable the row of pixels and the reset gate 120 is pulsed for resetting the floating diffusion 90 to the voltage of Vdd or substantially close to the voltage of Vdd. It is noted that a ground or disable switch 125, which is connected to a ground bus 55, is always in the opposite position as switch 40 for preventing leaking current.
The gate 130 of an amplifying transistor 140 is electrically connected to the floating diffusion 90 for receiving and amplifying the voltage of the floating diffusion 90. The amplifying transistor 140 receives the reset voltage and transfers to the output 150 when the reset transistor 110 is pulsed, as discussed in the preceding paragraph. Then the amplifying transistor 140 receives and transfers the image signal to the output 150 when the transfer gate 80 of the transfer transistor 70 is pulsed, which dumps the charge onto the floating diffusion 90 that consequently is read as a voltage by the amplifying transistor 140, as also discussed above. A bias current 160 is connected to the output of the amplifier for biasing the amplifier.
The output of the amplifier is then readout to a sample and hold circuit array 45 (see
The invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention.
