Patent Application
20120227794
1. Field of the Invention
The present invention relates to methods and processes for forming solar cell devices and solar cell devices made by such methods and processes. In particular, the present invention relates to methods and processes for the reduction of recombination losses in solar cell devices and solar cell devices with reduced recombination losses.
2. Description of the Related Art
The efficiency of solar cells is improved by reducing recombination losses. Recombination loss refers to the reaction between electrons and holes in the semiconductor. Recombination can occur due to several physical recombination mechanisms, such as radiative, Auger, and deep-level (commonly known as Shockley-Read-Hall) recombination. Recombination loss in the bulk of the solar cell may occur separately from recombination loss at the surfaces of the solar cell. In general, recombination at the surfaces of a solar cell become relatively more important as the material quality is improved and the device is made thinner. This is particularly true for silicon solar cells where thin substrates are used in order to reduce the cost.
A dielectric layer on the surface of silicon may be used to reduce recombination losses. Such dielectric layers are said to “passivate” the surface because the defect states responsible for the recombination are made electrically inactive, or “passivated”. Passivation layers can include thermally grown SiO2, deposited layers of various inorganic compounds, or deposited layers of semiconductor materials (e.g., various alloys of a-Si:H).
When light falls on the solar cell, energy from the incident photons generates electron-hole pairs on both sides of p-n junction region 103. In a typical, n-type emitter region 102 and p-type base region 101, electrons diffuse across the p-n junction to a lower energy level and holes diffuse in the opposite direction, creating a negative charge on the emitter and a corresponding positive charge build-up in the base. When an electrical circuit is made between the emitter and the base, a current will flow and electricity is produced by solar cell 100. The efficiency at which solar cell 100 converts incident energy into electrical energy is affected by a number of factors, including the recombination rate of electrons and holes in solar cell 100 and the fraction of light that is reflected off backside layers of solar cell 100 and back into the substrate 110.
Recombination occurs when electrons and holes, which are moving in opposite directions in solar cell 100, combine with each other. Each time an electron-hole pair recombines in solar cell 100, charge carriers are eliminated, thereby reducing the efficiency of solar cell 100. Recombination may occur in the bulk silicon of substrate 110 or on either surface 105, 106 of substrate 110. One function of the passivation layer 104 is to minimize the carrier recombination at the surface of the emitter region(s) 102 or the base region 101 over which the passivation layer 104 is formed. Thorough passivation of the surface of a solar cell greatly improves the efficiency of the solar cell by reducing surface recombination.
Surface recombination in silicon is very well understood. See, for example, Armin Aberle, “Surface passivation of crystalline silicon solar cells: a review,” Prog. In Photovoltaics, vol. 8, pp. 473-487 (2000). There are two primary physical mechanisms that are typically employed for reducing surface recombination. In the first mechanism, the density of states responsible for the recombination is reduced. In the second mechanism, a fixed charge at the surface reduces the density of one of the charge carriers to lower the net recombination rate. “Fixed charge” refers to defects in the dielectric near the interface that are charged under normal operating conditions. The charge tends to be a chemical property of the dielectric on the silicon, and may be difficult to modulate to any great extent. Thermally grown oxides tend to have a small positive charge <1011 cm−2). Silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD) generally has a large positive fixed charge (>1012 cm−2), while aluminum oxide deposited by atomic-layer deposition has a negative fixed charge. Positive fixed charge is useful for passivating n-type surfaces since the positive charge repels the minority-charge carrier (positively charged holes). The opposite is true for dielectrics with negative fixed charge; i.e., these materials are useful for passivating p-type surfaces since the negative charge repels electrons.
Control of the fixed charge is particularly important for back-contact silicon solar cells. Back-contact solar cells have both the positive and negative polarity contacts on the rear of the solar cell. There must be good electrical isolation between the two regions that must also be passivated for low recombination losses. As an example,
The positive-polarity contact and grid (“P-metal”) 220 is separated from the n+ diffusion 218 on the rear surface by a dielectric diffusion barrier 214. The quality of the interface between the dielectric diffusion barrier 214 and the p-type silicon 210 affects the electrical isolation between the n+ diffusion 218 and p-metal contact 220; i.e., the solar cell will be shunted if there is sufficient positive fixed charge at the interface to “invert” the surface. “Inversion” occurs when the surface charge is sufficient to cause the interface to change polarity in charge conductivity. Therefore, there is a need for an improved method of reducing recombination losses in solar cell devices and prevent inversion of regions in solar cells.
The present invention generally provides methods and processes for forming solar cell devices. In one embodiment, the method includes disposing an amount of impurities into a charge compensating region formed on a rear surface of a substrate and forming a rear surface passivation layer over at least a portion of the charge compensating region, wherein the amount of the impurities disposed in the charge compensating region is selected to compensate for an amount of charge formed in the rear surface passivation layer.
In another embodiment, a method of forming a solar cell device, includes forming an array of vias in a substrate that is doped with a first doping element, wherein the array of vias is formed between a front surface and a rear surface of the substrate, forming a charge compensating region on a portion of the rear surface, wherein the charge compensating region is doped with a third doping element of the same doping type as the first doping element, forming a dielectric passivation layer on the charge compensating region, forming a doped region on at least a portion of the front surface, on a surface of the vias in the array of vias, and at least a portion of the rear surface, wherein the doped region is doped with a second doping element that is of an opposite doping type to the first doping element, and depositing a first gridline on the rear surface and a distance along the rear surface from the array of vias, wherein the first gridline traverses the dielectric passivation layer and is electrically connected to the substrate doped with the first doping element.
In another embodiment, a solar cell device includes a substrate comprising a semiconductor material doped with a first doping element, the substrate comprising a front surface and a rear surface opposite the front surface, a doped region formed on the front surface and in the substrate, wherein the doped region is doped with a second doping element that is of an opposite doping type to the first doping element, a charge compensating region formed on the rear surface, wherein the charge compensating region is doped with a third doping element of the same doping type as the first doping element, a rear surface passivation layer formed on the charge compensating region, a back contact layer comprising a conductive material formed on the rear surface passivation layer, and a backside contact that traverses the rear surface passivation layer to electrically couple the back contact layer with the semiconductor material.
In another embodiment, a solar cell device includes a substrate having an array of vias formed between a front surface and a rear surface of the substrate, wherein the substrate is doped with a first doping element, a charge compensating region formed on a portion of the rear surface, wherein the charge compensating region is doped with a third doping element of the same doping type as the first doping element, a dielectric passivation layer formed on at least a portion of the charge compensating region, and a doped region formed on at least a portion of the front surface, a surface of the vias in the array of vias, and at least a portion of the rear surface adjacent the charge compensating region, wherein the doped region is doped with a second doping element that is of an opposite doping type to the first doping element.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
To facilitate understanding, identical or similar reference numerals have been used, where possible, to designate identical or similar elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
Embodiments of the present invention contemplate the formation of a solar cell device that has improved efficiency and device electrical properties. In particular, embodiments of the present invention may reduce the recombination losses often associated with solar cell devices. In one embodiment, the solar cell device is processed to alter the affect of charge that is typically formed in dielectric layers to reduce recombination losses in a solar cell. Although silicon solar cells are most commonly used, the present invention is applicable to solar cells comprising any material.
As previously stated in relation to
Embodiments of the invention may use a low-energy ion implant of a dopant atom to modulate the effective surface charge and reduce recombination losses. Only a low dose is required, so that the cost of the step may be minimized. The ionized dopants near the surface behave electrically like a fixed charge at the interface. One advantage of an implant for silicon solar cells is that commonly used, low cost dielectric coatings may be used for passivating either n-type or p-type silicon solar cells by changing the effective fixed charge. For example, PECVD a-SiNx:H may not passivate p-type Si well in silicon solar cells due to its large positive fixed charge. (The chemical symbol a-SiNx:H indicates that the material is amorphous, has variable stoichiometry, and has considerable hydrogen content. It is frequently abbreviated SiNx.) Embodiments of the invention generally provide a method of forming solar cells having a doped portion near dielectric layers to prevent inversion due to the positive charge in the dielectric material. Embodiments of the invention may include forming a shallow implant of ionized charge near dielectric interfaces within a solar cell device that will behave electrically as if it was a fixed charge to prevent inversion.
As will be shown and described below with reference to the Figures, embodiments of the invention include a method of forming a solar cell, including disposing an amount of impurities into a charge compensating region formed on a rear surface of a substrate, and forming a rear surface passivation layer over at least a portion of the charge compensating region, wherein the amount of the impurities disposed in the charge compensating region is selected to compensate for an amount of charge formed in the rear surface passivation layer. The impurities may comprise charge centers in the dielectric. In some embodiments, ion implantation is used to incorporate impurities into the charge compensating region. The impurities may comprise dopants in the silicon. Further details regarding embodiments of the invention are described below
In one embodiment, a solar cell device is formed using a process 400 for passivation of the rear surface of a silicon solar cell with a p-type substrate using a dielectric coating is as illustrated in
At step 402, the surfaces of the substrate 310, such as the front surface 305, rear surface 306 are etched to remove any undesirable material or crystallographic defects from the wafer production process and the laser machining process. In one embodiment, the etch process may be performed using a batch etch process in which the substrates are exposed to an alkaline etching solution. The substrates can be etched using a wet cleaning process in which they are sprayed, flooded, or immersed in an etchant solution. The etchant solution may be a conventional alkaline cleaning chemistry, such as a potassium hydroxide, or other suitable and cost effective etching solution. This step might additionally texture the surface for improved light collection.
Next, at step 404, as shown in
In general, it is desirable to create a doping profile in the front surface 502 that is different than the doping profile in the via surface 511 and back surface 503, so that the amount of light collected at the front surface 502 is maximized and the series resistance formed between the front surface 502 and the gridline 520 formed on the rear surface 503 is reduced. In one embodiment, it is desirable to create a doping profile in the portion of the diffused region 518 formed on the front surface 502 that has a sheet resistance of between about 60 Ω/sq and about 200 Ω/sq, and a doping profile in the portion of the diffused region 225 formed on the via surface 511 and the rear surface 503 that has a sheet resistance of between about 20 Ω/sq and about 80 Ω/sq, such as about 40 Ω/sq. In another embodiment, to simplify the solar cell device formation process a single dopant concentration profile is created in the diffused region 518, which is formed across the front surface 502, via surface 511 and portions of the back surface 503. In this configuration, for example, the dopant concentration in the diffused region 518 is doped to achieve a sheet resistance between about 60 Ω/sq and about 80 Ω/sq. In one embodiment, the dopant concentration in the diffused region 518 is doped to achieve a sheet resistance of greater than about 60 Ω/sq, since doping levels on the front surface of the solar cell that are less than about 60 Ω/sq will tend to inhibit light absorption, and thus decrease solar cell efficiency.
At step 406, the substrate is cleaned and etched to remove any glass formed on the surfaces. Phosphorous glass that may have formed during the diffusion process should be removed. For example, a phosphosilicate glass (PSG) may be formed on the top surface of the silicon bulk layer 305 which may then be etched off using an etchant, such as HF acid. The PSG etch may be performed globally. In one example, phosphorous glass is etched from the front surface 305 and the rear surface 306. In one embodiment the etch chemistry used is HF for the front surface and a combination of HNO3 and HF is used for the rear surface. An inline etch float process may be also used where the substrate floats on the rear surface in the desired etch chemistry to preferentially etch the rear surface of the substrate.
Next, at step 408, as shown in
The charge compensating region 317 is formed by doping a portion of the substrate to a certain level so that it becomes a low dose region that is primarily at the surface to compensate the charge at dielectric layer. Doping may be performed at very low energy implant levels such as 2-50 keV and at dosages from between 1×1011 per centimeters squared to 1×1013 per centimeters squared. The depth of the dopant may be 1.5 micron or less, such as 1 micron. In another embodiment the dopant depth is less than 100 nm. For example, a boron implant may be performed at 20 keV to a depth of 64 nm. Generally, the implant should be shallow to not cause too much interference with the channel conductance. In another embodiment, the charge compensating region could include a portion of the dielectric passivation layer, i.e. the charge compensating region may include a portion of the dielectric passivation layer, the interface between the dielectric passivation layer and the substrate, and a portion of the substrate.
It is believed that implantation or other doping means of selected impurities near the interface to form the charge compensation region extrinsically controls the surface potential of dielectrically passivated surfaces. “Intrinsic” means the inherent surface charge due to the chemistry of the dielectric-silicon which may be small and positive for thermal oxides, etc. Thus, the surface potential may be controlled independent of the silicon substrate dopant type and/or amount.
Various doping methods may be used to dope the charge compensating region 317. For example, a plasma ion immersion implantation (PIII) may be used to implant the dopant. Pill may be less expensive and easier to scale in the area compared to traditional implanters using beam lines. In another embodiment, a furnace may be used to form the charge compensating region 317. The entire substrate surface may be doped when using a furnace method. However, the uniformity if likely poor as very high temperatures may be required. Additionally, if a glass is formed, such as a boronsilicate glass (BSG), it is typically difficult to etch and remove to form the charge compensating region 317. The dopant may then optionally be activated in at a temperature from 800° C. to 900° C. for 5 to 60 minutes. However, the charge compensating region 317 may alternatively be activated in a later step, such as in step 416.
Next, at step 410, in one embodiment, a thin passivation and/or antireflection layer, as shown in
Next, in some embodiments the passivation layer may be patterned using a laser or etch gel to form grid lines for the p-type contacts, though this step is optional. In other embodiments, the later steps of forming the p-type contacts themselves are able to pattern the passivation layer during formation of the p-type contacts.
At box 412, as illustrated in
At box 414, as illustrated in
At box 416, a conventional contact firing process is performed to assure that the front and rear electrical contacts and gridlines 307, 320, 321 make a good electrical contact to the desired regions of the substrate 310. In this step, the substrate is heated to desirable temperature to form a good electrical contact between the front contact 307 and the substrate 302, and the back contact layer 320 and backside contact 321 and the substrate 310. For example, the firing process may be performed in two parts. The first part may be performed as an organic burn off at 500° C. for a few minutes followed by a second part at a temperature between 700° C. and 800° C. for 10-30 seconds.
In another embodiment of the invention, a voltage-threshold implant may be preferably used to modify the region between the negative- and positive-polarity contacts in a back-contact cell as described below. The implant is preferably shallow and provides for independent control of the surface potential of the passivation layer
A back-contact cell device, such as a EWT solar cell device 500, may be formed using embodiments of the invention.
In one embodiment the method of forming a EWT solar cell device 500 includes forming an array of vias 512 in a substrate 510 that is doped with a first doping element, such as a p-type dopant. The array of vias 512 is formed between a front surface 502 and a rear surface 503 of the substrate 510. At step 702, and as shown in
In one embodiment, when employing thin solar cell substrates, such as substrates with a thickness of 100 μm or less, the via diameter is approximately greater than or equal to the substrate thickness. The via 512 density per unit surface area of the front surface 502, or rear surface 503, is dependent on the acceptable total series resistance loss due to current transport in the emitter region formed on the front surface 502 through the vias 512 to the rear surface 203 and second gridline 520. In general, the density of vias 512 can be decreased as the sheet resistance of the emitter region is reduced, such as determined by Ohms per square (Ω/sq). One skilled in the art will appreciate that as the diameter of the vias 512 increases the cross-sectional area through which the generated current can pass, and thereby reduce the resistance. However, increasing the size and/or density of vias 512 will affect the amount of energy required to form each of the vias, the throughput of the via formation process, and the usable surface area of the front side of the solar cell device.
Next, at step 704, the surfaces of the substrate 510, such as the front surface 502, rear surface 503, and via surface 511 are etched to remove any undesirable material or crystallographic defects from the wafer production process and the laser machining process. In one embodiment, the etch process may be performed using a batch etch process in which the substrates are exposed to an alkaline etching solution. The substrates can be etched using a wet cleaning process in which they are sprayed, flooded, or immersed in an etchant solution. The etchant solution may be a conventional alkaline cleaning chemistry, such as a potassium hydroxide, or other suitable and cost effective etching solution. This step might additionally texture the surface for improved light collection.
Next, at step 706, as shown in
In one embodiment the whole back surface 503 is doped with a p-type dopant, such as boron. In another embodiment, a selective portion of the back surface 503 is doped with a p-type dopant, such as boron. Doping may be performed at very low energy implant levels such as 2-50 keV and at dosages from between 1×1011 per centimeters squared to 1×1013 per centimeters squared. The depth of the dopant may be 1.5 micron or less, such as 1 micron. In another embodiment the dopant depth is less than 100 nm. For example, a boron implant may be performed at 20 keV to a depth of 64 nm. Generally, the implant should be shallow to not cause too much interference with the channel conductance. Various doping methods may be used to dope the charge compensating region 514. For example, a plasma ion immersion implantation (PIII) may be used to implant the dopant. Pill may be less expensive and easier to scale in the area compared to traditional implanters using beam lines. In another embodiment, a furnace may be used to form the charge compensating region 514. The entire substrate surface may be doped when using a furnace method. However, the uniformity if likely poor as very high temperatures may be required. Additionally, if a glass is formed, such as a boronsilicate glass (BSG), it is typically difficult to etch and remove to form the charge compensating region 514.
Next, at step 708, as shown in
Next, the substrate 201 may be cleaned to remove any undesirable formed oxide materials and/or surface contamination found on the surface of the substrate after step 308 has been performed. In one embodiment, the clean process may be performed using a batch cleaning process in which the substrates are exposed to a hydrofluoric acid (HF) containing cleaning solution. The substrates can be cleaned using a wet cleaning process in which they are sprayed, flooded, or immersed in a cleaning solution. For example, the etch/clean chemistry may be a HF solution with a small amount of oxidizing agent added. In another embodiment, step 310 may include an HCl clean with an oxidizing agent such as peroxides, followed by an HF dip.
Next, at step 710, as shown in
In general, it is desirable to create a doping profile in the front surface 502 that is different than the doping profile in the via surface 511 and back surface 503, so that the amount of light collected at the front surface 502 is maximized and the series resistance formed between the front surface 502 and the gridline 520 formed on the rear surface 503 is reduced. In one embodiment, it is desirable to create a doping profile in the portion of the diffused region 518 formed on the front surface 502 that has a sheet resistance of between about 60 Ω/sq and about 200 Ω/sq, and a doping profile in the portion of the diffused region 225 formed on the via surface 511 and the rear surface 503 that has a sheet resistance of between about 20 Ω/sq and about 80 Ω/sq, such as about 40 Ω/sq. In another embodiment, to simplify the solar cell device formation process a single dopant concentration profile is created in the diffused region 518, which is formed across the front surface 502, via surface 511 and portions of the back surface 503. In this configuration, for example, the dopant concentration in the diffused region 518 is doped to achieve a sheet resistance between about 60 Ω/sq and about 80 Ω/sq. In one embodiment, the dopant concentration in the diffused region 518 is doped to achieve a sheet resistance of greater than about 60 Ω/sq, since doping levels on the front surface of the solar cell that are less than about 60 Ω/sq will tend to inhibit light absorption, and thus decrease solar cell efficiency.
Next, at step 712, the substrate 510 may be cleaned to remove any undesirable formed oxide materials and/or surface contamination found on the surface of the substrate after step 710 has been performed. In one embodiment, the clean process may be performed using a batch cleaning process in which the substrates are exposed to a hydrofluoric acid (HF) containing cleaning solution. The substrates can be cleaned using a wet cleaning process in which they are sprayed, flooded, or immersed in a cleaning solution. For example, the etch/clean chemistry may be a HF solution with a small amount of oxidizing agent added. In another embodiment, step 310 may include an HCl clean with an oxidizing agent such as peroxides, followed by an HF dip. Optionally, the dielectric passivation layer 516 may be etched using an HF solution of 10-20 parts water to 1 part HF, where the HF is a 49% HF/water solution.
Next, at step 714, in one embodiment, a thin passivation and/or antireflection layer (not shown) may be formed over the front surface 502, via surface 511 and/or portions back surface 503. The thin passivation and/or antireflection (ARC) layer may be a dielectric layer, preferably comprising a nitride (e.g., silicon nitride), that is preferably disposed on front cell surface 502 in order to passivate the surface and provide an anti-reflection coating. In one embodiment, a passivation and ARC layer is formed on the front surface 502 and portions of the vias 512 in step 714, and then a passivation and ARC layer is formed on the rear surface 503 and portions of the vias 512. In one embodiment, the thin passivation and/or antireflection layer is formed using a conventional PECVD, thermal CVD or other similar formation process. The passivation layer thickness may be between about 75-85 nm on both front and rear surfaces, although the rear surface may be as thin as 30 nm in some embodiments.
Next, in some embodiments the passivation layer may be patterned using a laser or etch gel to form grid lines for the p-type contacts, though this step is optional. In other embodiments, the later steps of forming the p-type contacts themselves are able to pattern the passivation layer during formation of the p-type contacts.
At box 716, as illustrated in
At box 718, as illustrated in
In some embodiments, the aluminum paste and rear PECVD SiNx are typically selected so that the aluminum does not fire through the SiNx film. The boron implant could alternatively be performed after, the deposition of the dielectric on the rear surface. It may be advantageous to implant through the dielectric in order to get a shallow implant in some embodiments. Other p-type dopants (e.g., In, Al) may alternatively be used instead of boron, and other dielectric coatings may alternatively be used instead of SiNx.
At box 720, a conventional contact firing process is performed to assure that the first and second gridlines 520, 522 make a good electrical contact to the desired regions of the substrate 510. In this step, the substrate is heated to desirable temperature to form a good electrical contact between the first gridline 520 and the substrate 510, and the second gridline 522 and the substrate 510. For example, the firing process may be performed in two parts. The first part may be performed as an organic burn off at 500° C. for a few minutes followed by a second part at a temperature between 700° C. and 800° C. for 10-30 seconds.
While the foregoing is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. Variations and modifications of the present invention will be obvious to those skilled in the art and it is intended to cover all such modifications and equivalents.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US2010/049537 | 9/20/2010 | WO | 00 | 5/29/2012 |
| Number | Date | Country | |
|---|---|---|---|
| 61243615 | Sep 2009 | US |
