Patent Application
20130313623
This disclosure relates generally to threshold gates and circuitry associated with threshold gates.
Often, various Boolean gates are required to implement a complex Boolean function. As the number of Boolean gates increases, the amount of space needed to provide the Boolean gates in an integrated circuit (IC) also increases. In addition, how fast the IC circuit can generate an output for the Boolean function, and the amount of power required by the IC circuit is determined by the number of Boolean gates needed to implement the Boolean function. Furthermore, Boolean gates are volatile and thus cannot store an output for the Boolean function if the power is turned off.
Accordingly, there is a need to reduce the number of Boolean gates required by an IC circuit.
Threshold gates and related circuitry are disclosed in this disclosure. The threshold gate may implement a threshold function that provides an output just like a complex Boolean function requiring numerous Boolean gates. In one embodiment, a threshold gate includes a threshold realization element and a magnetic tunnel junction (MTJ) element. The MTJ element is switchable from a first resistive state to a second resistive state. To realize a threshold function with the MTJ element, the threshold realization element is configured to switch the MTJ element from the first resistive state to the second resistive state in accordance with the threshold function. In this manner, the first resistive state and the second resistive state of the MTJ element may be utilized to represent an output of the threshold function. Since the MTJ element is non-volatile, the output of the threshold function is stored even if power to the threshold gate is interrupted. Furthermore, the threshold function implemented by the threshold gate may provide the output in the same manner as the output of a complex Boolean function requiring several Boolean gates. Thus, the threshold gate may be more compact, faster, and/or more space efficient than the Boolean gates required to generate the same output.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
This disclosure relates generally to threshold gates and related circuitry. Threshold gates are configured to implement a threshold function, which may map a Boolean input representing binary values to an output in the same manner as an implementation of the same function using conventional AND-OR Boolean gates. This may be advantageous because a single threshold gate may be able to generate the output while the equivalent representation of the Boolean function using AND-OR gates may require several Boolean gates. Accordingly, the threshold gate may be more compact, faster, and/or more space efficient than the network of Boolean gates required to implement the same Boolean function.
A threshold gate is a non-decomposable primitive circuit that realizes a threshold function to provide an output by comparing some physical quantity such as charge, voltage or current. Below are exemplary equations that demonstrate various examples of threshold functions that may be implemented by threshold gates:
Different threshold gates may be utilized to operate in accordance with the various threshold functions shown above. In the equations above, parameters x1, x2 . . . xn is a set of Boolean variables wherein each Boolean variable in the set of Boolean variables has a binary value. Parameters w1, w2 . . . wn is a set of weights wherein each weight in the set of weights has an integer value. The T is a threshold value of the threshold function fT. A Boolean function fB(x1, x2 . . . xn) may be implemented by a threshold gate if the threshold gate is operable to provide the weight values in the set of weights of threshold function fT(x1, x2 . . . xn) and the threshold value T of the threshold function such that the threshold function fT(x1, x2 . . . xn) implemented by the threshold gate maps the set of Boolean variables to the same output as the Boolean function fB(x1, x2 . . . xn). The threshold function fT(x1, x2 . . . xn) is represented by the set of weights and the threshold value in the following format [w1, w2 . . . wn; T]. The output of the Boolean function has a binary value and thus so does the output of the threshold function.
For example, in one embodiment, the first resistance state is a high resistance state and the second resistance state is a low resistance state. Furthermore, the first magnetic orientation alignment state is an anti-parallel magnetic orientation state in which the magnetic orientations for the ferromagnetic materials on opposing sides of the tunneling barrier are unaligned and in substantially opposite directions. Additionally, the second magnetic orientation alignment state is a parallel magnetic orientation state in which the magnetic orientations for the ferromagnetic materials on opposing sides of the tunneling barrier are aligned and in substantially the same directions. In this embodiment, the MTJ element 14 may be configured to generate a current of electrons tunneling across the tunneling barrier. Given the application of a magnetic field 3, a density of states of spin-up and spin-down electrons is provided on opposing sides of the tunneling barrier, which defines the magnetic orientations of the ferromagnetic materials. Accordingly, the MTJ element 14 is in the high resistance state as a result of the anti-parallel magnetic orientation state because there are less spin-up and spin-down electrons on opposing sides of the tunneling barrier to provide the tunneling current. Also, the MTJ element 14 is in the low resistance state as a result of the parallel magnetic orientation state because there more spin-up and spin-down electrons on opposing sides of the tunneling barrier to provide the tunneling current.
The threshold realization element 12 is configured to switch the passive resistive element from the first resistive state to the second resistive state in accordance with a threshold function. For instance, the threshold realization element 12 in
To switch the MTJ element 14 from the first resistive state to the second resistive state, the threshold realization element 12 is configured to generate a signal 16. The MTJ element 14 is operable to receive the signal 16 and is switchable from the first resistive state (and the first magnetic orientation alignment state) to the second resistive state (and the second magnetic orientation alignment state) in response to the signal 16 having a signal level greater than a switching magnitude. The signal level may be a voltage level and/or a current level of the signal 16 and the switching magnitude may be a switching voltage magnitude and/or a switching current magnitude. In one embodiment, the signal level of the signal 16 is greater than the switching magnitude for a given time duration, d. When the signal level of the signal 16 is greater than the switching magnitude for the time duration, d, there is an adjustment in the alignment of the magnetic orientations of the ferromagnetic materials. Thus, the MTJ element 14 is switched from the first magnetization orientation state (and the first resistive state) to the second magnetization orientation state (and the second resistive state) in response to the signal level of the signal 16 being greater than the switching magnitude for the given time duration, d.
In this embodiment, the threshold realization element 12 is configured to receive a Boolean input BI representing Boolean variables and a threshold input TI that indicates the threshold value T. The threshold realization element 12 is configured to adjust the threshold value of the threshold function so that the threshold value T corresponds to the switching magnitude. The Boolean input BI may represent the Boolean variables x1, x2 . . . xn for the threshold function. The signal level of the signal 16 is provided by the threshold realization element 12 such that the signal level represents a scalar product of the set of Boolean variables x1, x2 . . . xn and the set of weights of the threshold function. In one embodiment, the weight values for the weights w1, w2 . . . wn of the threshold function are represented by a number of times that the Boolean variables x1, x2 . . . xn are provided in the Boolean input BI.
As shown in
The TMR of the MTJ element 20 is given by:
TMR=(RHigh−RLow)/RLow.
Referring now to
The majority function element 36 was thus configured to implement a k/N majority function whose majority integer value is the integer number, k. If the transistors 38 each have a width, w, a current level, lk of the threshold realization current 40 drawn by k number of transistors (each of width w) should exceed the switch current magnitude lc of the MTJ element 20 at a current duration, d. Accordingly, if k or more of the transistors 38 are on, the MTJ element 20 is switched from high resistance state (and anti-parallel magnetization orientation state) to low resistance state (and parallel magnetization orientation state).
The majority element can thus realize a k/N majority function and any of its derivatives. The threshold gate 34 is thus programmable to implement any threshold function that corresponds to the k/N majority function or any of its derivatives. For example, the majority function element 36 is configured to receive a set of bit signals (referred to generically as element 42 and specifically to elements 42-1, 42-2, 42-3, 42-4, 42-5, 42-6, 42-7, 42-8). In this embodiment, the integer number N=8 and the integer number k is 4. More specifically, a gate of the transistor 38-1 receives a bit signal 42-1 that represents a bit, b1. A gate of the transistor 38-2 receives a bit signal 42-2 that represents a bit, b2. A gate of the transistor 38-3 receives a bit signal 42-3 that represents a bit, b3. A gate of the transistor 38-4 receives a bit signal 42-4 that represents a bit, b4. A gate of the transistor 38-5 receives a bit signal 42-5 that represents a bit, b5. A gate of the transistor 38-6 receives a bit signal 42-6 that represents a bit, b6. A gate of the transistor 38-7 receives a bit signal 42-7 that represents a bit, b7. A gate of the transistor 38-8 receives a bit signal 42-8 that represents a bit, b8.
To implement the majority function, the current level of the threshold realization current 40 is provided by the majority function element 36 in accordance with the majority function on the bit signals 42. More specifically, the majority function element 36 is configured to generate the threshold realization current 40 such that the current level corresponds with an aggregated sum of the bits b1-b8 represented by the bit signals 42. In particular, the current level of the threshold realization current 40 that monotonically corresponds with the aggregated sum (b1+b2+b3+b4+b5+b6+b7+b8) of the bits b1-b8 and the integer number k represents a majority value. It should be noted that the current level of the threshold realization current 40 might not be a linear function of the sum of the bits b1-b8. It could be a monotonic function of the sum of the bits b1-b8. The monotonic behavior of the threshold realization current 40 is all that is needed to realize a threshold function. For example, in an alternate embodiment, the threshold realization current 40 supplied from the active PMOS transistors is amplified and/or attenuated before feeding to a passive resistive element such as an STT-MTJ element.
In
As an example, the Boolean function f=ab+bc+ca, where a, b, c are each Boolean variables, corresponds to a threshold function having a set of weights and a threshold value of [1, 1, 1; 2]. With N=8 and k=4, the majority value is equal to 4; however, the threshold value of the threshold function is equal to 2. The threshold function is realized if one of the bits b1-b8 is assigned to the Boolean variable a, one of the bits of b1-b8 is assigned to the Boolean variable, b, one of the Boolean variables is assigned to the Boolean variable, c, two of the transistors 38 are maintained so as to be activated, and a remainder of the transistors 38 are deactivated.
More specifically, the majority function element 36 is programmable to realize the threshold function of [1, 1, 1; 2] by assigning the bits b1-b8 represented by the bit signals 42 in accordance with the set of weights and the threshold value. Boolean variable, a, is provided as the bit b1 represented by the bit signal 42-1. The Boolean variable, b, is provided as the bit b2 represented by the bit signal 42-2. The Boolean variable, c, is provided as the bit b3 represented by the bit signal 42-3. The bit b4 is provided as a logical 0 represented by the bit signal 42-4. The bit b5 is provided as a logical 0 represented by the bit signal 42-5. The bit b6 is provided as a logical 1 represented by the bit signal 42-6. The bit b7 is provided as a logical 1 represented by the bit signal 42-7. The bit b8 is provided as a logical 1 represented by the bit signal 42-8. This assignment of the threshold function [1, 1, 1; 2] to the majority function implemented by the majority function element 36 is represented as (a, b, c, 1, 1, 0, 0, 0). Thus, in this case, bits 1-3 are an example of the Boolean input BI with regard to
For example, a Boolean function is a v b v c v d v e, where a, b, c, d, and e are Boolean variables. The Boolean function, a v b v c v d v e corresponds to a threshold function with a set of weights and a threshold value of [1, 1, 1, 1, 1; 1]. The majority function element 36 is programmable to realize the threshold function of [1, 1, 1, 1, 1; 1] by assigning the bits b1-b8 represented by the bit signals 42 in accordance with the set of weights and the threshold value. Boolean variable, a, is provided as the bit b1 represented by the bit signal 42-1. The Boolean variable, b, is provided as the bit b2 represented by the bit signal 42-2. The Boolean variable, c, is provided as the bit b3 represented by the bit signal 42-3. The Boolean variable, d, is provided as the bit b4 represented by the bit signal 42-4. The Boolean variable, e, is provided as the bit b5 represented by the bit signal 42-5. The bit b6 is provided as a logical 0 represented by the bit signal 42-6. The bit b7 is provided as a logical 0 represented by the bit signal 42-7. The bit b8 is provided as a logical 0 represented by the bit signal 42-8. This assignment of the threshold function [1, 1, 1, 1, 1; 1] to the majority function implemented by the majority function element 36 is represented as (a, b, c, d, e, 0, 0, 0). Thus, in this case, bits 1-5 are an example of the Boolean input BI with regard to
As another example, a Boolean function of abcd corresponds to a threshold function with a set of weights and a threshold value of [1, 1, 1, 1; 4]. The majority function element 36 is programmable to realize the threshold function of [1, 1, 1, 1; 4] by assigning the bits b1-b8 represented by the bit signals 42 in accordance with the set of weights and the threshold value. Boolean variable, a, is provided as the bit b1 represented by the bit signal 42-1. The Boolean variable, b, is provided as the bit b2 represented by the bit signal 42-2. The Boolean variable, c, is provided as the bit b3 represented by the bit signal 42-3. The Boolean variable, d, is provided as the bit b4 represented by the bit signal 42-4. The bit b5 is provided as a logical 1 represented by the bit signal 42-5. The bit b6 is provided as a logical 1 represented by the bit signal 42-6. The bit b7 is provided as a logical 1 represented by the bit signal 42-7. The bit b8 is provided as a logical 1 represented by the bit signal 42-8. This assignment of the threshold function [1, 1, 1, 1; 4] to the majority function implemented by the majority function element 36 is represented as (a, b, c, d, 1, 1, 1, 1). Thus, in this case, bits 1-4 are an example of the Boolean input BI with regard to
As another example, a Boolean function of ab v (a v b)(cd v de v ce) corresponds to a threshold function with a set of weights and a threshold value of [2, 2, 1, 1, 1; 4]. The majority function element 36 is programmable to realize the threshold function of [2, 2, 1, 1, 1; 4] by assigning the bits b1-b8 represented by the bit signals 42 in accordance with the set of weights and the threshold value. Boolean variable, a, is provided as the bit b1 represented by the bit signal 42-1. The Boolean variable, a, is also provided as the bit b2 represented by the bit signal 42-2. The Boolean variable, b, is provided as the bit b3 represented by the bit signal 42-3. The Boolean variable, b, is also provided as the bit b4 represented by the bit signal 42-4. The Boolean variable, c, is provided as the bit b5 represented by the bit signal 42-5. The Boolean variable, d, is provided as the bit b6 represented by the bit signal 42-6. The Boolean variable, e, is provided as the bit b7 represented by the bit signal 42-7. The bit b8 is provided as a logical 1 represented by the bit signal 42-8. This assignment of the threshold function [2, 2, 1, 1, 1; 4] to the majority function implemented by the majority function element 36 is represented as (a, a, b, b, c, d, e, 1). Thus, in this case, bits 1-7 are an example of the Boolean input BI with regard to
The table above illustrates design parameters for one model of the MTJ element 20. The function lc(d) is for the MTJ element 20 and shows values of the switching current magnitude lc mapped to pulse duration d at various operating points (referred to generically as p and specifically as p1, p2, p3, p4, p5, p6, p7, p8, p9). for the switching current magnitude lc of a population of the MTJ element 20, designed in accordance with the MTJ element 20. While a function lc(d) is actually exponential, the lc(d) is approximately linear over a limited range of the values of the pulse duration d. Error bars (referred to generically as e and specifically as e1, e2, e3, e4, e5, e6, e7, e8, e9) are the operation points p of the function lc(d) due to manufacturing variations in the switching current magnitude lc(d).
More specifically, the error bars e each specify that the signal level of the threshold realization current 40 has a probability of switching a randomly fabricated MTJ element (like the MTJ element 20 with the design parameters in the table above) from the high resistance state to the low resistance state is less than ∈ when the signal level is below a magnitude of lcmin(d) and a probability of 1-∈ when the signal level of the threshold realization current 40 is above the magnitude lcmax(d) indicated by the error bar e. For example, for the error bar e1 at operating point p1 with a pulse duration of 1.6 nanoseconds, the magnitude of lcmin(d) is 165 μA and the magnitude of lcmax(d) is 220 μA. An expected magnitude is 220 μA.
To determine a width w of the transistors 38, simulations were performed with the data for the function lc(d) to ensure that the majority function of k=4 and N=8 is implemented by the majority function element 36. All simulation were performed with a VDD=1V. An onset, M, is equal to the majority value k=4, which is a minimum number of the transistors 38 that are activated with the pulse duration d=1.6 ns such the MTJ element 20 is switched from the high resistance state (and the anti-parallel magnetic orientation alignment state) to the low resistance state (and the parallel magnetic orientation alignment state). An offset, m, is equal to the majority value k minus 1, (i.e., m=k−1), which is the maximum number of the transistors 38 that can be activated without the MTJ element 20 being switched from the from the high resistance state (and the anti-parallel magnetic orientation alignment state) to the low resistance state (and the parallel magnetic orientation alignment state). From the simulations, the width w of the transistors 38 is selected so that the current level of the threshold realization current 40 is generated above the lcmax(d), which in this example is 220 μA at the pulse duration d=1.6 ns, when the number of transistors 38 that are activated is equal to onset, M. Furthermore, from the simulations, the width w of the transistors 38 is selected so that the current level of the threshold realization current 40 is generated below the lcmin(d), which in this example is 165 μA at the pulse duration d=1.6 ns, when the number of transistors 38 that are activated is equal to offset, m. In this manner, the majority function element 36 is fabricated to ensure that the threshold realization current 40 is generated with the signal level above the switching current magnitude lc of the of the MTJ element 20 when a number equal to the onset M (i.e., M=k) of the transistors 38 is activated and with the current level below the switch current magnitude lc of the MTJ element 20 when a number equal to the offset, m, (i.e., m=k−1) of the transistors 38 are activated.
Accordingly, the threshold gate 44 is transparent while the write signal WR is active during the write pulse (write phase). When the threshold gate 44 is transparent and the write signal WR is active (write pulse, write phase) and/or asserted, the current level of the threshold realization current 40 is provided by the majority function element 36 in accordance with the majority function on the bit signals 42, as described above with respect to
The threshold gate 44 further includes a transistor NM1, a transistor NM2, transistor NM3 and another MTJ element 50. The threshold gate 44 shown in
As shown in
The transistors NM2 and the transistor NM3 are configured to generate the differential state signal DSS while the read signal RD is active and/or asserted during a read pulse (read phase). In this embodiment, the transistor NM2 and the transistor NM3 are each N-channel FETs and in particular NMOSs. The gate of the transistor NM2 and the gate of the transistor NM3 both receive a read signal RD. A source of transistor NM2 is connected to the MTJ element 50 while a source of the transistor NM3 is coupled to the MTJ element 20. More specifically, the source of the transistor NM3 is connected between the majority function element 36 and the MTJ element 20. A drain of the transistor NM2 is coupled to a node N5, and a drain of the transistor NM3 is coupled to a node N6. The differential state signal DSS is output from both of the nodes N5, N6.
The differential state generation element 52 is configured to generate the differential state signal DSS such that the differential state signal DSS indicates whether the MTJ element 20 is in the high resistance state (and the anti-parallel magnetic orientation alignment state) or in the low resistance state (and the parallel magnetic orientation alignment state). This is done by asserting the read signal RD, which generates a read pulse (read phase) in the read signal RD and activates the read signal RD. The differential state generation element 52 is thus transparent to the state of the MTJ element 20 when the read signal RD is active and/or asserted during the read pulse (read phase). When read signal RD is active (read pulse, read phase), the transistor NM3 and the transistor NM2 are both enabled. Before the read signal RD is asserted, the voltages at the nodes N5 and N6, i.e., signals REF and ST, are both at the same voltage (whose value is somewhere between VDD and 0). Irrespective of whether the MTJ element 20 is in the high resistive state (Rhigh) or the low resistive state (Rlow), its resistance is never equal to that of the MTJ element 50 (which is (Rhigh+Rlow)/2). Therefore, when the read signal RD is asserted (during the read pulse (read phase)), the transistors NM2 and NM3 are enabled and the nodes N5 and N6 discharge through different resistances. This creates a voltage difference between the nodes N5 and N6 which may be amplified by an external sense amplifier circuit (not shown in
For example, since the TMR of the MTJ element 50 has a TMR value of about ½ the TMR value for the TMR of the MTJ element 20, the transistor NM2 generates a reference signal REF having a reference voltage level. In this embodiment, the reference voltage level of the reference signal REF is at VDD/2. As such, during the read pulse (read phase) and while the read signal RD is active and/or asserted, the reference voltage level (i.e., VDD/2) is provided at the node N5. The reference signal REF is one part of the differential state signal DSS. Also, during the read pulse (read phase) and while the read signal RD is active and/or asserted, the transistor NM6 generates a state signal ST having a state voltage level. The state signal ST is another part of the differential state signal DSS.
If the MTJ element 20 is in the high resistance state (and the anti-parallel magnetic orientation alignment state), the voltage difference between the nodes N5 and N6 is negative, i.e., the voltage at the node N5 is lower than that of the node N6. The external sense amplifier circuit amplifies this difference and produces logical 0 as the output of threshold function. For example, a state voltage level of the state signal ST is approximately equal to VDD. A voltage difference between the reference voltage level of the reference signal VREF and the state voltage level of the state signal ST is thus approximately −VDD/2. In other words, a voltage difference between the node N5 and the node N6 is thus approximately −VDD/2. On the other hand, if the MTJ element 20 is in the low resistance state (and the parallel magnetic orientation alignment state), the nodes N5 and N6 voltage difference is positive and the external sense amplifier amplifies this difference to produce logical 1 as the output of the threshold function. For example, a state voltage level of the state signal ST is approximately equal to a reference voltage level (i.e., in this example, ground). A voltage difference between the reference voltage level of the reference signal VREF and the state voltage level of the state signal ST is thus approximately +VDD/2. In other words, a voltage difference between the node N5 and the node N6 is thus approximately +VDD/2. When the read signal RD is inactive and/or unasserted after the read pulse (read phase), the differential state generation element 52 is opaque to the state of the MTJ element 20.
Next, the threshold gate 44 is also configured to receive a preset signal PR. At a beginning of a clock cycle [after the write pulse (write phase) when the write signal WR is inactive and the read pulse (read phase) of a previous clock cycle], the preset PR may become active and/or be asserted during a preset pulse (preset phase). The transistor NM1 operates as a reset device. In this embodiment, the transistor NM1 is an N-channel FET and more particularly an NMOS. A drain of the transistor NM1 is coupled between the majority function element 36, source of the transistor NM1 is coupled to ground, and a gate of the transistor NM1 is coupled to receive the preset signal PR. More specifically, the MTJ element 20 is coupled between the drain of the transistor NM1 and the gate of the transistor NM1. When the preset signal PR is active and/or asserted during the preset pulse (preset phase), the transistor NM1 generates a reset current RC across the MTJ element 20. The transistor NM1 is configured to generate the reset current RC such that a current level of the reset current RC is greater than the switching current magnitude, but in the opposite direction as the threshold realization current 40. In other words, the reset current RC has a current level greater than the switching current magnitude but a current direction opposite the current direction of the threshold realization current 40. Thus, the transistor NM1 is configured to ensure that the MTJ element 20 is in the high resistance state (and the anti-parallel magnetic orientation alignment state) by generating the reset current RC. For example, if the MTJ element 20 were being held in the high resistance state, the MTJ element 20 would be maintained in the high resistance state in response to the reset current RC. On the other hand, if the MTJ element 20 were being held in the low resistance state, the MTJ element 20 would switch from the low resistance state to the high resistance state in response to the reset current RC.
The write signal WR, the read signal RD, and the preset signal PR are complementary to one another and thus are not asserted at the same time. In other words, the write pulse (write phase), the read pulse (read phase), and preset pulse (preset phase) occur during different time intervals of a clock cycle. The write pulse (write phase), the read pulse (read phase), and preset pulse (preset phase) may be repeated every clock cycle as determined by a clock signal.
During the read pulse (read phase) and while the read signal RD is active and/or asserted, the sense amplifier element SA is configured to generate a first logic state signal 62 and a second logic state signal 64 in accordance with the voltage difference of the differential state signal DSS. The first logic state signal 62 and the second logic state signal 64 are logically inverted with respect to one another during the read pulse (read phase) and while the read signal RD is active and/or asserted. Accordingly, when the voltage difference of the differential state signal DSS between the node N5 and the node N6 is negative (for example, −VDD/2), the sense amplifier element SA generates the first logic state signal 62 with a high voltage state (logical 1) (which in this example is around VDD) and the second logic state signal 64 with a low voltage state (logical 0), (which in this example is around ground). Thus, as a result of the MTJ element 20 being in the high resistance state (and the anti-parallel magnetic orientation alignment), the first logic state signal 62 has the high voltage state (logical 1) and the second logic state signal 64 has the low voltage state (logical 0). On the other hand, when the voltage difference of the differential state signal DSS between the node N5 and the node N6 is positive (for example, +VDD/2), the sense amplifier element SA generates the first logic state signal 62 with a low voltage state (logical 0) (which in this example is around ground) and the second logic state signal 64 with a high voltage state (logical 1), (which in this example is around VDD). Thus, as a result of the MTJ element 20 being in the low resistance state (and the parallel magnetic orientation alignment), the first logic state signal 62 has the low voltage state (logical 1) and the second logic state signal 64 has the low voltage state (logical 0).
The latch L also is configured to receive the read signal RD. In this embodiment, the latch L is transparent during the read pulse (read phase) and while the read signal RD is active and/or asserted. In this embodiment, the latch L thus generates a bit output signal Q and an inverted bit output signal
Outside the read pulse (read phase) and while the read signal RD is inactive and/or unasserted, the latch L is configured to be opaque to the first logic state signal 62 and the second logic state signal 64 and to hold the voltage state of the bit output signal Q and the voltage state of the inverted bit output signal
Letters (i.e., A and B) indicate a row of the threshold logic array 66. More specifically, within the threshold logic block, the Letter A indicates an upper row pair of threshold gates 44(A)(1) and 44(A)(2). Letter B indicates an low row pair of the threshold gates 44(B)(1) and 44(B)(2). Generically, the threshold gates 44(A)(1) and 44(A)(2) in the upper row pair and the threshold gates 44(B)(1) and 44(B)(2) in the lower row pair may be referred to as a row pair of the threshold gates 44(1) and 44(2). Also, generically, the differential state signal DSS(A)(1) and differential state signal DSS(A)(2) for the upper row pair and the differential state signal DSS(B)(1) and differential state signal DSS(B)(2) for the lower row pair may be referred to as the differential state signal DSS(1) and differential state signal DSS(2).
Numbers (i.e., 1 and 2) indicate a column of the threshold logic array 66. More specifically, within the threshold logic block, the number 1 indicates a left column pair the threshold gates 44(A)(1) and 44(B)(1). Number 2 indicates an right column pair of the threshold gates 44(A)(2) and 44(B)(2). Generically, the threshold gates 44(A)(1) and 44(B)(1) in the left column pair and the threshold gates 44(A)(2) and 44(B)(2) in the right column pair may be referred to as a column pair of the threshold gates 44(A) and 44(B). Also, generically, the differential state signal DSS(A)(1) and differential state signal DSS(B)(1) for the left row pair and the differential state signal DSS(A)(2) and differential state signal DSS(B)(2) for the right column pair may be referred to as the differential state signal DSS(A) and differential state signal DSS(B).
In this embodiment, a sequential state threshold logic element 68A includes the upper row pair of threshold gates 44(A)(1) and 44(A)(2). The sequential state threshold logic element 68A has a sense amplifier element SA(A) and an SR latch L(A). The sense amplifier element SA(A) receives both the differential state signal DSS(A)(1) from the threshold gate 44(A)(1) and the DSS(A)(2) the differential state signal DSS(A)(2). The sense amplifier element SA(A) is configured to generate a first logic state signal 62(A) as a set signal for the SR latch L(A) and a second logic state signal 64A as a reset signal for the SR latch L(A).
A sequential state threshold logic element 68B includes the low row pair of threshold gates 44(B)(1) and 44(B)(2). The sequential state threshold logic element 68B has a sense amplifier element SA(B) and an SR latch L(B). The sense amplifier element SA(B) receives both the differential state signal DSS(B)(1) from the threshold gate 44(B)(1) and the DSS(B)(2) the differential state signal DSS(B)(2). The sense amplifier element SA(B) is configured to generate a first logic state signal 62(B) as a set signal for the SR latch L(B) and a second logic state signal 64(B) as a reset signal for the SR latch L(B). Generically, the sequential state threshold logic elements 68A, 68B are referred to as sequential state threshold logic element 68 since both have the same topology.
A control circuit is configured to generate the preset signal PR, a write signal WR_1, a receive signal RD_1, a write signal WR_2, and a read signal RD_2. All of the threshold gates 44(A)(1), 44(A)(2), 44(B)(1), 44(B)(2) receive the preset signal PR. The left column pair of threshold gates 44(A)(1) and 44(B)(1) each receive the write signal WR_1 and the read signal RD_1. The right column pair of threshold gates 44(A)(1) and 44(B)(1) each receive the write signal WR_2 and the read signal RD_2. Thus, for each of the sequential state threshold logic elements 68, the threshold gate 44(1) receives the write signal WR_1 and the read signal RD_1. The threshold gate 44(2) receives the write signal WR_2 and the read signal RD_2. In each of the sequential state threshold logic elements 68 (i.e., both 68A, 68B), the sense amplifier element SA (i.e., both SA(A) and SA(B)) receive the OR of both of the read signals RD_1 and RD_2 (collectively called an RD signal). This OR gate (not shown explicitly) ensures that sense amplifiers SA(A) and SA(B) are active when either the read signal RD_1 is active (column 1 is active) or the read signal RD_2 is active (column 2 is active).
Feedforward device 70A and feedforward device 70B may include multiplexers and/or decoding circuits configured to route the appropriate bit signals through the bit lines a-z to the threshold gates 44(A)(1), 44(A)(2), 44(B)(1), 44(B)(2). The setup and hold timing for the bit signals on bit lines may be timed by a clock signal Clk, so that the feedforward device 70A and feedforward device 70 transfer the bit output signal Q and the inverted bit output signal
Referring now to
The read signal RD_1 is then asserted (i.e., read pulse RP1 is provided) and the threshold gate 44(A)(1) generates the differential state signal DSS(A)(1) and the threshold gate 44(B)(1) generates the differential state signal DSS(B)(1). The sense amplifier element SA(A) generates the first logic state signal 62(A) and the second logic state signal 64(A) in accordance with the differential state signal DSS(A)(1). As a result, the SR latch L(A) then generates the bit output signal Q(A) and the inverted bit output signal
The bit output signal Q(A) and the inverted bit output signal
The read signal RD_2 is then asserted (i.e., read pulse RP2 is provided) and the threshold gate 44(A)(2) generates the differential state signal DSS(A)(2) and the threshold gate 44(B)(2) generates the differential state signal DSS(B)(2). The sense amplifier element SA(A) generates the first logic state signal 62(A) and the second logic state signal 64(A) in accordance with the differential state signal DSS(A)(2). As a result, the SR latch L(A) then generates the bit output signal Q(A) and the inverted bit output signal
Each of the threshold gates 44(1) and 44(2) in the row pair receive the preset signal PR. The majority function element 36(1) receives the write signal, WR_1 and the transistor NM21 and the transistor NM31 receive the read signal RD_1. The majority function element 36(1) thus implements its corresponding majority function and thus determines the state of the MTJ element 20(1) when the write signal WR_1 is asserted. The transistor NM21 and the transistor NM31 generate the differential state signal DSS(1) (the differential state signal DSSA(1) for sequential state threshold logic element 68A in
Alternatively or additionally, the gates of the PMOSs PM1 and PM2 receive an output from an OR gate, wherein the read signals RD_1, RD_2 are inputs to the OR gate (i.e., output is equal to RD_1 v RD_2). Alternatively, threshold gates may be implemented where the first resistive state is a low resistive state and second resistive state is a high resistive state. During the write pulse, enough active transistors switch the MTJ element from a low resistive state to a higher resistive state, and not otherwise. The preset signal PR now ensures that the MTJ element starts in a low resistive state before application of the write pulse. The simplest change to accommodate the reversed meaning of final resistive states of MTJ element is to interchange the nodes N1 and N2 (i.e., interchange their connections to the S and R inputs of the SR latch) in the sense amplifier element SA shown in
A gate of the PMOS PM1 receives the read signals, RD_1, RD_2, i.e., RD_1 v RD_2. Additionally, a gate of the PMOS PM2 also receives the read signals RD_1, RD_2. The gates of the PMOS PM1 and PMOS PM2 are both in a low voltage state (ground) when both of the read signals, RD_1, RD_2 are unasserted. Thus, when both of the read signals RD_1, RD_2 are unasserted, the PMOS PM1 and the PMOS PM2 are activated and the nodes N1 and N2 are pre-charged to a high voltage state (˜VDD). This is called a reset phase. During the reset phase, the nodes N5 and N6 are both at VDD-Vth. In contrast, the gates of the PMOS PM1 and the PMOS PM2 are both at the high voltage state when any of the read signals RD_1, RD_2 is asserted. Accordingly, the PMOS PM1 and the PMOS PM2 are both deactivated (turned OFF) when any one of the read signals RD_1, RD_2 is asserted, i.e., in an evaluation phase.
Accordingly, there are two evaluation phases during each clock cycle. When the read signal RD_1 is asserted and the read signal RD_2 is unasserted (first evaluation phase), the sense amplifier element SA evaluates the state of the MTJ element 20(1) based on the DSS(1). If the MTJ element 20(1) is in the high resistance state (and the anti-parallel magnetic orientation alignment), the DSS(1) has a negative voltage level difference from the node N5 to the node N6. Accordingly, more current is drawn from the node N2 than the node N1. Thus, the node N2 discharges faster than the node N1. As a result, the PMOS PM4 is activated, pulling the node N1 to a high voltage state (˜VDD and a logical 1) and the node N2 to a low voltage state (˜ground and a logical 0). In contrast, if the MTJ element 20(1) is in the low resistance state (and the parallel magnetic orientation alignment), the DSS(1) has a positive voltage level difference from the node N5 to the node N6. As a result, more current is drawn from the node N1 than the node N2. Thus, the node N1 discharges faster than the node N2. As a result, the PMOS PM3 is activated, pulling the node N2 to a high voltage state (˜VDD and a logical 1) and the node N1 to a low voltage state (˜ground and a logical 0).
When the read signal RD_2 is asserted and the read signal RD_1 is unasserted (second evaluation phase), the sense amplifier element SA evaluates the state of the MTJ element 20(2) based on the DSS(2). If the MTJ element 20(2) is in the high resistance state (and the anti-parallel magnetic orientation alignment), the DSS(2) has a negative voltage level difference from the node N5 to the node N6. Accordingly, more current is drawn from the node N2 than the node N1. Thus, the node N2 discharges faster than the node N1. As a result, the PMOS PM4 is activated, pulling the node N1 to a high voltage state (˜VDD and a logical 1) and the node N2 to a low voltage state (˜ground and a logical 0). In contrast, if the MTJ element 20(2) is in the low resistance state (and the parallel magnetic orientation alignment), the DSS(2) has a positive voltage level difference from the node N5 to the node N6. As a result, more current is drawn from the node N1 than the node N2. Thus, the node N1 discharges faster than the node N2. As a result, the PMOS PM3 is activated, pulling the node N2 to a high voltage state (˜VDD and a logical 1) and the node N1 to a low voltage state (˜ground and a logical 0). The nodes N1 and N2 provide the first logic state signal 62 (the first logic state signal 62A for the sequential state threshold logic element 68A in
The threshold gate 44(B)(1) has been programmed to compute a carry, with Boolean variables B1, A1, A0, B0, Cin. As such, a majority function element (like the majority function element 36 shown in
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
This application claims the benefit of provisional patent application Ser. No. 61/651,646, filed May 25, 2012, the disclosure of which is hereby incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61651646 | May 2012 | US |
