Claims
- 1. A method of isolation fabrication of an integrated circuit having a surface with active regions, with at least some of said active regions containing NMOS transistors, said method comprising:
- a. growing a field oxide on regions of the surface, said field oxide having at least two different widths, with some of said widths being substantially greater than 1 micron, and with some of said widths being less than about 1 micron, with said growing of field oxide creating an oxide-silicon interface beneath said oxide; and
- b. implanting channel stop dopants in said integrated circuit without active area masking, said implanting being at an energy high enough to implant channel stop dopants through field oxide in regions having widths less than about 1 micron to provide a maximum of implanting channel stop dopants in silicon under said oxide-silicon interface, but with said implanting being at an energy low enough to provide a maximum of implanting channel stop dopants within said field oxide regions having widths substantially greater than 1 micron.
- 2. The method of claim 1, wherein:
- (a) said channel stop dopants are boron; and
- (b) said active device regions are moats to be doped n or p type for n and p channel field effect transistor active devices.
- 3. The method of claim 2, wherein:
- said implant of channel stop dopants is performed with the dopant ion beam aligned to provide maximal channeling of the dopant ions in the active device regions.
Parent Case Info
This is a division, of application Ser. No. 07/038,388, filed Apr. 15, 1987 now U.S. Pat. No. 4,890,147.
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Date |
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3860454 |
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Jan 1975 |
|
4261761 |
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Non-Patent Literature Citations (1)
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Tsai et al., IEEE Electron Device Letters, vol. 10, No. 7 (Jul. 1989), pp. 307-309. |
Divisions (1)
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Number |
Date |
Country |
Parent |
38388 |
Apr 1987 |
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