Patent Application
20250089310
As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, reducing the size of memory and logic cells is becoming increasingly more difficult, as is reducing device spacing at the device layer. As transistors are packed more densely, the formation of certain device structures used to isolate adjacent transistors becomes challenging. Accordingly, there remain a number of non-trivial challenges with respect to forming semiconductor devices.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used.
Techniques are provided herein to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to device layer transistors, such as finFETs or gate-all-around transistors (e.g., ribbonFETs and nanowire FETs). In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. The semiconductor regions can be, for example, fins of semiconductor material or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend between the first and second source or drain regions along a first direction while the gate structure extends over the semiconductor regions along a second direction. A structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. The structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). In either case, an airgap spacer exists between the structure and the gate structure. The presence of the airgap spacer provides a region with a very low dielectric constant (e.g., around 1.0) between the structure and the adjacent gate structure, thus reducing the parasitic capacitance in the device. Numerous variations and embodiments will be apparent in light of this disclosure.
As previously noted above, there remain a number of non-trivial challenges with respect to integrated circuit fabrication. In more detail, as devices become smaller and more densely packed, many structures become more challenging to fabricate as critical dimensions (CD) of the structures push the limits of current fabrication technology. Example through-gate structures like gate cuts or vias are used in integrated circuit design to isolate gate structures from one another and (in the case of vias) provide a signal or power routing path to backside interconnects. Such gate cuts may be relatively thin and are thus filled with a robust high-k dielectric material (e.g., a material with a dielectric constant of 6.5 or greater, such as silicon nitride). Similarly, via structures may have a dielectric liner along its edges that includes a high-k dielectric material. But the use of such high-k materials can lead to high parasitic capacitance between the conductive gate electrode on either side of the gate cut or via. Using a low-k dielectric material instead can help to reduce such parasitic capacitance. However, low-k materials usually include an oxygen component, and deposition of oxygen-containing dielectric materials implicates oxidation risk of the underlying material(s). Also, deposition of oxygen-containing dielectric materials includes ion flux. Such factors can cause shifting in electrical properties of the underlying material(s). Also, oxygen-rich low-k dielectric materials may not be robust enough to withstand erosion caused by, for example, downstream processing and planarization.
Thus, and in accordance with an embodiment of the present disclosure, an integrated circuit is disclosed that includes one or more through-gate structures (gate cut structures or conductive via structures) having an airgap spacer between the through-gate structure and the adjacent gate electrode. Additionally, the through-gate structures may extend in a first direction to be adjacent to source or drain regions and the airgap spacer also exists between the through-gate structure and the adjacent source or drain regions. According to some embodiments, a deep recess is formed through at least an entire thickness of the gate structure and adjacent to a semiconductor region that extends in the first direction between source or drain regions. The deep recess may also extend through at least a portion of an entire thickness of a dielectric layer beneath the gate structure. A sacrificial layer may be formed along walls of the deep recess and the through-gate structure is then formed on the sacrificial layer. Following the formation of the semiconductor devices and any back-end-of-the-line (BEOL) processes, the substrate may be removed from the backside, exposing a bottom surface of the through-gate structure and the sacrificial layer along the edges of the through-gate structure. The sacrificial layer may then be removed from the backside, leaving behind an airgap spacer having substantially the same width as the sacrificial layer. The sacrificial layer may be aluminum oxide and may have a thickness of less than 10 nm.
According to an embodiment, an integrated circuit includes a semiconductor device having a semiconductor region extending in a first direction from a source or drain region and a gate structure extending in a second direction over the semiconductor region, a dielectric layer beneath the gate structure, and a structure spaced from the semiconductor region in the second direction and extending in a third direction along an entire thickness of the gate structure and along an entire thickness of the dielectric layer. An airgap exists between the structure and the gate structure and between the structure and the dielectric layer.
According to another embodiment, an integrated circuit includes a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region, a first dielectric layer beneath the gate structure, a conductive structure spaced from the semiconductor region in the second direction and extending in a third direction along an entire thickness of the gate structure and along an entire thickness of the dielectric layer, and a second dielectric layer over the gate structure and on a top surface of the conductive structure. An airgap exists between the conductive structure and the gate structure and between the conductive structure and the dielectric layer.
According to another embodiment, a method of forming an integrated circuit includes forming a fin comprising semiconductor material, the fin extending above a substrate and extending in a first direction; forming a dielectric layer adjacent to a subfin portion of the fin; forming source or drain regions at opposite ends of the fin; forming a gate structure on the dielectric layer and over the semiconductor material and extending in a second direction; forming a recess through an entire thickness of the gate structure and through an entire thickness of the dielectric layer; forming a sacrificial layer along sidewalls and a bottom surface of the recess; forming a conductive material on the sacrificial layer within the recess; removing the substrate from the backside of the integrated circuit, wherein the removing exposes a bottom surface of the conductive material; and removing the sacrificial layer from the backside to form an airgap between the conductive material and the gate structure and between the conductive material and the dielectric layer.
The techniques can be used with any type of non-planar transistors, including finFETs (sometimes called tri-gate transistors), nanowire and nanoribbon transistors (sometimes called gate-all-around transistors), or forksheet transistors, to name a few examples. The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions that are deposited during an etch-and-replace source/drain forming process. The dopant-type in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate-first process or a gate-last process (sometimes called a replacement metal gate, or RMG, process). Any number of semiconductor materials can be used in forming the transistors, such as group IV materials (e.g., silicon, germanium, silicon germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).
Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. For instance, in some example embodiments, such tools may indicate the presence of airgaps along the edges of through-gate structures (e.g., gate cuts or vias). The airgaps may extend along an entire interface between a given through-gate structure and the adjacent gate electrode. In some embodiments, airgaps are also present between the through-gate structures and adjacent source or drain regions along a given source/drain trench.
It should be readily understood that the meaning of “above” and “over” in the present disclosure should be interpreted in the broadest manner such that “above” and “over” not only mean “directly on” something but also include the meaning of over something with an intermediate feature or a layer therebetween. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the term “layer” refers to a material portion including a region with a thickness. A monolayer is a layer that consists of a single layer of atoms of a given material. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure, with the layer having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A layer can be conformal to a given surface (whether flat or curvilinear) with a relatively uniform thickness across the entire layer.
Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer. If two materials are elementally different, then one of the materials has an element that is not in the other material.
Each of the semiconductor devices may be, for example, non-planar metal oxide semiconductor (MOS) transistors, such as tri-gate (e.g., finFET) or gate-all-around (GAA) transistors, although other transistor topologies and types could also benefit from the techniques provided herein. The illustrated example embodiments use the GAA structure. The various illustrated semiconductor devices represent a portion of an integrated circuit that may contain any number of similar semiconductor devices.
As can be seen, the semiconductor devices may be formed over a dielectric base layer 102. In some embodiments, a lower portion of (or all of) the substrate beneath dielectric base layer 102 is removed and replaced with one or more backside interconnect layers to form, for example, backside signal and power routing, during a backside process. Dielectric base layer 102 may represent any number of deposited dielectric materials, and may include different dielectric materials such as silicon dioxide, silicon oxynitride, silicon nitride, and/or silicon oxycarbonitride.
Each of the semiconductor devices includes one or more corresponding nanoribbons 104 that extend parallel to one another along a first direction between corresponding source or drain regions as seen more clearly in
The term nanoribbon may also encompass other similar shapes such as nanowires or nanosheets. The semiconductor material of nanoribbons 104 may be formed from a semiconductor substrate. In some embodiments, the semiconductor devices may each include semiconductor regions in the shape of fins that can be, for example, native to the substrate (formed from the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins can be formed of material deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In another such example, non-native fins can be formed in a so-called aspect ratio trapping based process, where native fins are etched away so as to leave fin-shaped trenches which can then be filled with an alternative semiconductor material (e.g., group IV or III-V material). In still other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate forming of the illustrated nanoribbons 104 during a gate forming process where one type of the alternating layers is selectively etched away so as to liberate the other type of alternating layers within the channel region, so that a gate-all-around (GAA) process can then be carried out. Again, the alternating layers can be blanket deposited and then etched into fins or deposited into fin-shaped trenches.
According to some embodiments, the source or drain regions are epitaxial regions that are provided using an etch-and-replace process. In other embodiments the source or drain regions could be, for example, implantation-doped native portions of the semiconductor fins or substrate. Any semiconductor materials suitable for source and drain regions can be used (e.g., group IV and group III-V semiconductor materials). The composition and doping of the source or drain regions may be the same or different, depending on the polarity of the transistors. In an example, for instance, one transistor is a p-type MOS (PMOS) transistor, and the other transistor is an n-type MOS (NMOS) transistor. As such, source or drain region 106 may have a different dopant type (n or p) compared to any other source or drain region 106 along a given source/drain trench. Any number of source or drain configurations and materials can be used.
According to some embodiments, a lower dielectric layer 108 exists beneath source or drain regions 106. Lower dielectric layer 108 can include any suitable dielectric material, such as silicon dioxide or silicon nitride or silicon oxynitride and may be provided to isolate source or drain regions 106 from other underlying structures. According to some embodiments, another dielectric fill 110 is provided around and/or over portions of source or drain regions 106 along the source/drain trench after epitaxial formation of the source/drain regions is complete. Dielectric fill 110 may be any suitable dielectric material, although in some embodiments, dielectric fill 110 includes the same dielectric material within dielectric base layer 102 or lower dielectric layer 108. In one example, each of dielectric fill 110, lower dielectric layer 108, and dielectric base layer 102 includes silicon dioxide. According to some embodiments, any number of conductive contacts 112 may be formed on corresponding source or drain regions 106. According to some embodiments, conductive contacts 112 may be any suitably conductive material such as tungsten (W). Other conductive materials may include copper (Cu), ruthenium (Ru), cobalt (Co), titanium (Ti), molybdenum (Mo), or any alloys thereof. Conductive contacts 112 may be formed directly on a top surface of source or drain regions 106 and may extend along portions of the sides of source or drain regions 106.
According to some embodiments, a gate structure extends over nanoribbons 104 of each semiconductor device along a second direction across the page of
Gate electrode 116 may represent any number of conductive layers, such as any metal, metal alloy, or doped polysilicon layers. In some embodiments, gate electrode 116 includes one or more workfunction metals around nanoribbons 104. In some embodiments, one of the semiconductor devices is a p-channel device that includes a workfunction metal having titanium around its nanoribbons and another semiconductor device is an n-channel device that includes a workfunction metal having tungsten around its nanoribbons. Gate electrode 116 may also include a fill metal or other conductive material around the workfunction metals to provide the whole gate electrode structure. In some embodiments, a gate cap 118 may be provided on a top surface of gate electrode 116 within the gate trench. Gate cap 118 may be any suitable dielectric material, such as silicon oxynitride, silicon nitride, or silicon oxycarbonitride.
According to some embodiments, a first interconnect layer above the semiconductor devices includes a dielectric interconnect layer 120. Dielectric interconnect layer 120 may have any number of conductive vias or conductive layers present within it. Dielectric interconnect layer 120 may include any suitable dielectric material, such as silicon dioxide.
According to some embodiments, various through-gate structures are present that pass across the gate trench in the first direction and through an entire thickness of the gate structure in a third direction. For example, a conductive via structure 122 may extend along the first direction through the gate structure and across the source/drain trench to pass adjacent to source or drain regions 106, as illustrated in
Another example through-gate structure includes a gate cut 130. According to some embodiments, gate cut 130 may also extend along the first direction through the gate structure and across the source/drain trench to pass adjacent to source or drain regions 106, as illustrated in
In some embodiments, the transistor structures are very densely packed such that there is little space between adjacent source or drain regions 106 along the second direction. In such examples, any of airgaps 128a-128b or airgaps 134a-134b may directly abut or expose a portion of the adjacent source or drain regions 106.
Substrate 201 can be, for example, a bulk substrate including group IV semiconductor material (such as silicon, germanium, or silicon germanium), group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and/or any other suitable material upon which transistors can be formed. Alternatively, substrate 201 can be a semiconductor-on-insulator substrate having a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, substrate 201 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers indium gallium arsenide and indium phosphide). Any number of substrates can be used.
According to some embodiments, sacrificial layers 202 have a different material composition than semiconductor layers 204. In some embodiments, sacrificial layers 202 are silicon germanium (SiGe) while semiconductor layers 204 include a semiconductor material suitable for use as a nanoribbon such as silicon (Si), SiGe, germanium, or III-V materials like indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layers 202 and in semiconductor layers 204, the germanium concentration is different between sacrificial layers 202 and semiconductor layers 204. For example, sacrificial layers 202 may include a higher germanium content compared to semiconductor layers 204. In some examples, semiconductor layers 204 may be doped with either n-type dopants (to produce a p-channel transistor) or p-type dopants (to produce an n-channel transistor).
While dimensions can vary from one example embodiment to the next, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm), and the thickness of each of semiconductor layers 204 may be about the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of sacrificial layers 202 and semiconductor layers 204 may be deposited using any known or proprietary material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
According to some embodiments, an anisotropic etching process through the layer stack continues into at least a portion of substrate 201, where the unetched portions of substrate 201 beneath the fins form subfin regions 304. The etched portions of substrate 201 may be filled with a dielectric fill 306 that acts as shallow trench isolation (STI) between adjacent fins. Dielectric fill 306 may be any suitable dielectric material such as silicon dioxide, and may be recessed to a desired depth as shown (in this example case, down to around the upper surface of subfin regions 304), so as to define the active portion of the fins that will be covered by a gate structure. In some embodiments, dielectric fill 306 is recessed below the top surface of subfin regions 304.
As seen in the cross-section views, sacrificial gate 402 extends across the fins along the gate trench cross-section of
According to some embodiments, a bottom dielectric layer 504 may be deposited prior to the formation of source or drain regions 502. Bottom dielectric layer 504 may be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. Bottom dielectric layer 504 may be included to provide isolation between source or drain regions 502 and subfin regions 304.
According to some embodiments, another dielectric fill 506 is provided along the source/drain trench. Dielectric fill 506 may extend between adjacent ones of the source or drain regions 502 along the second direction and also may extend up and over each of the source or drain regions 502, according to some embodiments. Accordingly, each source or drain region may be isolated from any adjacent source or drain regions by dielectric fill 506. Dielectric fill 506 may be any suitable dielectric material, although in some embodiments, dielectric fill 506 includes the same dielectric material as dielectric fill 306 or bottom dielectric layer 504. In one example, each of dielectric fill 506, bottom dielectric layer 504, and dielectric fill 306 includes silicon dioxide. Dielectric fill 506 may not be present between certain adjacent source or drain regions in situations where the adjacent source or drain regions are desired to be electrically coupled together. According to some embodiments, a top surface of dielectric fill 506 may be polished using, for example, chemical mechanical polishing (CMP). The top surface of dielectric fill 506 may be polished until it is substantially coplanar with a top surface of sacrificial gate 402.
Gate electrode 704 may be deposited over gate dielectric 702 and can be any conductive structure. In some embodiments, gate electrode 704 includes doped polysilicon, a metal, or a metal alloy. Example suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. Gate electrode 704 may include, for instance, one or more workfunction layers, resistance-reducing layers, and/or barrier layers. The workfunction layers can include, for example, p-type workfunction materials (e.g., titanium nitride) for PMOS gates, or n-type workfunction materials (e.g., titanium aluminum carbide) for NMOS gates.
According to some embodiments, a gate cap 706 may be formed by first recessing gate electrode 704 and filling the recess with a dielectric material. The dielectric material may then be polished such that its top surface is substantially coplanar with any adjacent spacer structures or material within the source/drain trench. Gate cap 706 may be any suitable dielectric material, such as silicon nitride.
According to some embodiments, a portion of dielectric fill 506 may be recessed within the source/drain trench to expose at least a top surface of source or drain regions 502. A conductive contact 708 may be formed within the recess to contact at least the top surfaces of source or drain regions 502. In some embodiments, dielectric fill 506 is recessed far enough to expose one or more side surfaces of source or drain regions 502, in which case conductive contact 708 also contacts the exposed side surfaces of source or drain regions 502. Conductive contact 708 may include any suitable conductive material, such as tungsten, molybdenum, or ruthenium, for making electrical contact with the underlying source or drain regions 502. A top surface of conductive contact 708 may be polished to be substantially coplanar with a top surface of gate cap 706.
Deep recesses 802/804 may be formed by etching through gate electrode 704 using any suitable metal gate etch process that iteratively etches through portions of gate electrode 704 while simultaneously protecting the sidewalls of the recess from lateral etching to provide a high height-to-width aspect ratio recess (e.g., aspect ratio of 5:1 or higher, or 10:1 or higher). Deep recesses 802/804 may extend in the first direction through multiple gate trenches and source/drain trenches to isolate adjacent gate structures and source or drain regions. Accordingly, deep recesses 802/804 may extend in the first direction through the source/drain trench and separate adjacent source or drain regions 502 from one another. An anisotropic RIE process may be performed to etch through the various materials to form deep recesses 802/804.
First airgaps 1602 and second airgaps 1604 may have substantially the same thickness (e.g., less than 10 nm ) as they are formed from the removal of the same sacrificial layer 902. In some examples, the thickness of first airgaps 1602 and second airgaps 1604 is between about 5 nm and about 7 nm. According to some embodiments, the first interconnect layer spans across the top of first airgaps 1602 and second airgaps 1604. For example, conductive interconnect layer 1404 extends across the top of one of first airgaps 1602 to contact both the conductive via and conductive contact 708. A backside interconnect layer may also be formed that bridges across the bottom of first airgaps 1602 and/or second airgaps 1604. The airgaps provide a region of very low dielectric constant (around 1.0) between the conductive via and adjacent conductive structures (e.g., gate electrode 704 and contact 708), thus reducing the parasitic capacitance. It should be noted that first airgaps 1602 and second airgaps 1604 may include an inert gas (e.g., argon) or no appreciable gas at a vacuum pressure.
The conductive via may not extend through all gate trenches along the first direction.
As can be further seen, chip package 1800 includes a housing 1804 that is bonded to a package substrate 1806. The housing 1804 may be any housing, and may provide, for example, electromagnetic shielding and environmental protection for the components of chip package 1800. The one or more dies 1802 may be conductively coupled to a package substrate 1806 using connections 1808, which may be implemented with any number of connection mechanisms, such as solder bumps, ball grid array (BGA), pins, or wire bonds, to name a few examples. Package substrate 1806 may be any package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between the faces of package substrate 1806, or between different locations on each face. In some embodiments, package substrate 1806 may have a thickness less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of package geometries can be used. Additional conductive contacts 1812 may be disposed at an opposite face of package substrate 1806 for conductively contacting, for instance, a printed circuit board (PCB). One or more vias 1810 extend through a thickness of package substrate 1806 to provide conductive pathways between one or more of connections 1808 to one or more of contacts 1812. Vias 1810 are illustrated as single straight columns through package substrate 1806 for case of illustration, although other configurations can be used (e.g., damascene, dual damascene, through-silicon via, or an interconnect feature that meanders through the thickness of substrate 1806 to contact one or more intermediate locations therein). In still other embodiments, vias 1810 are fabricated by multiple smaller stacked vias, or are staggered at different locations across package substrate 1806. In the illustrated embodiment, contacts 1812 are solder balls (e.g., for bump-based connections or a ball grid array arrangement), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). In some embodiments, a solder resist is disposed between contacts 1812, to inhibit shorting.
In some embodiments, a mold material 1814 may be disposed around the one or more dies 1802 included within housing 1804 (e.g., between dies 1802 and package substrate 1806 as an underfill material, as well as between dies 1802 and housing 1804 as an overfill material). Although the dimensions and qualities of the mold material 1814 can vary from one embodiment to the next, in some embodiments, a thickness of mold material 1814 is less than 1 millimeter. Example materials that may be used for mold material 1814 include epoxy mold materials, as suitable. In some cases, the mold material 1814 is thermally conductive, in addition to being electrically insulating.
Method 1900 begins with operation 1902 where any number of parallel semiconductor fins are formed, according to some embodiments. The semiconductor material in the fins may be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed of material deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In another such example, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitates forming of nanowires and nanoribbons during a gate forming process where one type of the alternating layers are selectively etched away so as to liberate the other type of alternating layers within the channel region, so that a gate-all-around (GAA) process can then be carried out. The alternating layers can be blanket deposited and then etched into fins, or deposited into fin-shaped trenches. The fins may also include a cap structure over each fin that is used to define the locations of the fins during, for example, an RIE process. The cap structure may be a dielectric material, such as silicon nitride.
According to some embodiments, a dielectric layer is formed around subfin portions of the one or more fins. In some embodiments, the dielectric layer extends between each pair of adjacent parallel fins and runs lengthwise in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate and the dielectric layer may be formed within the recessed portions of the substrate. Accordingly, the dielectric layer acts as shallow trench isolation (STI) between adjacent fins. The dielectric layer may be any suitable dielectric material, such as silicon dioxide.
Method 1900 continues with operation 1904 where a sacrificial gate and spacer structures are formed over the fins. The sacrificial gate may be patterned using a gate masking layer in a strip that runs orthogonally over the fins (many gate masking layers and corresponding sacrificial gates may be formed parallel to one another (e.g., forming a cross-hatch pattern with the fins). The gate masking layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate may be formed from any suitable material that can be selectively removed at a later time without damaging the semiconductor material of the fins. In one example, the sacrificial gate includes polysilicon. The spacer structures may be deposited and then etched back such that the spacer structures remain mostly only on sidewalls of any exposed structures. According to some embodiments, the spacer structures may be any suitable dielectric material, such as silicon nitride or silicon oxynitride.
Method 1900 continues with operation 1906 where source or drain regions are formed at the ends of the semiconductor regions of each of the fins. Any portions of the fins not protected by the sacrificial gate and spacer structures may be removed using, for example, an anisotropic etching process followed by the epitaxial growth of the source or drain regions from the exposed ends of the semiconductor layers in the fins. In some example embodiments, the source or drain regions are NMOS source or drain regions (e.g., epitaxial silicon) or PMOS source or drain regions (e.g., epitaxial SiGe). A dielectric fill may be formed around and over the tops of the source or drain regions along the source/drain trench. The dielectric fill may include any suitable dielectric material, such as silicon dioxide or silicon oxynitride.
Method 1900 continues with operation 1908 where the sacrificial gate is replaced with a gate structure. According to some embodiments, the sacrificial gate may be removed along with any sacrificial layers within the exposed fins between the spacer structures (in the case of GAA structures). A gate structure may then be formed in place of the sacrificial gate. The gate structure may include both a gate dielectric and a gate electrode. The gate dielectric is first formed over the exposed semiconductor regions between the spacer structures followed by forming the gate electrode within the remainder of the trench between the spacer structures, according to some embodiments. The gate dielectric may include any number of dielectric layers deposited using a CVD process, such as ALD. The gate electrode can include any conductive material, such as a metal, metal alloy, or polysilicon. The gate electrode may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name a few examples.
According to some embodiments, contacts are formed over the source or drain regions. The contacts may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, or cobalt. The contact may include any number of different conductive materials and may extend over the top surfaces of any number of source or drain regions within the source/drain trench.
Method 1900 continues with operation 1910 where a deep recess is formed through at least an entire thickness of the gate structure. According to some embodiments, a trench recess may be etched through both the gate structure and through the dielectric fill around the source or drain regions, such that the trench recess extends along the first direction across both the gate trench and the source/drain trench. The trench recess may extend substantially parallel and lengthwise to the fins or nanowires. A reactive ion etching (RIE) process may be used to cut through the various material layers and form the trench. In some embodiments, the trench extends deep enough to extend through an entire thickness of the dielectric layer beneath the gate structure and expose the substrate beneath the dielectric layer.
Method 1900 continues with operation 1912 where a sacrificial layer is formed within the trench recess. According to some embodiments, the sacrificial layer is formed at least on the sidewalls of the trench recess and may also form on the bottom surface of the trench recess. The sacrificial layer may have a thickness of less than 10 nm , or between 5 and 7 nm. In some examples, the sacrificial layer includes aluminum oxide. The sacrificial layer may be formed using a conformal deposition process to produce a layer having substantially the same thickness on both trench recess sidewalls. An example conformal deposition process is ALD.
Method 1900 continues with operation 1914 where a conductive via is formed on the sacrificial layer within the trench recess. The conductive via may include any number of conductive layers. For example, the conductive via may include a conductive liner formed first on the sacrificial layer and a conductive fill formed on the conductive liner. In some examples, the conductive liner includes titanium nitride or tantalum nitride. The conductive fill may include any suitable conductive material, such as tungsten, ruthenium, molybdenum, or cobalt. The formation of the conductive via by depositing conductive materials within the remaining volume of the trench recess after forming the sacrificial layer also self-aligns the conductive via within the center of the trench recess (as the sacrificial layer has substantially the same thickness on both sidewalls owing to its conformal deposition process). This self-alignment is helpful to avoid shorting between the conductive via and the adjacent gate electrode.
Method 1900 continues with operation 1916 where the substrate is removed from the backside to expose at least a bottom surface of the conductive via. The substrate may be removed via any arrangement of grinding, polishing, and/or chemical etching processes. According to some embodiments, all materials are removed from the backside up until at least a bottom surface of the dielectric layer beneath the gate structure is exposed or until a bottom surface of the conductive via is exposed. According to some embodiments, the subfin portions may exposed from the backside and replaced with additional dielectric materials.
Method 1900 continues with operation 1918 where the sacrificial layer is removed from the backside (e.g., from exposing the backside of the structure to one or more etchants). Any suitable isotropic etching process may be used to selectively remove the sacrificial layer. Removing the sacrificial layer from around the conductive via leaves behind airgaps between the sidewalls of the conductive via and adjacent structures, according to some embodiments. The airgaps may extend along the entire height of the conductive via. For example, the airgaps are between the conductive via and the gate electrode and between the conductive via and the dielectric layer beneath the gate structure along the gate trench. The first airgaps may also be between the conductive via and the adjacent source or drain region and its contact along the source/drain trench.
Depending on its applications, computing system 2000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 2002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 2000 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment (e.g., a module including an integrated circuit on a substrate, the substrate having semiconductor devices that include through-gate structures with airgap spacers). In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 2006 can be part of or otherwise integrated into the processor 2004).
The communication chip 2006 enables wireless communications for the transfer of data to and from the computing system 2000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 2006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 2000 may include a plurality of communication chips 2006. For instance, a first communication chip 2006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 2006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 2004 of the computing system 2000 includes an integrated circuit die packaged within the processor 2004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more semiconductor devices as variously described herein. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 2006 also may include an integrated circuit die packaged within the communication chip 2006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 2004 (e.g., where functionality of any chips 2006 is integrated into processor 2004, rather than having separate communication chips). Further note that processor 2004 may be a chip set having such wireless capability. In short, any number of processor 2004 and/or communication chips 2006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.
In various implementations, the computing system 2000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
It will be appreciated that in some embodiments, the various components of the computing system 2000 may be combined or integrated in a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components or any suitable combination of hardware, firmware or software.
The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.
Example 1 is an integrated circuit that includes a semiconductor device having a semiconductor region extending in a first direction from a source or drain region and a gate structure extending in a second direction over the semiconductor region, a dielectric layer beneath the gate structure, and a structure spaced from the semiconductor region in the second direction and extending in a third direction along an entire thickness of the gate structure and along an entire thickness of the dielectric layer. An airgap exists between the structure and the gate structure and between the structure and the dielectric layer.
Example 2 includes the integrated circuit of Example 1, wherein the structure comprises a dielectric material.
Example 3 includes the integrated circuit of Example 2, wherein the dielectric material comprises a low-k dielectric material.
Example 4 includes the integrated circuit of any one of Examples 1-3, wherein the structure comprises a conductive material.
Example 5 includes the integrated circuit of Example 4, wherein the conductive material comprises a conductive liner and a conductive fill on the conductive liner.
Example 6 includes the integrated circuit of Example 5, wherein the conductive liner comprises titanium and nitrogen.
Example 7 includes the integrated circuit of Example 5 or 6, wherein the conductive fill comprises tungsten, cobalt, ruthenium, or molybdenum.
Example 8 includes the integrated circuit of any one of Examples 1-7, wherein the airgap has a thickness of less than 10 nm.
Example 9 includes the integrated circuit of any one of Examples 1-8, wherein the semiconductor device is a first semiconductor device, the semiconductor region is a first semiconductor region, the source or drain region is a first source or drain region, the gate structure is a first gate structure, and the airgap is a first airgap. The integrated circuit further comprises a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region. The structure is spaced from the second semiconductor region in the second direction such that the structure is between the first semiconductor region and the second semiconductor region along the second direction. A second airgap exists between the structure and the second gate structure.
Example 10 includes the integrated circuit of Example 9, wherein the first airgap and the second airgap have substantially the same thickness.
Example 11 includes the integrated circuit of any one of Examples 1-10, wherein the dielectric layer is a first dielectric layer, the integrated circuit further comprising a second dielectric layer over the gate structure, such that a top surface of the structure contacts a bottom surface of the second dielectric layer.
Example 12 includes the integrated circuit of Example 11, wherein the second dielectric layer extends over the airgap.
Example 13 includes the integrated circuit of any one of Examples 1-12, wherein the structure extends in the first direction adjacent to the source or drain region.
Example 14 includes the integrated circuit of Example 13, wherein the airgap also extends in the first direction such that the airgap is between the structure and the source or drain region.
Example 15 is a printed circuit board comprising the integrated circuit of any one of Examples 1-14.
Example 16 is an electronic device that includes a chip package having one or more dies. At least one of the one or more dies includes a semiconductor region extending in a first direction from a first source or drain region to a second source or drain region, a gate structure extending in a second direction over the semiconductor region, a dielectric layer beneath the gate structure, and a structure spaced from the semiconductor region in the second direction and extending in a third direction along an entire thickness of the gate structure and along an entire thickness of the dielectric layer. An airgap exists between the structure and the gate structure and between the structure and the dielectric layer.
Example 17 includes the electronic device of Example 16, wherein the structure comprises a dielectric material.
Example 18 includes the electronic device of Example 17, wherein the dielectric material comprises a low-k dielectric material.
Example 19 includes the electronic device of any one of Examples 16-18, wherein the structure comprises a conductive material.
Example 20 includes the electronic device of Example 19, wherein the conductive material comprises a conductive liner and a conductive fill on the conductive liner.
Example 21 includes the electronic device of Example 20, wherein the conductive liner comprises titanium and nitrogen.
Example 22 includes the electronic device of Example 20 or 21, wherein the conductive fill comprises tungsten, cobalt, ruthenium, or molybdenum.
Example 23 includes the electronic device of any one of Examples 16-22, wherein the airgap has a thickness of less than 10 nm.
Example 24 includes the electronic device of any one of Examples 16-23, wherein the semiconductor region is a first semiconductor region, the source or drain region is a first source or drain region, the gate structure is a first gate structure, and the airgap is a first airgap. The at least one of the one or more dies further comprises a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region. The structure is spaced from the second semiconductor region in the second direction such that the structure is between the first semiconductor region and the second semiconductor region along the second direction. A second airgap exists between the structure and the second gate structure.
Example 25 includes the electronic device of Example 24, wherein the first airgap and the second airgap have substantially the same thickness.
Example 26 includes the electronic device of any one of Examples 16-25, wherein the dielectric layer is a first dielectric layer, the at least one of the one or more dies further comprising a second dielectric layer over the gate structure, such that a top surface of the structure contacts a bottom surface of the second dielectric layer.
Example 27 includes the electronic device of Example 26, wherein the second dielectric layer extends over the airgap.
Example 28 includes the electronic device of any one of Examples 16-27, wherein the structure extends in the first direction adjacent to the source or drain region.
Example 29 includes the electronic device of Example 28, wherein the airgap also extends in the first direction such that the airgap is between the structure and the source or drain region.
Example 30 includes the electronic device of any one of Examples 16-29, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.
Example 31 is a method of forming an integrated circuit. The method includes forming a fin comprising semiconductor material, the fin extending above a substrate and extending in a first direction; forming a dielectric layer adjacent to a subfin portion of the fin; forming source or drain regions at opposite ends of the fin; forming a gate structure on the dielectric layer and over the semiconductor material and extending in a second direction; forming a recess through an entire thickness of the gate structure and through an entire thickness of the dielectric layer; forming a sacrificial layer along sidewalls and a bottom surface of the recess; forming a conductive material on the sacrificial layer within the recess; removing the substrate from the backside of the integrated circuit, wherein the removing exposes a bottom surface of the conductive material; and removing the sacrificial layer from the backside to form an airgap between the conductive material and the gate structure and between the conductive material and the dielectric layer.
Example 32 includes the method of Example 31, wherein the sacrificial layer comprises aluminum and oxygen.
Example 33 includes the method of Example 31 or 32, wherein removing the sacrificial layer comprises applying an ammonia gas to etch the sacrificial layer.
Example 34 includes the method of any one of Examples 31-33, wherein forming the conductive material comprises forming a conductive liner and forming a conductive fill on the conductive liner.
Example 35 includes the method of any one of Examples 31-34, further comprising removing a bottom portion of the sacrificial layer prior to forming the conductive material.
Example 36 includes the method of any one of Examples 31-35, wherein the dielectric layer is a first dielectric layer, the method further comprising forming a second dielectric layer on a top surface of the conductive material prior to removing the sacrificial layer.
Example 37 is an integrated circuit that includes a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region, a first dielectric layer beneath the gate structure, a conductive structure spaced from the semiconductor region in the second direction and extending in a third direction along an entire thickness of the gate structure and along an entire thickness of the dielectric layer, and a second dielectric layer over the gate structure and on a top surface of the conductive structure. An airgap exists between the conductive structure and the gate structure and between the conductive structure and the dielectric layer.
Example 38 includes the integrated circuit of Example 37, wherein the conductive structure comprises a conductive liner and a conductive fill on the conductive liner.
Example 39 includes the integrated circuit of Example 38, wherein the conductive liner comprises titanium and nitrogen.
Example 40 includes the integrated circuit of Example 38 or 39, wherein the conductive fill comprises tungsten, cobalt, ruthenium, or molybdenum.
Example 41 includes the integrated circuit of any one of Examples 37-40, wherein the airgap has a thickness of less than 10 nm.
Example 42 includes the integrated circuit of any one of Examples 37-41, wherein the semiconductor device is a first semiconductor device, the semiconductor region is a first semiconductor region, the source or drain region is a first source or drain region, the gate structure is a first gate structure, and the airgap is a first airgap. The integrated circuit further comprises a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region. The conductive structure is spaced from the second semiconductor region in the second direction such that the conductive structure is between the first semiconductor region and the second semiconductor region along the second direction. A second airgap exists between the conductive structure and the second gate structure.
Example 43 includes the integrated circuit of Example 42, wherein the first airgap and the second airgap have substantially the same thickness.
Example 44 includes the integrated circuit of any one of Examples 37-43, wherein the second dielectric layer extends over the airgap.
Example 45 includes the integrated circuit of any one of Examples 37-44, wherein the conductive structure extends in the first direction adjacent to the source or drain region.
Example 46 includes the integrated circuit of Example 45, wherein the airgap also extends in the first direction such that the airgap is between the conductive structure and the source or drain region.
Example 47 is a printed circuit board comprising the integrated circuit of any one of Examples 37-46.
Example 48 includes the subject matter of any one of Examples 1 through 47, wherein the semiconductor region (or first and second semiconductor regions) comprises one or more semiconductor nanoribbons, nanowires, or nanosheets. In another such example, the semiconductor region(s) comprises a semiconductor fin. In another such example, a first semiconductor region comprises one or more semiconductor nanoribbons, nanowires, or nanosheets, and a second semiconductor region comprises a fin.
The foregoing description of the embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto.
