Claims
- 1. A pulse converting circuit for converting an inputted pulse signal to a divided-frequency pulse signal having either of rising and falling edges in accordance with both the rising and falling edges of said inputted pulse signal, comprising:a signal generating circuit for generating a clock signal; a counter for counting the clock signal outputted from said signal generating circuit; and a synchronous circuit for receiving said inputted pulse signal, causing an output signal to shift from one of logic levels to the other logic level and initializing the count value of said counter with the rising and falling timings of said inputted pulse signal, and causing said output signal to shift from said other logic level to said one of logic levels when the count value of said counter reaches a predetermined value, the output signal of said synchronous circuit being outputted as said divided-frequency pulse signal.
- 2. The pulse converting circuit according to claim 1, wherein said signal generating circuit has the function of setting and changing the period of the generated clock signal.
- 3. The pulse converting circuit according to claim 1, having the function of setting and changing the predetermined count value of said counter obtained when said synchronous circuit causes the output signal to shift from the other logic level to said one of logic levels.
- 4. An FM demodulating circuit for obtaining the frequency of an FM signal whose frequency is modulated, comprising:an input signal converting circuit for converting an inputted FM signal to an FM pulse signal which is set to one of logic levels when the potential of the FM signal is higher than a reference potential, and is set to the other logic level when the potential of the FM signal is lower than said reference potential; an FM frequency divider for converting the FM pulse signal inputted from said input signal converting circuit to an FM divided-frequency pulse signal having either of rising and falling edges in accordance with both the rising and falling edges of the FM pulse signal; and a measuring circuit for measuring the time between said either of edges of the FM divided-frequency pulse signal outputted from said FM frequency divider, wherein the time obtained by said measuring circuit is the time taken from the rising edge to the falling edge of said FM pulse signal or the time taken from the falling edge to the rising edge thereof, and the inverse number of the time is obtained to find the frequency of said FM signal.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-293894 |
Nov 1995 |
JP |
|
Parent Case Info
This is a divisional of application Ser. No. 08/747,180, filed Nov. 12, 1996 now U.S. Pat. No. 5,982,841.
US Referenced Citations (12)
Foreign Referenced Citations (3)
Number |
Date |
Country |
44 00 825 |
Jul 1994 |
DE |
0 735 374 |
Oct 1996 |
EP |
58-169222 |
Oct 1983 |
JP |
Non-Patent Literature Citations (1)
Entry |
T. Wtanabe et al., “A Time-to-Digital Converter LSI”, Technical Report of IEICE, pp. 37-43. |