Claims
- 1. Time-division multiplex communication system comprising:
- a transmitting device which regularly encodes an n-bit word in a linear block code into a bit sequence to be transmitted, and a checking device at a receiving end which looks for the n-bit word in the received bit sequence by checking groups of n successive bits as to whether they are coded in the block code,
- wherein the checking device (SR1, SR2, N.sub.1 to N.sub.n-k, LS) checks all n-bit groups (X.sub.j to X.sub.j-n-1) which begin with any one (X.sub.j) of the n successive bits of the received bit sequence by successively checking in parallel n-bit groups and by independently checking each n-bit group.
- 2. A system as claimed in claim 1, wherein the checking device (SR1, SR2, N.sub.1 to N.sub.n-k, LS) calculates a syndrome (S.sub.1 to S.sub.n-k) for each of the n-bit groups (X.sub.j to X.sub.j-n-1) on the basis of a parity check matrix of the linear block code used and, if the syndrome (S.sub.1 to S.sub.n-k) is zero, provides a signal indicating the presence of one of the n-bit words.
- 3. Time-division multiplex communication system comprising:
- a transmitting device which regularly encodes an n-bit word in a linear block code into a bit sequence to be transmitted, and a checking device (SR1, SR2, N.sub.1 to N.sub.n-k, LS) at a receiving end which looks for the n-bit word in the received bit sequence by checking groups of n successive bits as to whether they are coded in the block code,
- wherein the checking device (SR1, SR2, N.sub.1 to N.sub.n-k, LS) successively checks all n-bit groups (X.sub.j to X.sub.j+n-1) which begin with any one (X.sub.j) of the n successive bits of the received bit sequence,
- wherein the checking device (SR1, SR2, N.sub.1 to N.sub.n-k, LS) calculates a syndrome (S.sub.1 to S.sub.n-k) is zero, provides a signal indicating the presence of one of the n-bit words, and
- wherein the checking device (SR1, SR2, N.sub.1 to N.sub.n-k, LS) contains
- a network (N.sub.i) for each component (S.sub.i) of the syndrome (S.sub.1 to S.sub.n-k) which calculates one component (S.sub.i) of the syndrome (S.sub.1 to S.sub.n-k) from the n-bit bit group (X.sub.j to X.sub.j+n-1) to be checked,
- a logic (LS) which determines from the calculated components of the syndrome (S.sub.1 to S.sub.n-k) whether the syndrome (S.sub.1 S.sub.n-k) is zero, and
- a delay circuit (SR2) which delays the received bit sequence until the check of an n-bit group is completed.
- 4. A system as claimed in claim 3, wherein the checking device (SR1, SR2, N.sub.1 to N.sub.n-k, LS) processes the received bit sequence at the bit rate (C).
- 5. A system as claimed in claim 4, wherein in the checking device (SR1, SR2, N.sub.1 N.sub.n-k, LS), each bit of an n-bit bit group (X.sub.j to X.sub.j+n-1) to be checked is fed into each of the networks (N.sub.i) in parallel, and that each of the networks (N.sub.i) calculates its component (S.sub.i) of the syndrome (S.sub.1 to S.sub.n-1) in several successive stages by exclusive-ORing its input bits in accordance with the parity check matrix.
- 6. A system as claimed in claim 5, wherein the received bit sequence passes through an (N-1)-bit shift register (SR1) which provides an n-bit bit group (X.sub.j to X.sub.j+n-1) to the networks (N.sub.1 to N.sub.n-k) on each pulse of the bit rate (C).
- 7. A system as claimed in claim 6, wherein each network (N.sub.i) is fed only with those bits of the n-bit bit group (X.sub.j to X.sub.j+n-1) for which the associated parity check matrix components to be used in the network (N.sub.i) are nonzero.
- 8. A system as claimed in claim 7, wherein those networks (N.sub.i) whose number (M.sub.i) of stages (ST.sub.1 to ST.sub.4 is less than the maximum number of stages required in any of the networks have additional stages including delay elements (E.sub.2), so that all networks (N.sub.1 to N.sub.n-k) provide their components (S.sub.i) of the syndrome (S.sub.1 to S.sub.n-k) at their outputs simultaneously.
- 9. A method in a time-division multiplex communication system having a transmitting device which regularly encodes an n-bit word in a linear block code into a bit sequence to be transmitted, and a checking device at a receiving end, for checking for an n-bit word coded in a linear block code in a received bit sequence by checking groups of n successive bits, comprising the step of:
- checking all n-bit groups (X.sub.j to X.sub.j+n-1) which begin with any one (X.sub.j) of the successive bits in the bit sequence, by successively checking in parallel n-bit groups and by independently checking each n-bit group.
- 10. The method of claim 9, wherein the successively checking step comprises the steps of:
- calculating a syndrome (S.sub.1 to S.sub.n-k) for each of the n-bit bit groups on the basis of a parity check matrix of the linear block code; and
- if the syndrome is zero, providing a signal indicating the presence of one of the n-bit words.
- 11. A method for checking for an n-bit word coded in a linear block code in a bit sequence by checking groups of n successive bits, comprising the step of:
- storing a selected number of bits of the bit sequence;
- calculating each component of the syndrome (S.sub.1 to S.sub.n-k) from an n-bit group to be checked;
- determining a magnitude from the calculated components of the syndrome;
- successively and independently checking all n-bit groups (X.sub.j to X.sub.j+n-1) which begin with any one (X.sub.j) of the successive bits in the bit sequence; and
- delaying the received bit sequence until the check of an n-bit group (X.sub.j to X.sub.j+n-1) is completed.
- 12. A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted, comprising:
- storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits; and
- checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by checking all n-bit groups (X.sub.j to X.sub.j+n-1) which begin with any one (X.sub.j) of the successive bits, by successively checking in parallel n-bit groups and by independently checking each n-bit group.
- 13. The checking device of claim 12, wherein the checking means calculates a syndrome (S.sub.1 to S.sub.n-k) for each of the n-bit groups on the basis of a parity check matrix of the linear block code used and, if the syndrome is zero, provides a signal indicative of the presence of one of the n-bit words.
- 14. A system as claimed in claim 12, wherein processing within the checking means takes place at a bit rate (C) of the received bit sequence.
- 15. The checking device of claim 12, wherein in the checking means, an n-bit group (X.sub.j to X.sub.j+n-1) to be checked is fed into each of a plurality of networks (N.sub.i) in parallel, and that each of the networks calculates its component (S.sub.i) of the syndrome (S.sub.1 to S.sub.n-k) in several successive stages by exclusive-ORing its input bits in accordance with a parity check matrix.
- 16. A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted comprising:
- storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits;
- checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by successively checking all n-bit groups (X.sub.j to X.sub.j+n-1) which begin with any one (X.sub.j) of the successive bits;
- a network (N.sub.i) for each component (S.sub.i) of the syndrome (S.sub.1 to S.sub.n-k) which calculates one component (S.sub.i) of the syndrome (S.sub.1 to S.sub.n-k) from the n-bit group (X.sub.j to X.sub.j+n-1) to be checked;
- a logic means (LS) which determines from the calculated components of the syndrome (S.sub.1 to S.sub.n-l) whether the syndrome is zero; and
- a delay circuit (SR2) which delays the received bit sequence until the check of an n-bit bit group is completed.
- 17. A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted, comprising:
- storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits; and
- checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by successively checking all n-bit groups (X.sub.j to X.sub.j+n-1) which begin with any one (X.sub.j) of the successive bits;
- wherein the received bit sequence passes through the storage means comprising an (n-1)-bit shift register (SR1), which provides an n-bit bit group (X.sub.j to X.sub.j+n-1) to a plurality of networks (N.sub.1 to N.sub.n-k) on each pulse of a bit clock (C);
- wherein each network (N.sub.i) is fed only with those bits of the n-bit group (X.sub.j to X.sub.j+n-1) for which the associated parity check matrix components to be used in the network (N.sub.i) are non-zero;
- wherein the networks (N.sub.i) whose number (M.sub.i) of stages ST.sub.4 to ST.sub.1) is less than a maximum number of stages required in any of the networks of additional stages, including delay elements (E.sub.2), so that all networks (N.sub.1 to N.sub.n-k) provide their components (S.sub.i) of the syndrome (S.sub.1 ) to S.sub.n-k) at their outputs simultaneously.
Priority Claims (1)
Number |
Date |
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3922486 |
Jul 1989 |
DEX |
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Parent Case Info
This is a continuation of copending application Ser. No. 07/547,494 filed on Jul. 2, 1990, now abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0269974 |
Jun 1988 |
EPX |
Continuations (1)
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Number |
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Parent |
547494 |
Jul 1990 |
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