TIME-DOMAIN INCREMENTAL TWO-STEP CAPACITANCE-TO-DIGITAL CONVERTER

Abstract

An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.

Description

FIELD OF THE INVENTION

Embodiments described herein relate generally to capacitance sensing, in particular, a capacitance-to-digital converter circuit and methodologies.

BACKGROUND

A capacitance-to-digital converter can be used to convert some sensed physical quantities as a measure to capacitance to a digital output which can be processed by a back-end CPU. Energy efficiency is vital due to the limited energy storage (e.g., batteries) of many applications. For example, with the booming of Internet of Things application, it is expected that billions of devices will be deployed in our surroundings. Many of the applications may employ environmental sensing such as temperature, humidity, placement, audio sensors, e.g., microphone, touchscreen.

SAR CDC is a design that is well suited for low-to-medium resolution applications. To reach high resolution, SAR CDC often employ a low-noise comparator or an OTA-based active charge transfer, either of which can result in degraded power efficiency. ΔΣ CDC may be suitable for high-resolution applications, but it may employ OTAs and the repeated charging of the sensing capacitor, which can also lead to high power consumption. Zoom CDC can achieve high resolution with only one-time charging, but its energy efficiency is generally limited by power-hungry OTAs. Open-loop SAR-VCO CDC achieves low power consumption by eliminating the OTA, however, the VCO gain variation often cause inter-stage gain error and requires background calibration, which increases the design complexity and makes it unsuitable for single-shot measurement in sensor node applications due to the long convergence time.

There is a benefit to having improved CDC designs that further improve energy efficiency and reduce design complexity.

SUMMARY

This present disclosure provides an exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM). The TDΔΣM includes (rather than an operational transconductance amplifier (OTA)-based active-RC integrator, e.g., typically used in conventional CDC) a voltage-controlled oscillator (VCO)-based integrator, which can be configured for mostly digital operation and low-power while providing capabilities for infinite DC gain and intrinsic quantization in phase domain. The exemplary TDΔΣM can provide 76-dB SNDR using a low-order loop and a low oversampling ratio (OSR). Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion, which improves the energy efficiency by over two times as compared to the conventional CDC and known approaches.

In an aspect, a capacitance-to-digital converter (CDC) is disclosed comprising a first stage successive approximation register capacitance-to-digital converter (1^st stage SAR CDC) circuit portion configured to perform a plurality of successive approximations of an input sensed capacitance signal to generate a SAR conversion residue and a first set of converted outputs; and a second stage time-domain incremental delta-sigma modulator capacitance-to-digital converter (2^nd stage TD incremental ΔΣM CDC) circuit portion that quantizes the SAR conversion residue, using, in part, a voltage-controlled oscillator (VCO) based integrator of the 2^nd stage TD incremental ΔΣM CDC operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs, wherein the 2^nd stage TD incremental ΔΣM CDC generates a second set of converted outputs as a representation of the input sensed capacitance signal (e.g., wherein the capacitor ratio is precisely matched so that VCO gain variation cannot change the feedback factor).

In some embodiments, the 2^nd stage TD incremental ΔΣM CDC circuit portion comprises a N-stage ring voltage-controlled oscillator (VCO) circuit; and a phase and frequency detector (PFD) coupled to the N-stage ring voltage-controlled oscillator (VCO) circuit to an output for the closed-loop control.

In some embodiments, the 2^nd stage TD incremental ΔΣM CDC circuit portion further comprises a passive charge sharing (CS) circuit coupled to the N-stage ring voltage-controlled oscillator (VCO) circuit.

In some embodiments, the N-stage ring voltage-controlled oscillator (VCO) circuit is implemented as a G_m-stage-driven current-controlled oscillator (CCO).

In some embodiments, the G_m-stage-driven CCO is configured to convert the SAR conversion residue into a frequency variation at the output N-stage ring VCO and generate output a phase-difference signal.

In some embodiments, the PFD is configured to detect and integrate the phase difference signal to generate an integrated phase difference signal.

In some embodiments, the PFD comprises a multi-phase quantizer configured to transform the integrated phase difference signal to a multi-level output, the PFD further comprising a sampling circuit to sample the multi-level output.

In some embodiments, the close-loop control comprises a first-order loop.

In some embodiments, the 2^nd stage TD incremental ΔΣM CDC is configured to operate in an incremental mode.

In some embodiments, the 2^nd stage TD incremental ΔΣM CDC is configured to disable operation during SAR operation of the 1^st stage SAR CDC.

In some embodiments, the capacitance-to-digital converter (CDC) further includes a capacitance sensing network circuit coupled to the 1^st stage SAR CDC circuit portion, the capacitance sensing network circuit being configured to switch between a first capacitance sensing input associated with a first capacitive plate and a second capacitance sensing input associated with a second capacitive plate.

In some embodiments, the capacitance sensing network circuit comprises a chopper circuit, the chopper be configured to perform the switching between the first capacitance sensing input and the second capacitance sensing input.

In some embodiments, the 2^nd stage TD incremental ΔΣM CDC is configured to disable operations during sensing operation of the capacitance sensing network circuit.

In some embodiments, the 2^nd stage TD incremental ΔΣM CDC is configured as an N-bit incremental ΔΣM CDC selected from the group consisting of: a 2-bit incremental ΔΣM CDC, a 3-bit incremental ΔΣM CDC, a 4-bit incremental ΔΣM CDC, a 5-bit incremental ΔΣM CDC, a 6-bit incremental ΔΣM CDC, a 7-bit incremental ΔΣM CDC, an 8-bit incremental ΔΣM CDC, a 9-bit incremental ΔΣM CDC, and a 10-bit incremental ΔΣM CDC.

In another aspect, a microcontroller is disclosed comprising one of more of any one of the above-discussed capacitance-to-digital converter.

In another aspect, an integrated chip is disclosed comprising one of more of any one of the above-discussed capacitance-to-digital converter.

In another aspect, a method is disclosed of converting a sensed capacitance signal, associated with a capacitance source, to an output digital signal representing the sensed capacitance analog signal, the method comprising successively approximating over a first set of plurality of approximations (e.g., coarse approximation), the sensed capacitance signal to generate i) a residue signal and ii) first set of converted outputs of the digital signal; generating a first digital-to-analog converted signal of the first set of converted outputs of the digital signal; finely approximating (e.g., via time-domain sigma delta modulation), over a second set of plurality of approximations (e.g., fine approximation), an updated residue signal to determine a second set of converted outputs of the digital signal, wherein the updated residual signal include the generated residue signal and closed-loop feedback control signals generated based on the first set of plurality of approximations and the second set of plurality of approximations; and generating a second digital-to-analog converted signal of the second set of converted outputs of the digital signal representing the sensed capacitance signal; and combining the first digital-to-analog converted signal and second digital-to-analog converted signal to generate the updated residue signal.

In some embodiments, the finely approximating operation comprises quantizing the residue signal, using, in part, a voltage-controlled oscillator (VCO) based integrator operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs by converting the residue signal into a frequency variation to generate an output a phase difference signal; integrating the phase difference signal to generate an integrated phase difference signal; and transforming the integrated phase difference signal to a multi-level output for the closed-loop control.

In some embodiments, the method further includes converting a second sensed capacitance signal corresponding to another portion of the capacitance source; and averaging output of the first conversion of the sensed capacitance signal and output of the second conversion of the second sensed capacitance signal in the digital domain.

In some embodiments, the second set of plurality of approximations are performed via a time-domain sigma-delta modulator (TD ΔΣM).

In some embodiments, the conversion of the sensed capacitance signal is performed using less than 0.083 nJ per conversion.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments of the present invention may be better understood from the following detailed description when read in conjunction with the accompanying drawings. Such embodiments, which are for illustrative purposes only, depict novel and non-obvious aspects of the invention. The drawings include the following figures:

FIG. 1 shows an exemplary two-stage successive-approximation register and time-domain delta-sigma modulator capacitance-to-digital converter in accordance with an illustrative embodiment.

FIG. 2A shows a system-level chopping operation for the exemplary two-stage SAR/TDΔΣM CDC of FIG. 1 in accordance with an illustrative embodiment.

FIG. 2B shows a chopper embedded capacitance sensing network to operate system-level chopping operation with the exemplary SAR/TDΔΣM CDC of FIG. 1 in accordance with an illustrative embodiment.

FIG. 2C shows the exemplary two-stage SAR/TDΔΣM CDC of FIG. 1 configured with a chopper embedded capacitance sensing network in accordance with an illustrative embodiment.

FIG. 3 shows a method to operate the exemplary two-stage SAR/TDΔΣM CDC of FIG. 1 in accordance with an illustrative embodiment.

FIG. 4 depicts a block diagram of the 2nd stage TDΔΣM CDC circuit in accordance with an illustrative embodiment.

FIG. 5 shows a schematic of the exemplary SAR/TDΔΣM CDC of FIG. 1 in accordance with an illustrative embodiment.

FIG. 6 shows a block diagram of an example TDΔΣM circuit that can be used in the 2^nd stage TDΔΣM circuit in accordance with an illustrative embodiment.

FIG. 7 shows a diagram of a ring voltage-controlled oscillator cell that can be used in the exemplary SAR/TDΔΣM CDC of FIG. 1 in accordance with an illustrative embodiment.

FIG. 8 shows a diagram of a phase-frequency detector-based sampler that can be used in the exemplary SAR/TDΔΣM CDC of FIG. 1 in accordance with an illustrative embodiment.

FIG. 9A shows a photo of a fabricated die of a SAR/TDΔΣM CDC implemented in a 40-nm CMOS process in accordance with an illustrative embodiment.

FIG. 9B shows the fabricated die of a SAR/TDΔΣM CDC of FIG. 9A with the relevant portion of the circuit expanded.

FIG. 10 shows measured DC capacitance performance of the fabricated SAR/TDΔΣM CDC of FIG. 9 in accordance with an illustrative embodiment.

FIG. 11 shows the static performance of the fabricated SAR/TDΔΣM CDC of FIG. 9 measured in a linearity test mode in accordance with an illustrative embodiment.

FIG. 12 shows measured SNDR and SFDR performance across operating frequency for the fabricated SAR/TDΔΣM CDC of FIG. 9 in accordance with an illustrative embodiment.

FIG. 13 shows measured SNDR and SFDR across an amplitude sweep for the fabricated SAR/TDΔΣM CDC of FIG. 9 in accordance with an illustrative embodiment.

FIG. 14 shows a comparison of CDC Figure of Merit (FoM) versus ENOB of the exemplary SAR/TDΔΣM CDC architecture with different CDC architectures in accordance with an illustrative embodiment.

FIG. 15 shows an example of redundancy allocation between 1^st stage SAR and 2^nd stage TDΔΣM CDC in accordance with an illustrative embodiment.

FIG. 16 shows simulation results for a 1000-run Monte Carlo simulation of the exemplary SAR/TDΔΣM CDC with capacitor mismatch in accordance with an illustrative embodiment.

FIG. 17A shows a plot showing comparative performance between an open-loop design and the closed-loop design of the exemplary SAR/TDΔΣM CDC regarding the VCO gain variation in accordance with an illustrative embodiment.

FIG. 17B shows block diagrams of the open-loop design and the closed-loop design of the exemplary SAR/TDΔΣM CDC used in the study of FIG. 17A in accordance with an illustrative embodiment.

DETAILED SPECIFICATION

Each and every feature described herein, and each and every combination of two or more of such features, is included within the scope of the present invention provided that the features included in such a combination are not mutually inconsistent.

In some aspects, the disclosed technology relates to capacitance-to-digital converter circuits and operations. Although example embodiments of the disclosed technology are explained in detail herein, it is to be understood that other embodiments are contemplated. Accordingly, it is not intended that the disclosed technology be limited in its scope to the details of construction and arrangement of components set forth in the following description or illustrated in the drawings. The disclosed technology is capable of other embodiments and of being practiced or carried out in various ways.

It must also be noted that, as used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Ranges may be expressed herein as from “about” or “approximately” one particular value and/or to “about” or “approximately” another particular value. When such a range is expressed, other exemplary embodiments include from the one particular value and/or to the other particular value.

By “comprising” or “containing” or “including” is meant that at least the named compound, element, particle, or method step is present in the composition or article or method, but does not exclude the presence of other compounds, materials, particles, method steps, even if the other such compounds, material, particles, method steps have the same function as what is named.

In describing example embodiments, terminology will be resorted to for the sake of clarity. It is intended that each term contemplates its broadest meaning as understood by those skilled in the art and includes all technical equivalents that operate in a similar manner to accomplish a similar purpose. It is also to be understood that the mention of one or more steps of a method does not preclude the presence of additional method steps or intervening method steps between those steps expressly identified. Steps of a method may be performed in a different order than those described herein without departing from the scope of the disclosed technology. Similarly, it is also to be understood that the mention of one or more components in a device or system does not preclude the presence of additional components or intervening components between those components expressly identified.

Some references, which may include various patents, patent applications, and publications, are cited in a reference list and discussed in the disclosure provided herein. The citation and/or discussion of such references is provided merely to clarify the description of the disclosed technology and is not an admission that any such reference is “prior art” to any aspects of the disclosed technology described herein. In terms of notation, “[n]” corresponds to the nth reference in the list. For example, [1] refers to the first reference in the list, namely [1] S. Park, G.-H. Lee, and S. Cho, “A 2.92-μW Capacitance-to-Digital Converter with Differential Bond-wire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, 2019. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference.

In the following description, references are made to the accompanying drawings that form a part hereof and that show, by way of illustration, specific embodiments or examples. In referring to the drawings, like numerals represent like elements throughout the several figures.

Example System

FIG. 1 shows an exemplary two-stage successive-approximation register and time-domain delta-sigma modulator capacitance-to-digital converter in accordance with an illustrative embodiment. Specifically, FIG. 1 shows an exemplary two-stage capacitance-to-digital converter (CDC) 100 (also referred to herein as “SAR/TDΔΣM CDC” 100) configured with a first stage successive approximation register capacitance-to-digital converter (1^st stage SAR CDC) circuit portion 102 configured for coarse conversions (shown during, and referenced as, “Φ₁” 104) and a second stage time-domain delta-sigma modulator capacitance-to-digital converter (2^nd stage TDΔΣM CDC also referred to herein as TDΔΣM CDC) circuit portion 106 configured for fine conversions (shown during, as referenced as, “Φ₂” 108) of sense capacitance (shown during, and referenced as, “Sense Φ₀” 110) sensed via a sensing circuit portion 112.

As shown in FIG. 1, the 1^st stage SAR CDC circuit portion 102 includes a successive approximation register (SAR) circuit 114 (as an “8b (8-bit) SAR” 114) configured to perform a plurality of successive approximations of an input sensed capacitance signal comprising a measured or converted voltage 116 (shown as voltage signal “V_x” 116′) acquired from capacitance device or element 118 (shown as “C_x” and “C_os” 118). In other embodiments, the sensed capacitance signal may be operated upon as a converted current signal or other signal representation (e.g., frequency, etc.).

The 2^nd stage TDΔΣM CDC circuit portion 106 includes a digital-to-analog converter 120 (shown as “DAC” 120) that uses the first set of converted outputs 122 and feedback signals 124 from the 2^nd stage TDΔΣM CDC circuit portion 106 to generate a SAR conversion residue (shown as signal 126) when combined, via a combiner circuit 128, with the input sensed capacitance signal (e.g., via voltage signal 116′) associated with capacitance “C_x” and “C_os.”

The 2^nd stage TDΔΣM CDC circuit portion 106 includes a TDΔΣM 134 (shown as “TD Operation” 134) configured to quantize the SAR conversion residue 126. The TDΔΣM 134 includes, in some embodiments, a voltage-controlled oscillator (VCO) based integrator 130 (shown as part of “H_L(S)” 130′) operating in a closed-loop control (shown as 124′) with the DAC 120 to generate a second set of converted outputs 132. The VCO integrator 130 can provide intrinsic clocked averaging (ICLA) capability (shown as 130″) that can address the ΔΣM feedback DAC mismatches. In addition, the 2^nd stage TDΔΣM CDC circuit portion 106 may implement a low-order loop (e.g., 1^st order loop). The closed-loop gain (e.g., set by the capacitor ratio) can be precisely matched by merging the ΔΣ feedback DAC (associated with 114) with the SAR DAC (associated with 110).

Indeed, FIG. 1 depicts a conceptual block and timing diagram of the exemplary SAR/TDΔΣM CDC 100. The exemplary SAR/TDΔΣM CDC 100, as shown in FIG. 1, includes an 8-bit SAR (e.g., 114) and a 4-bit TDΔΣM (e.g., 134) for respective coarse and fine CDC conversions. During sensing operation Φ₀ 110, the sensor capacitor C_X 118 is sampled by the sensing circuit portion 112 (e.g., a DAC array) and is first quantized by the coarse 8-bit SAR 114 in coarse operation Φ₁ 104. After that, the TDΔΣM 134 performs the fine quantization operation of the SAR conversion residue 126. In the example of FIG. 1, the TDΔΣM (e.g., 134) includes a first-order loop (e.g., shown associated with signal 124′) with a multi-bit quantizer 136 (shown in FIG. 1 as a 4-bit quantizer 136).

Capacitance sensors (e.g., associated with capacitance 118) may include capacitive touch sensors for user input, including, for buttons, scroll wheels, matrix keypad, and sider bars. Capacitance sensors may include single-ended grounded sensors, differential ended grounded sensors, single-ended floating sensors, and differential ended floating sensors. Capacitance sensors may be used in body worn sensors or medical devices, e.g., to detect sweat, respiration rate, blood pressure, liquid level. Capacitance sensors may include temperature sensors, humidity sensors, placement sensors, audio sensors, e.g., microphone sensors, touchscreen sensors, among others.

To further save energy, the TDΔΣM 134 is configured to operate in an incremental mode (shown as “Reset” 138) where the integrator is reset prior to each input signal conversion. The TDΔΣM 134 may be configured to consume only, or mainly, dynamic power. In addition, the TDΔΣM 134 may be configured to be disabled during sensing operation Φ₀ and SAR conversion operation Φ₁.

As shown in FIG. 1, the 2^nd stage TDΔΣM CDC circuit portion 106 includes a decimation filter 140 to provide the second set of converted outputs 132 (shown as the digital output “d₂” 132) by filtering the TDΔΣM output.

Also, as shown in FIG. 1, a simple first-order digital integrator may be adopted to provide sufficient noise suppression:

$H\left(z\right)=\frac{1}{\left(1-z^{-1}\right)}.$

The exemplary SAR/TDΔΣM CDC 100 may be configured with an over-sampling ratio (OSR) of 15 while also providing notches at integer multiples of f_s=15, e.g., to suppress unwanted periodic interferences.

The chopper embedded capacitance operations can be used to improve the SAR/TDΔΣM CDC operation by reducing offset errors as well as flicker noise.

FIG. 2A shows a system-level chopping operation for the exemplary two-stage SAR/TDΔΣM CDC 100 in accordance with an illustrative embodiment. FIG. 2B shows a chopper embedded capacitance sensing network to operate system-level chopping operation with the exemplary SAR/TDΔΣM CDC 100 in accordance with an illustrative embodiment. FIG. 2C shows the exemplary two-stage SAR/TDΔΣM CDC 100 of FIG. 1 configured with a chopper embedded capacitance sensing network in accordance with an illustrative embodiment.

As shown in FIG. 2A, the SAR/TDΔΣM CDC 100 is configured to perform capacitance sensing twice—one across the capacitor sensor in a first direction (e.g., G 118 (shown as 202) and an offset capacitor or capacitance C_os 204) and as second across the same capacitor sensor in a second direction inverse of the first direction (e.g., C_os 204 and C_x 202). Each of the sensed capacitance is converted by the 1^st stage SAR CDC and 2^nd stage TDΔΣM CDC (shown as “CDC” 100a) and the output combined by an average operation to generate the final output (shown as “Do” 206).

During the first chopping phase, V_REFP and V_REFN (shown in FIG. 2B and associated with a sense voltage across a capacitor) are sampled on the, say, bottom plates of C_X and C_OS, respectively. Once Φ₀ finishes, the bottom plate voltages are swapped, resulting in a signal charge proportional to the difference between C_X and C_OS transferred to the merged DAC array.

The exemplary SAR/TDΔΣM CDC 100 can generate a total capacitance C_TOTAL at the comparator input where C_TOTAL≡C_X+C_OS+C_DAC+C_PAR, where C_DAC is the total capacitive DAC including SAR DAC C_SAR and TDΔΣM DAC CALM, and C_PAR (see FIG. 4) is a total parasitic capacitance of the device, e.g., including that of the bond-pad, electrostatic discharge device, and wiring capacitance. The signal charge may result in a voltage V_X at the comparator input that can be converted by the CDC per Equation 1.

$\begin{array}{cc}{V}_x=\frac{\left(C_x-C_{\mathrm{OS}}\right)·\left(V_{\mathrm{REFP}}-V_{\mathrm{REFN}}\right)}{C_{\mathrm{TOTAL}}}& \left(\mathrm{Equation}1\right)\end{array}$

In the second chopping phase, the sampled voltage is flipped, which provides an inverted signal voltage for the CDC. The overall conversion is performed twice with swapped input polarities, which up-modulates the offset and flicker noise to the chopping frequency. With the two conversion results averaged in the digital domain, it creates a notch which attenuates the unwanted low-frequency errors. The system-level chopping operation may be used to improve the thermal noise limited performance by 3 dB.

Method of Operation

FIG. 3 shows a method to operate the exemplary two-stage SAR/TDΔΣM CDC (e.g., for one chopping phase) of FIG. 1 in accordance with an illustrative embodiment. Specifically, FIG. 3 shows a method 300 to perform a first-stage successive approximation and a second-stage discrete-time fine approximation (e.g., time-domain delta sigma modulation) to convert a sensed capacitance signal to an output digital signal in accordance with an illustrative embodiment.

As shown in FIG. 3, the method 300 includes the step of successively approximating (step 302) over a first set of plurality of approximations (e.g., coarse approximation), the sensed capacitance signal (e.g., associated with a measured/converted voltage 116) to generate i) a residue signal (e.g., 126) and ii) first set of converted outputs of the digital signal (e.g., 122). In some embodiments, the 1^st stage SAR CDC circuit portion 102 includes a successive approximation register (SAR) circuit 114 (as an “8b (8-bit) SAR” 114) configured to perform a plurality of successive approximations of an input sensed capacitance signal (e.g., associated with measured/converted voltage 116) acquired from capacitance device 118.

The method 300 further includes generating (step 304) a first digital-to-analog converted signal of the first set of converted outputs of the digital signal (e.g., 122). In some embodiments, the 2^nd stage TDΔΣM CDC circuit portion 106 includes a digital-to-analog converter 120 that uses the first set of converted outputs 122 and feedback signals 124 from the 2^nd stage TDΔΣM CDC circuit portion 106 to generate a SAR conversion residue signal 126 when combined, via a combiner circuit 128, with the input sensed capacitance signal (e.g., via voltage signal 116′). The method 300 further includes the step of finely approximating (e.g., time-domain sigma delta modulation) (306), over a second set of plurality of approximations (e.g., fine approximation), an updated residue signal (e.g., 126) to determine a second set of converted outputs of the digital signal (e.g., 132), wherein the updated residual signal (e.g. 126) include the generated residue signal (e.g., 126) and closed-loop feedback control signals (e.g., 124′) generated based on the first set of plurality of approximations and the second set of plurality of approximations.

In some embodiments, the finely approximating operation (306) comprises quantizing the residue signal, using, in part, a voltage-controlled oscillator (VCO) based integrator operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs by converting the residue signal into a frequency variation to generate an output a phase difference signal; integrating the phase difference signal to generate an integrated phase difference signal; and transforming the integrated phase difference signal to a multi-level output for the closed-loop control.

The method 300 further includes the step of generating (308) a second digital-to-analog converted signal of the second set of converted outputs of the digital signal representing the sensed capacitance signal. In some embodiments, the 2^nd stage TDΔΣM CDC circuit portion 106 includes a TDΔΣM 134 (shown as “TD Operation” 134) configured to quantize the SAR conversion residue 126. In some embodiments, the TDΔΣM 134 includes, in some embodiments, a voltage-controlled oscillator (VCO) based integrator 130 operating in a closed-loop control (shown as 124′) with the DAC 120 to generate a second set of converted outputs 132.

The method 300 further includes the step of combining (310) the first digital-to-analog converted signal and second digital-to-analog converted signal to generate a capacitance-to-digital conversion output. See, FIG. 2C.

In some embodiments, the method 300 further includes converting a second sensed capacitance signal corresponding to another portion of the capacitance source; and averaging output of the first conversion of the sensed capacitance signal and output of the second conversion of the second sensed capacitance signal in the digital domain. See, FIGS. 2A, 2B, and 2C.

Time-Domain Incremental ΔΣ CDC

FIG. 4 depicts a block diagram 400 of the 2^nd stage TDΔΣM CDC circuit portion 106 (shown as 106a) in accordance with an illustrative embodiment. In FIG. 4, Co represents the equivalent residue sensing capacitance 126 (shown as 126a) after the SAR conversion. The 2^nd stage TDΔΣM CDC circuit portion 106 includes a 7-stage ring-VCO (402) implemented by a G_m-stage-driven current-controlled oscillator (CCO) and is configured to convert the residue voltage V_RES (404) into frequency variation at the VCO output (406) and achieves the phase integration. The integrated phase difference is subsequently detected by a phase and frequency detector (PFD) 408. The multi-PFD phase quantization transforms the phase information of each VCO stage to a tri-level output 410, which is then sampled by DFFs (shown having an associated sampling frequency “f_s” 412). The digital output (shown as “t_ΔΣM” 414) is a set of thermometer codes for the ΔΣM feedback DAC. The loop gain L(s) can be derived per Equation 2.

$\begin{array}{cc}L\left(s\right)=\frac{K_{\mathrm{Loop}}}{s}=\frac{K_{\mathrm{VCO}}·N·\beta ·V_{\mathrm{REF}}}{s}& \left(\mathrm{Equation}2\right)\end{array}$

In Equation 2, N represents the number of CCO stages, K_VCO the VCO tuning gain, and V_REF is the full swing of the C_DAC reference voltage. The VCO tuning gain K_VCO=G_m·K_CCO includes the transconductance of the G_m stage and the CCO current to frequency conversion gain. In Equation 2, β is the capacitive feedback factor of the loop and may be set as

$\beta =\frac{C_{FB}}{C_{TOTAL}},$

where C_FB is the unit TDΔΣM feedback capacitor.

The noise transfer function (NTF) can be derived per Equation 3.

$\begin{array}{cc}\mathrm{NTF}=\frac{1-z^{-1}}{1-\left(1-K_{\mathrm{Loop}}·T_s\right)·z^{-1}}& \left(\mathrm{Equation}3\right)\end{array}$

In Equation 3, T_S is the period of the clock sampling the DFFs after the PFD array. In a nominal design, say, with a 5-pF C_X (118), a 5-pF C_SAR, a 2-pF C_PAR extracted as the parasitic capacitance, and a 10-fF C_FB, β can be is calculated as 6×10⁻³. In this example, K_VCO can be set as 552 MHz/V; the sampling frequency f_s set as 5.12 MHz; and V_REF set as 1.1 V. The result is an NTF of (1−z⁻¹)/(1−0.3 z⁻¹). With a 4-bit TDΔΣM and an 8-bit coarse SAR, the OSR may be set to 15 to achieve an 82-dB SQNR.

Example Circuit Implementation

FIG. 5 shows a schematic of the exemplary SAR/TDΔΣM CDC 100 (shown as 100b) in accordance with an illustrative embodiment. The circuit includes two halves that operate differentially, though only a single-ended circuit is shown in the figure for simplicity. That is, only one portion of the “SAR DAC” 502 and “TDΔΣM DAC” 504 are shown while the circuit includes a second portion, shown as “Replica of SAR & TDΔΣM DACs” 506.

As shown in FIG. 5, the exemplary SAR/TDΔΣM CDC 100a may include a differential sensing networks 112 (shown as 112a) include two pairs of C_X and C_OS that are connected through bond pads to the differential SAR and TDΔΣM DAC arrays on chip. Indeed, other configurations may be used, e.g., single pair of C_X and C_OS, or single capacitance element.

During conversion stage Φ₀, the CDC 100b is reset. When conversion stage Φ₀ ends, e.g., by switching the bottom-plate voltages of C_X and C_OS between V_REFP and V_REFN, the differential signal voltage V_X+/V_X− is created at the comparator input (e.g., at 508). The SAR 114 (shown as 114a) performs an 8-bit synchronous conversion of V_X 116 (shown as 116a). By adopting 20-fF SAR DAC unit capacitor, the sensing capacitance dynamic range, (C_X−C_OS), is set to be 5 pF. Although redundancy may be applied, no redundancy is necessarily required during the SAR conversion since any conversion error can be absorbed by the second stage fine quantization. After the conversion, the SAR comparator 508 is reconfigured as a G_m stage and drives a 7-stage dual-CCO 510 to perform the phase-domain integration. The output of the 14-level phase quantizer 512 is fed back to the TDΔΣM DAC array 134a to realize the modulation. With a 1st-order loop (124′) and 25% clock cycle retiming delay (shown as 514), the ΔΣM does not require any excess loop delay compensation.

TDΔΣM Loop Filter Design

FIG. 6 shows a block diagram of an example TDΔΣM 134 (shown as 134b) in accordance with an illustrative embodiment. During conversion stages Φ₀ and Φ₁, the 7-stage dual-CCO 510 (shown as 510a) is disabled. When conversion stage Φ₂ arrives, the CCO rings 510a are closed and start to oscillate. To facilitate the incremental operation, the CCO rings 510a are designed to start with the same initial phase. The integrated phase difference is subsequently detected by the PFD (phase-frequency detector) array, which converts the phase information into a tri-level DAC control signal 516.

To reduce the offset mismatches between the SAR and TDΔΣM stages, the comparator input pair M_1p,n (602, 604) and tail transistor M_b (606) are reused as a G_m stage (508a) that converts the residue V_RES (126) into current (shown as “I_CCO” 608) to drive the CCOs 510a, as shown in FIG. 6.

The CCOs 510a are directly biased by branching the current difference between the PMOS and NMOS current sources,

$I_{\mathrm{CCO}}=\frac{1}{2}{I}_{PMOS}-I_{NMOS}.$

To save energy, only a 360-nA I_CCO may be used in the circuit, resulting in a low output swing of 0.25 V. A level-shifter 610 similar to that described in [29] may be placed between the CCO 510a and the PFD 512 (shown as 512a). The level-shifter 610 is configured to produce a sharp transition edge and consumes only dynamic current.

The digital circuits 620, including PFD-based sampler 512a, re-timer 614, and the encoder (shown also in 614), are powered under 0.6 V, while the analog circuits (616), including feedback DAC (618) and G_m stage (508a), are operated under 1.1 V. Level-shifters 622 are also placed between digital (620) and analog domains (616) to improve the circuit robustness.

Low noise CCO: In some embodiments, the individual cell of the CCO (510a) is implemented to operate differentially. FIG. 7 shows a diagram of a ring voltage-controlled oscillator cell that can be used in the exemplary SAR/TDΔΣM CDC of FIG. 1 in accordance with an illustrative embodiment. Specifically, FIG. 7 shows a diagram of each current-controlled oscillator (CCO) cell 700 in accordance with an illustrative embodiment. The differential operation can be used to improve power supply rejection. In some embodiments, in contrast to the conventional CMOS cross-coupling [21]4241, only PMOS cross-coupling may be used to reduce the capacitive load, thus increasing the VCO tuning gain. In addition, with the reduced number of active devices, only PMOS cross-coupled delay cell contributes less noise compared with the CMOS-coupled structure.

Phase-Frequency Detector (PFD) and Encoder: An array of 7 PFDs is used, in some embodiments, to provide the tri-level phase quantization for each stage CCO output. FIG. 8 shows a diagram of a phase-frequency detector-based sampler 512a (shown as 512b) that can provide tri-level phase quantification output in accordance with an illustrative embodiment. As shown in FIG. 8, the output 802 of a quantizer slide (U, D) (shown as 802 and 804) has three possible codes: “01”, “00”, and “10”, which can be interpreted as (−1, 0, +1) (shown in 806) from a DAC control perspective. The tri-level signal may drive a tri-level DAC (V_REFN; V_CM; V_REFP) (516) without needing additional logic operation. The PFD array 512a may achieve a linear input range of −2π to 2π and produce a 4-bit quantizer output. When compared to an XOR gate, which is widely used in the conventional VCO-based quantizers [23]-[25], the PFD array 512a may quadruple the input phase range while increasing the quantizer bits by 1 bit.

Experimental Results

A study was conducted to evaluate performance of the SAR/TDΔΣM CDC (e.g., 100, 100a) as compared to state-of-art like CDCs in accordance with an illustrative embodiment.

Measured core size: FIG. 9A shows a photo of a fabricated die of a SAR/TDΔΣM CDC (e.g., 100, 100a) in a 40-nm CMOS process in accordance with an illustrative embodiment. FIG. 9B shows the fabricated die of a SAR/TDΔΣM CDC of FIG. 9A with the relevant portion of the circuit expanded. Indeed, the fabricated SAR/TDΔΣM CDC occupies an area of 0.06 mm². The analog supply is set to 1.1 V, while the digital supply is reduced to 0.6 V to save power. With a measurement time of 12.5 is, the fabricated SAR/TDΔΣM CDC was observed to consume 0.083 nJ per conversion. In each conversion, it was also observed that 0.044 nJ was consumed by the reference that charges the capacitors, 0.023 nJ was consumed by the VCO, and 0.016 nJ was consumed by digital logic. Indeed, by adopting time-domain signal processing, the power consumption of ΔΣM had been greatly reduced and no longer dominates the CDC power.

The maximum value of C_X that can be sensed by the fabricated SAR/TDΔΣM CDC for zero C_OS is 5 pF. The capacitance sensing range can be extended, in some embodiments, beyond 5 pF by adjusting the sensing circuit with a nonzero C_OS, which is used to cancel the signal-independent baseline capacitance [24].

DC capacitance measurement. FIG. 10 shows measured DC capacitance performance in accordance with an illustrative embodiment. Per FIG. 10, a series of DC capacitors ranging from 1 pF to 4 pF are measured. Based on the measurement, it was observed that the measured code standard deviation was within 0.045 LSB, which translates to a capacitance resolution of 0.23 fF. In addition, it was observed that the system measured the noise-limited capacitance resolution.

Measured Static Performance. FIG. 11 shows the static performance of the CDC measured in a linearity test mode in accordance with an illustrative embodiment. As shown in FIG. 11, the measured DNL and INL were within 0.11 LSB and 0.15 LSB, respectively.

Measured SNDR and SFDR. FIG. 12 shows measured SNDR and SFDR performance across operating frequency for the fabricated SAR/TDΔΣM CDC of FIG. 9 in accordance with an illustrative embodiment. In FIG. 12, it can be observed that the fabricated SAR/TDΔΣM CDC can provide measured SNDR and SFDR of 75.8 dB and 88.9 dB, respectively across the measured frequency range up to 40 KHz. The fabricated SAR/TDΔΣM CDC can provide a corresponding CDC resolution of 0.29 fF, which includes both noise and non-linearities.

FIG. 13 shows measured SNDR and SFDR across an amplitude sweep for the fabricated SAR/TDΔΣM CDC of FIG. 9 in accordance with an illustrative embodiment. As shown in FIG. 13, it was observed that the fabricated SAR/TDΔΣM CDC has a dynamic range of 79 dB.

Table 1 shows performance summary of the SAR/TDΔΣM CDC device of FIG. 9 as compared to other state-of-the-arts CDCs.

	JSSC-13	VLSI-16	ISSCC-14	VLSI-14	JSSC-17	JSSC-15	ISSCC-15
	Tan [2]	Omran [7]	Ha [10]	Oh [18]	Sanyal [24]	Oh [30]	Jung [31]	This work
Process [nm]	160	180	180	160	40	180	40	40
Architecture	ΔΣM	SAR	SAR	Zoom SAR +	SAR + VCO	Dual-	Delay-	Zoom SAR +
				ΔΣM		Slope	Chain	TDΔΣM
Measured Sensor	Dual	Dual	Single	Single	Single	Single	Single	Dual
Back. Cal. Free	✓	✓	✓	✓	X	✓	✓	✓
OTA-Free	X	X	✓	X	✓	X	X	✓
Input Range [pF]	0.54-1.06	0-12.66	2.5-75.3	0-24	0-5	5.3-30.7	0.7-10000	0-5
Meas. Time [μs]	800	16	4000	230	1	6400	19	12.5
Resolution [fF]	0.07	1.1	6	0.16	1.1	54.9	12.3	0.29
Energy [nJ]	8.24	0.12	0.64	7.75	0.075	0.7044	0.0353	0.083
SNDR1 [dB]	68.4	70.6	81.8	94.7	64.2	44.24	49.73	75.8
FoM2	3800	35	64	175	55	53004	1403	16
[fJ/conv-step]

In Table 1, SNDR is defined in Equation 4. FOM is defined as

$\mathrm{FOM}=\frac{\mathrm{Energy}}{2\left(\mathrm{SNDR}-1.76\right)\left(6.02\right)}.$

Reference 3 in the table is measured with 11.3 pF. Reference 4 in the table is calculated with one subrange.

The SAR/TDΔΣM CDC used in the study was OTA-free. The exemplary SAR/TDΔΣM CDC used a VCO to realize the TDM, and the VCO is configured to operate in close-loop operation to obviates the need for background calibration. Effective number of bits (ENOB) is calculated as ENOB=(SNDR−1.76)/6.02. The figure of merit (FoM) was defined as FoM=Energy/2^ENOB, which represents the energy required for each effective bit conversion. Overall, the exemplary SAR/TDΔΣM CDC achieved a CDC FoM of 16 fJ/conversion-step, which represents a 2 times energy-efficiency improvement over the state-of-the-art works, including those referenced herein.

As shown in FIG. 14, it can be seen that the exemplary SAR/TDΔΣM CDC architecture compares favorably with state-of-the-art and achieves the highest energy efficiency.

DISCUSSION

Capacitive sensors are widely used to measure various physical quantities, including pressure [1], humidity [2], and displacement [3]. Ultra-low-power capacitance-to-digital converter (CDCs) may be require for sensors with limited battery capacity or powered by energy harvesters. There are a few conventional architectures developed to perform the direct capacitance-to-digital conversion. The successive approximation register (SAR)-based CDCs have attracted attention due to the superior energy efficiency of their analog-to-digital converter (ADC) counterparts [4]-[6]. A SAR CDC may be simple to design and may achieve high energy efficiency for low-to-medium resolution applications. However, the passive charge sharing (CS) between the sensing capacitor and the capacitive digital-to-analog converter (DAC) causes signal degradation.

To reach high resolution, CS may require a low-noise comparator [7]-[9] or operational transconductance amplifier (OTA)-based active charge transfer [10], resulting in degraded power efficiency.

Inherited from ΔΣ ADCs, the CDCs [2], [3], [11]-[13] naturally suit high-resolution applications. Nevertheless, their energy efficiency may be limited by the OTA-based integrators in the loop filter, which may consume static current. Moreover, a large oversampling ratio (OSR) may be needed in the conventional single-bit loop, which may require repeatedly charging of the sensing capacitor, e.g., a third-order loop filter with an OSR of 200 may be needed in [2].

To maintain high resolution while reducing conversion energy, the zoom architecture, a subcategory of two-step converters, was proposed in [14]-[16]. It used a SAR converter to coarsely quantize the input, followed by a modulator to perform fine quantization. Although the zoom-in nature restricted the converter to near-DC inputs, it was appropriate for sensor nodes where environmental parameters (e.g., capacitance) changed very slowly [17]. A zoom CDC [18] combined the merits of SAR and M, and thus, it can achieve high resolution with only one-time charging of the sensing capacitor.

The zoom architecture may provide a more balanced trade-off between conversion accuracy and energy consumption. However, in that two-step architecture, a high-order loop filter was still required with a single-bit quantizer. It dominated the system power due to the static current in the OTA-embedded loop filter. To address such limitation, a multi-bit quantizer can be applied to reduce the loop filter order. However, to ensure loop linearity, dynamic element matching (DEM) block are usually implemented to address the multi-bit feedback DAC mismatch issue, which consume extra power and area.

Recently, time-domain (TD) analog signal processing techniques became popular due to their power efficiency in the advanced CMOS technologies. By representing and processing signals using time-related variables, such as frequency and phase, TD signal processing benefits from transistor scaling, as time information can be processed through mostly digital circuits.

Recent advancements in ΔΣMs [19]-[23] replaced the conventional OTA-based active-RC integrator with a voltage-controlled oscillator (VCO)-based integrator, which conferred several key advantages: 1) the VCO can be mostly digital and scaling friendly; it can work well under low supply voltage and consumes low power; 2) it can provide infinite DC gain in the phase domain, and thus is well-suited for high-precision applications that demand high DC loop gain; 3) it can have intrinsic spatial phase quantization, and thus, can enable a simple multi-bit quantization using only minimum-size DFFs; it can obviate the need for an array of low-offset comparator. With these merits, a two-step CDC in [24] achieved low power consumption by performing the open-loop VCO-based ΔΣM and eliminating power-hungry OTAs. With the intrinsic phase quantization, a 3-bit quantizer was implemented by XOR-gates, which enabled a low OSR design (e.g., 3) and further reduced the energy consumption. However, the process, voltage, and temperature (PVT)-sensitive VCO gain variation can cause inter-stage gain error, which can degrade the conversion accuracy. A background calibration loop was implemented to track the VCO gain, which increased the design complexity and made it unsuitable for single-shot measurement in sensor node applications due to the long convergence time.

The exemplary SAR/TDΔΣM CDC implements an incremental two-step CDC that includes a coarse SAR CDC and a fine closed-loop time-domain CDC. Comparing to the open-loop VCO-based CDC [24], the exemplary SAR/TDΔΣM CDC performs closed-loop TDM-based CDC, which obviates the need for background calibration. The closed-loop gain is also set by the capacitor ratio, which is precisely matched by merging the feedback DAC with the SAR DAC. Therefore, the VCO gain variation cannot change the feedback factor, and thus, has a negligible impact on CDC performance. In the exemplary SAR/TDΔΣM CDC design, 20% VCO gain variation can result in only 2-dB of SQNR change. By implementing a phase and frequency detector (PFD)-based quantifier (rather than an XOR-based phase quantizer), the exemplary SAR/TDΔΣM CDC in such embodiment may obtain one extra quantizer bit with the same number of VCO stages, which can further reduce the required OSR for the target resolution. Further, the dual-VCO integrator of the exemplary SAR/TDΔΣM CDC can be used to bring intrinsic clocked averaging (ICLA) capability that can address the M feedback DAC mismatches, and obviate the need for dedicated DEM block, as previously suggested in [25]. By reusing the SAR comparator as the G_m stage of the VCO-based integrator, offsets in the SAR and the M may be inherently matched, which can remove the need for offset mismatch calibration. With a largely simplified loop filter, the exemplary SAR/TDΔΣM CDC can be fabricated in 40-nm CMOS to achieve a resolution of 0.29 fF while dissipating only 0.083 nJ per conversion. The exemplary SAR/TDΔΣM CDC can thus improve energy efficiency by over 2 times as compared to the state-of-the-art like devices.

Capacitance Resolution. Three noise sources may limit the capacitance resolution of the exemplary SAR/TDΔΣM CDC: 1) kT/C sampling noise from Φ₀; 2) thermal noise of the TDΔΣM; and 3) quantization noise. Indeed, the flicker noise may be primarily attenuated by the system-level chopping as discussed herein, and the comparator noise may be canceled at the CDC output when two-step conversion results are combined.

The capacitance sampling noise, referred to the single-ended input, may be calculated by Equation 5A.

$\begin{array}{cc}{C}_{n,\mathrm{sample}}=\sqrt{\frac{\mathrm{kT}}{C_{\mathrm{TOTAL}}}}·\frac{C_{\mathrm{TOTAL}}}{V_{\mathrm{REF}}}& \left(\mathrm{Equation}5A\right)\end{array}$

Per Equation 5A, with a 12-pF C_TOTAL, 1.1V V_REF and an OSR of 15, the input-referred capacitance noise is 52 aF. The capacitance noise induced by the TDΔΣM can be mainly contributed by the G_m stage and the following CCO. For the CCO, the input-referred noise current PSD may be calculated per Equation 5B.

$\begin{array}{cc}\stackrel{\_}{{\iota }_{n,\mathrm{cco}}^2}=\frac{D}{{\pi }^2{K}_{\mathrm{CCO}}^2}·\Delta f& \left(\mathrm{Equation}5B\right)\end{array}$

In Equation 5B, D is the phase diffusion constant and can be obtained from phase noise simulation, e.g., as described in [28]. Based on a SPICE simulation, the CCO input-referred noise current PSD can be calculated as 194 fA/√{square root over (Hz)}.

Together with the Gm stage, whose input-referred noise voltage PSD can be calculated as

$\stackrel{\_}{{\upsilon }_{n,\mathrm{cco}}^2}=\frac{4\mathrm{kT}\gamma }{g_m}·\Delta f.$

The TDΔΣM noise referend to the single-ended input may be calculated as Equation 6.

$\begin{array}{cc}{c}_{n,\mathrm{dsm}}\approx \sqrt{\left(\frac{\stackrel{\_}{v_{n,\mathrm{gm}}^2}}{\Delta f}+\frac{\stackrel{\_}{{\iota }_{n,\mathrm{cco}}^2}}{\Delta f·g_m^2}\right)·\frac{f_s}{2\mathrm{OSR}}}·\frac{C_{\mathrm{TOTAL}}}{V_{\mathrm{REF}}}& \left(\mathrm{Equation}6\right)\end{array}$

In Equation 6, g_m=30 μS, the Gm stage can contribute over 90% of the thermal noise, resulting in a 0.12-fF single-ended c_n,dsm.

The quantization noise of the CDC can be calculated from the quantification noise of the incremental TDΔΣM as the quantization noise of the SAR stage can be canceled at the output. The single-ended ΔΣM may have an equivalent quantization step of C_LSB=5 fF. Extracted from simulation, the single-ended rms quantization noise is 0.15 fF. Hence, the total calculated rms capacitance noise of the CDC can be calculated as 0.19 fF.

Redundancy Arrangement. A trade-off between resolution and redundancy may be considered when choosing a unit capacitor size of the TDΔΣM DAC.

The exemplary SAR/TDΔΣM CDC may implement a tri-level feedback DAC with 10-fF unit capacitance to produce an equivalent M LSB of 5 fF. With 20 fF as the SAR LSB, an inter-stage gain of 4 may be provided between the two-step conversions.

FIG. 15 shows an example of redundancy allocation between 1^st stage SAR and 2^nd stage TDΔΣM in accordance with an illustrative embodiment. Indeed, other degree of redundancy allocation may be used.

As shown in FIG. 15, the full input range of the TDΔΣM may be set as 14 LSB as determined by the tri-level outputs of the 7 PFDs. With the 4-LSB SAR conversion residue, a 5 LSB inter-stage redundancy range may be employed to address any offset mismatch, which may have been already minimized by reusing the comparator (e.g., 508) as the Gm stage.

Two blocks may contribute to the inter-stage offsets: 1) the cross-coupled inverter pair in the comparator, and 2) the ring-CCO. With 0.6-LSB (1 sigma) input-referred comparator cross-coupled latch offset and 0.5-LSB (1 sigma) input-referred ring-CCO offset, an overall offset deviation of 0.8 LSB may be expected in the system. With 5 LSB inter-stage redundancy provided, greater than 6 sigma tolerance of offset mismatches may be achieved.

Indeed, if there is any SAR conversion error, the error may be absorbed by the redundancy. To this end, the offsets between the two stages may be tolerated without any offset calibration.

Non-ideal effects in TDCDC per Capacitive DAC Mismatch. Capacitive DAC is often the key component in a given CDC design and often defines the conversion accuracy. Static element mismatch in the capacitor array can lead to the increased noise floor as well as harmonic distortion.

The capacitive DAC array of the exemplary SAR/TDΔΣM CDC, in some embodiments, includes a SAR DAC with 20-fF unit capacitor and a ΔΣM DAC with a 10-fF unit capacitor. To ensure a better matching, the two capacitive DACs are combined together in the layout as discussed herein. The SAR unit capacitor may be constructed by two ΔΣM unit capacitors.

As in any multi-bit ΔΣM, DAC mismatch can cause non-linearity. The issue may be addressed by having an explicit DEM circuit to scramble the DAC element selection pattern; however, it incurs additional power and area cost.

In the exemplary SAR/TDΔΣM CDC, a dual-VCO-based integrator is implemented to provide ICLA capability similar, though different in implementation, to those described in [22], [25]. The transition edge of the VCO may be configured to rotate at twice the VCO center frequency, which may result in the same rotation frequency of the selected elements in the DAC array as 2f_VCO. Indeed, the mismatch errors may be up-modulated to even-order harmonics of the VCO center frequency and are inherently suppressed by the decimation filter.

With the ICLA capability, the exemplary SAR/TDΔΣM CDC performance may be limited by the SAR DAC mismatches. In certain design of the exemplary SAR/TDΔΣM CDC, the SAR unit capacitor may be constructed by two 10-fF M unit capacitors to provide a mismatch error of 0.14% (1 sigma) (e.g., per Monte-Carlo (MC) simulation).

FIG. 16 shows simulation results for a 1000-run Monte Carlo simulation of the exemplary SAR/TDΔΣM CDC with capacitor mismatch in accordance with an illustrative embodiment. As shown in FIG. 16, over 97% of the samples can guarantee a 76-dB SNDR.

Non-ideal effects in TDCDC per VCO Gain Variation. One limitation of a conventional time-domain design [24] is the PVT-induced VCO gain variation, which can change an inter-stage gain of that design and, thus, degrades conversion linearity. The exemplary SAR/TDΔΣM CDC employs an inter-stage gain between SAR and TDΔΣM, in some embodiments, that is precisely defined as the capacitor ratio and is independent of VCO gain. With the high DC loop gain provided by the VCO integrator, as indicated in (Equation 2), the variation may only have a limited impact on the system performance.

FIG. 17A shows a plot showing comparative performance between an open-loop design and the closed-loop design of the exemplary SAR/TDΔΣM CDC regarding the VCO gain variation in accordance with an illustrative embodiment. Indeed, FIG. 17A shows the robustness of the exemplary SAR/TDΔΣM CDC architecture. FIG. 17B shows block diagrams of the open-loop design and the closed-loop design of the exemplary SAR/TDΔΣM CDC used in the study of FIG. 17A in accordance with an illustrative embodiment.

As shown in FIG. 17A, with a ±20% VCO gain variation, the open-loop design has a significant performance degradation as high as 15 dB while the exemplary SAR/TDΔΣM CDC under study only has a 2-dB SQNR drop. Such a drop may be considered to be a negligible impact on the system SNR considering thermal noise and DAC mismatches.

Indeed, the exemplary SAR/TDΔΣM CDC provides an incremental two-step CDC with a time-domain ΔΣ modulator that can largely simplify the loop filter by using, e.g., rather than an OTA-based integrator, a VCO and using a multi-bit phase quantizer. The exemplary SAR/TDΔΣM CDC may achieve a resolution of 0.29 fF with an energy efficiency of 16 fJ/conversion-step, representing a 2 times improvement over the state-of-the-art like designs.

The exemplary SAR/TDΔΣM CDC may be implemented in IC or microcontroller for use in IoT (Internet of Things) applications. With the booming of IoT, there expect to have billions of devices in our surroundings. The environmental sensing plays a key role in the smart city concept. Among them, capacitive sensors are widely applied in the temperature, humidity, placement, audio sensors, e.g., microphone, touchscreen. The CDC plays the role of converting the physical quantities to the digital output which can be processed by the back-end CPUs. The energy efficiency is vital due to the limited battery energy. The exemplary SAR/TDΔΣM CDC can directly reduce the energy consumption and extend the battery life of such applications.

Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps or operational flow; plain meaning derived from grammatical organization or punctuation; the number or type of embodiments described in the specification. Throughout this application, various publications are referenced. The disclosures of these publications in their entireties are hereby incorporated by reference into this application in order to more fully describe the state of the art to which the methods and systems pertain.

Also, unless clearly stated otherwise, when any number or range is described herein, that number or range is approximate. When any range is described herein, unless clearly stated otherwise, that range includes all values therein and all sub ranges therein. Any information in any material (e.g., a United States/foreign patent, United States/foreign patent application, book, article, etc.) that has been incorporated by reference herein, is only incorporated by reference to the extent that no conflict exists between such information and the other statements and drawings set forth herein. In the event of such conflict, including a conflict that would render invalid any claim herein or seeking priority hereto, then any such conflicting information in such incorporated by reference material is specifically not incorporated by reference herein.

Although example embodiments of the present disclosure are explained in detail herein, it is to be understood that other embodiments are contemplated. Accordingly, it is not intended that the present disclosure be limited in its scope to the details of construction and arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

In summary, while the present invention has been described with respect to specific embodiments, many modifications, variations, alterations, substitutions, and equivalents will be apparent to those skilled in the art. The present invention is not to be limited in scope by the specific embodiment described herein. Indeed, various modifications of the present invention, in addition to those described herein, will be apparent to those of skill in the art from the foregoing description and accompanying drawings. Accordingly, the invention is to be considered as limited only by the spirit and scope of the disclosure, including all modifications and equivalents.

Still other embodiments will become readily apparent to those skilled in this art from reading the above-recited detailed description and drawings of certain exemplary embodiments. It should be understood that numerous variations, modifications, and additional embodiments are possible, and accordingly, all such variations, modifications, and embodiments are to be regarded as being within the spirit and scope of this application. For example, regardless of the content of any portion (e.g., title, field, background, summary, abstract, drawing figure, etc.) of this application, unless clearly specified to the contrary, there is no requirement for the inclusion in any claim herein or of any application claiming priority hereto of any particular described or illustrated activity or element, any particular sequence of such activities, or any particular interrelationship of such elements. Moreover, any activity can be repeated, any activity can be performed by multiple entities, and/or any element can be duplicated. Further, any activity or element can be excluded, the sequence of activities can vary, and/or the interrelationship of elements can vary. Unless clearly specified to the contrary, there is no requirement for any particular described or illustrated activity or element, any particular sequence or such activities, any particular size, speed, material, dimension or frequency, or any particularly interrelationship of such elements. Accordingly, the descriptions and drawings are to be regarded as illustrative in nature, and not as restrictive. Moreover, when any number or range is described herein, unless clearly stated otherwise, that number or range is approximate. When any range is described herein, unless clearly stated otherwise, that range includes all values therein and all sub ranges therein. Any information in any material (e.g., a United States/foreign patent, United States/foreign patent application, book, article, etc.) that has been incorporated by reference herein, is only incorporated by reference to the extent that no conflict exists between such information and the other statements and drawings set forth herein. In the event of such conflict, including a conflict that would render invalid any claim herein or seeking priority hereto, then any such conflicting information in such incorporated by reference material is specifically not incorporated by reference herein.

The following patents, applications and publications as listed below and throughout this document are hereby incorporated by reference in their entirety herein.

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Claims

1. A capacitance-to-digital converter (CDC) comprising: a first stage successive approximation register capacitance-to-digital converter (1st stage SAR CDC) circuit portion configured to perform a plurality of successive approximations of an input capacitance signal to generate a SAR conversion residue and a first set of converted outputs; anda second stage time-domain incremental delta-sigma modulator capacitance-to-digital converter (2nd stage TD incremental ΔΣM CDC) circuit portion that quantizes the SAR conversion residue, using, in part, a voltage-controlled oscillator (VCO) based integrator of the 2nd stage TD incremental ΔΣM CDC operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs, wherein the 2nd stage TD incremental ΔΣM CDC generates a second set of converted outputs as a representation of an input sensed capacitance signal.

2. The capacitance-to-digital converter of claim 1, wherein the 2nd stage TD incremental ΔΣM CDC circuit portion comprises: a N-stage ring VCO circuit; anda phase and frequency detector (PFD) coupled to the N-stage ring VCO circuit to an output for the closed-loop control.

3. The capacitance-to-digital converter of claim 2, wherein the 2nd stage TD incremental ΔΣM CDC circuit portion further comprises a passive charge sharing (CS) circuit coupled to the N-stage ring VCO circuit.

4. The capacitance-to-digital converter of claim 1, wherein the N-stage ring VCO circuit is implemented as a Gm-stage-driven current-controlled oscillator (CCO).

5. The capacitance-to-digital converter of claim 1, wherein the Gm-stage-driven CCO is configured to convert the SAR conversion residue into a frequency variation at the output N-stage ring VCO and generate output a phase difference signal.

6. The capacitance-to-digital converter of claim 2, wherein the PFD is configured to detect and integrate the phase difference signal to generate an integrated phase difference signal.

7. The capacitance-to-digital converter of claim 6, wherein the PFD comprises a multi-phase quantizer configured to transform the integrated phase difference signal to a multi-level output, the PFD further comprising a sampling circuit to sample the multi-level output.

8. The capacitance-to-digital converter of claim 1, wherein the close-loop control comprises a first-order loop.

9. The capacitance-to-digital converter of claim 1, wherein the 2nd stage TD incremental ΔΣM CDC is configured to operate in an incremental mode.

10. The capacitance-to-digital converter of claim 1, wherein the 2nd stage TD incremental ΔΣM CDC is configured to disable operation during SAR operation of the 1st stage SAR CDC.

11. The capacitance-to-digital converter of claim 1, further comprising a capacitance sensing network circuit coupled to the 1st stage SAR CDC circuit portion, the capacitance sensing network circuit being configured to switch between a first capacitance sensing input associated with a first capacitive plate and a second capacitance sensing input associated with a second capacitive plate.

12. The capacitance-to-digital converter of claim 5, wherein the capacitance sensing network circuit comprises a chopper circuit, the chopper be configured to perform the switching between the first capacitance sensing input and the second capacitance sensing input.

13. The capacitance-to-digital converter of claim 6, wherein the 2nd stage TD incremental ΔΣM CDC is configured to disable operations during sensing operation of the capacitance sensing network circuit.

14. The capacitance-to-digital converter of claim 1, wherein the 2nd stage TD incremental ΔΣM CDC is configured as an N-bit incremental ΔΣM CDC selected from the group consisting of: a 2-bit incremental ΔΣM CDC, a 3-bit incremental ΔΣM CDC, a 4-bit incremental ΔΣM CDC, a 5-bit incremental ΔΣM CDC, a 6-bit incremental ΔΣM CDC, a 7-bit incremental ΔΣM CDC, an 8-bit incremental ΔΣM CDC, a 9-bit incremental ΔΣM CDC, and a 10-bit incremental ΔΣM CDC.

15. The capacitance-to-digital converter of claim 1, wherein the capacitance-to-digital converter is configured in a microcontroller.

16. The capacitance-to-digital converter of claim 1, wherein the capacitance-to-digital converter is configured an as integrated chip.

17. A method of converting a sensed capacitance signal, associated with a capacitance source, to an output digital signal representing the sensed capacitance analog signal, the method comprising: successively approximating over a first set of plurality of approximations, the sensed capacitance signal to generate i) a residue signal and ii) first set of converted outputs of the digital signal;generating a first digital-to-analog converted signal of the first set of converted outputs of the digital signal;quantizing the residue signal, using, in part, a voltage-controlled oscillator (VCO) based integrator operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs; and generating a second digital-to-analog converted signal of the second set of converted outputs of the digital signal representing the sensed capacitance signal; andcombining the first digital-to-analog converted signal and second digital-to-analog converted signal to generate a capacitance-to-digital conversion output.

18. The method of claim 17, wherein the quantification operation comprises: converting the residue signal into a frequency variation to generate an output a phase difference signal;integrating the phase difference signal to generate an integrated phase difference signal; andtransforming the integrated phase difference signal to a multi-level output for the closed-loop control.

19. The method of claim 17, wherein the quantization operation is performed via a time-domain sigma-delta modulator (TD ΔΣM).

20. An apparatus comprising: a first stage successive approximation register capacitance-to-digital converter (1st stage SAR CDC) circuit portion configured to perform a plurality of successive approximations of an input capacitance signal to generate a SAR conversion residue and a first set of converted outputs; anda second stage time-domain incremental delta-sigma modulator capacitance-to-digital converter (2nd stage TD incremental ΔΣM CDC) circuit portion that quantizes the SAR conversion residue, using, in part, a voltage-controlled oscillator (VCO) based integrator of the 2nd stage TD incremental ΔΣM CDC operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs, wherein the 2nd stage TD incremental ΔΣM CDC generates a second set of converted outputs as a representation of an input sensed capacitance signal.