Patent Application
20250233596
This application claims the benefit of European Patent Application No. 24386005.3 filed Jan. 16, 2024, the disclosure of which is incorporated herein by reference in its entirety.
This disclosure relates to time-interleaved analogue-to-digital converters and methods of operating them.
An analogue-to-digital converter (ADC) is a system that converts an analogue signal into a digital signal. It is known to arrange several analogue to digital converters in parallel, each sampling at different instants, and then to combine their outputs together to reconstruct an output signal which is the digitized analogue input of the ADC (e.g. by plotting a graph of each output relative to its respective sampling time). This “time-interleaved” arrangement of ADCs achieves a higher throughput of the overall arrangement without increasing the clock frequency of the individual ADCs. This is effective since there is a fundamental limit to the maximum sampling speed of a single ADC.
It is possible that one or more ADCs within the time-interleaved ADC topology may become faulty or may fail, for example due to component aging, harsh environmental conditions such as extreme temperatures or high humidity, or an unexpected analogue stress, for example caused by a voltage spike. In case one or more of the individual ADCs fails, such an interleaved ADCs may become non-functional, or its digital output may become compromised, e.g. be less accurate or contain more noise.
It is a goal of the present disclosure to provide a time-interleaved analogue-to-digital converter which addresses some of these shortcomings.
According to a first aspect of this disclosure, there is provided a time-interleaved analogue-to-digital converter. The converter includes: a first analogue-to-digital converter, arranged to sample an analogue input and produce a digital output based on the sampled analogue input; a second analogue-to-digital converter, arranged to sample the analogue input and produce a digital output based on the sampled analogue input; a third analogue-to-digital converter, arranged to sample the analogue input and produce a digital output based on the sampled analogue input; and a signal interleaving portion, arranged to combine the digital outputs from the first analogue-to-digital converter and the second analogue-to-digital converter to produce a digital output signal. The time-interleaved analogue-to-digital converter is configured for operation both in an operational mode, and in a compensation mode, wherein the time-interleaved analogue-to-digital converter is configured to operate in the compensation mode when the third analogue-to-digital converter is non-functional. In the operational mode, the first analogue-to-digital converter is arranged to sample the analogue input at a first frequency and the second analogue-to-digital converter is arranged to sample the analogue input at a second frequency. In the compensation mode, the first analogue-to-digital converter is arranged to sample the analogue input at a third frequency and the second analogue-to-digital converter is arranged to sample the analogue input at a fourth frequency, wherein the third frequency is higher than the first frequency, and wherein the fourth frequency is higher than the second frequency.
Further according to this disclosure, there is also provided a method of operating a time-interleaved analogue-to-digital converter, comprising: in a compensation mode in which at least one analogue-to-digital converter of the time-interleaved analogue-to-digital converter is non-functional, increasing the sampling frequency of at least two of the remaining functional analogue-to-digital converters (optionally all of the remaining functional analogue-to-digital converters) of the time-interleaved analogue-to-digital converter, compared to their respective operating frequencies in an operational mode.
The time-interleaved analogue-to-digital converter is configured to operate in the compensation mode when the third analogue-to-digital converter is non-functional. By functional it will be understood that the analogue-to-digital converter is able to operate to convert an analogue input to a digital output to within a tolerable level of accuracy. Conversely, a non-functional analogue-to-digital converter is one unable (at a given time) to operate in this way. Thus, by increasing the sampling rates of the first and second analogue-to-digital converters (optionally all functional analogue-to-digital converters) in the compensation mode, this (partially or fully) compensates for the loss of samples from the third, non-functional (i.e. faulty) analogue-to-digital converter.
The time-interleaved analogue-to-digital converter may be configured to operate in the compensation mode when any of the first analogue-to-digital converter, the second analogue-to-digital converter and the third analogue-to-digital converter are non-functional (and to increase the sampling frequency of the remaining functional analogue-to-digital converters accordingly). For example, if the first analogue-to-digital converter is non-functional, in the compensation mode the sampling frequencies of the second analogue-to-digital converter and the third analogue-to-digital converter are increased, provided they are both still functional.
In some examples, the time-interleaved analogue-to-digital converter is configured to operate in the operational mode when all analogue-to-digital converters of the time-interleaved analogue-to-digital converter are functional. Thus, the operational mode refers to the mode of normal operation of the time-interleaved analogue-to-digital converter in which all of its component analogue-to-digital converters function successfully.
It is described herein above that the sampling frequency of at least two analogue-to-digital converters of the time-interleaved analogue-to-digital converter are increased, in the compensation mode. This is advantageous since by increasing the frequency of more than one analogue-to-digital converter, the sampling frequency of each needs to be increased less (to achieve the same level of compensation) than if only one analogue-to-digital converter were adjusted to compensate. Thus, the overhead required on the sampling frequency of each analogue-to-digital converter is lower.
In order to minimize the required increase in sampling frequency of the analogue-to-digital converters, it is preferable if the sampling frequency of all functional analogue-to-digital converters is increased to compensate for any non-functional analogue-to-digital converters. Thus, in some examples the time-interleaved analogue-to-digital converter is configured such that all functional analogue-to-digital converters sample the analogue input at a higher frequency in the compensation mode than in the operational mode. Dividing the sampling rate increase across all functional ADCs is beneficial because there is a limit of how much an ADC sampling rate can be increased. Furthermore, keeping the switching frequency of sampling signals relatively low using this method maintains the signals travelling on a digital board providing the ADC at a low frequency, which reduces the electro-magnetic interference on the board. Not requiring high frequency signals also reduces the difficulty of designing the digital board.
By arranging the first and second analogue-to-digital converters to sample at a higher frequency in a compensation mode than in the (normal) operational mode, the time-interleaved analogue-to-digital converter is able to compensate for the non-functioning of one or more other analogue-to-digital converters of the time-interleaved analogue-to-digital converter. Without any compensation, the total (or overall) sampling rate of the time-interleaved analogue-to-digital converter would decrease when one or more of the analogue-to-digital converters was non-functional (at a given time). However, according to the present disclosure this total sample rate is increased, relative to if no compensation action was taken, by increasing the sampling frequency of the functional analogue-to-digital converters. By increasing the sampling rate of the functional ADCs in an interleaved system after one or more ADCs has failed the time-interleaved ADC can maintain the overall system sampling rate i.e. allow the system to function as before the ADC/ADCs has failed.
It will be understood that although referred to herein simply as analogue-to-digital converters of the time-interleaved analogue-to-digital converter, these individual analogue-to-digital converters which together provide the time-interleaved analogue-to-digital converter may also be referred to as sub-analogue-to-digital converters.
In some examples, the first frequency and the second frequency (i.e. at which the first and second analogue-to-digital converters sample in the operational mode) are the same. In some examples, all analogue-to-digital converters of the time-interleaved analogue-to-digital converter are arranged (i.e. when functional) to sample at the same frequency in the operational mode. In reality, minor errors may cause the analogue-to-digital converters to sample at slightly different frequencies to each other, but nonetheless it will be understood that they are arranged such as to sample at the same frequency.
In some examples, the third frequency and the fourth frequency (i.e. at which the first and second analogue-to-digital converters sample in the compensation mode) are the same. In some examples, all functional analogue-to-digital converters of the time-interleaved analogue-to-digital converters are arranged (i.e. when functional) to sample at the same frequency in the compensation mode (a frequency higher than the sampling frequency in the operational mode).
The sampling frequency of an analogue-to-digital converter will be understood as the number of times in a given time period (e.g. per second) that that particular analogue-to-digital converter samples the analogue input, and produces a respective digital output based on that analogue input. The frequency is inversely related to the time period, T, between successive (i.e. immediately adjacent in time) instances of a particular analogue-to-digital converter sampling the analogue input. Each analogue-to-digital converter may be arranged to receive a respective (periodic) timing signal. Each analogue-to-digital converter may be triggered to sample the analogue input by a rising edge (e.g. a peak or spike) in its respective timing signal. It will be understood in this case that the frequency of the timing signal corresponds to the sampling frequency of the corresponding analogue-to-digital converter, and that the sampling frequency of the analogue-to-digital converter may be adjusted by adjusting the corresponding timing signal. The timing signal may be received by the analogue-to-digital converter from an external source (which may be one external source supplying the timing signals to all of the analogue-to-digital converters, or may be a separate source of each analogue-to-digital converter), or it may be received internally from a component which forms part of the analogue-to-digital converter.
It will furthermore by understood that the total, or overall, operational sampling rate of the time-interleaved analogue-to-digital converter (i.e. in the operational mode when all analogue-to-digital converters are functional) is the sum of the sampling frequencies of all of the analogue-to-digital converters that are part of the time-interleaved analogue-to-digital converter. At a given time, the total sampling rate of the time-interleaved analogue-to-digital converter is the sum of the sampling frequencies of all of the analogue-to-digital converters that are functional at that time.
Where all of the analogue-to-digital converters of the time-interleaved analogue-to-digital converter sample at the same frequency, the total sampling rate of the time-interleaved analogue-to-digital converter is the sampling frequency of one of the analogue-to-digital converters, multiplied by the number of (functional) analogue-to-digital converters in the time-interleaved analogue-to-digital converter.
The signal interleaving portion is arranged to combine the digital outputs from the first analogue-to-digital converter and the second analogue-to-digital converter (i.e. from at least the first and second analogue-to-digital converters) to produce the digital output signal. It will be appreciated that although arranged to combine the outputs of these converters, it does so in a given instance only if the converter is functional. The signal interleaving portion may be arranged to combine the digital outputs from the first analogue-to-digital converter and the second analogue-to-digital converter and also the third analogue-to-digital converter to produce the digital output signal. The signal interleaving portion may be arranged to combine the digital outputs of all functional analogue-to-digital converters to produce the digital output signal.
It is particularly advantageous if the total sampling frequency is maintained above a threshold level, since this ensures that the digital output signal from the signal interleaving portion is reasonably accurate-if the total sampling frequency of the time-interleaved analogue-to-digital converter drops too low, the digital output signal will not accurately reflect the analogue input signal.
It may be particularly advantageous if the total sampling frequency is maintained (approximately) at least at the same level which it is at in the operational mode (the total operational sampling frequency), even where one or more of the analogue-to-digital converters is non-functional. Thus, in some examples, the frequencies of the analogue-to-digital converters are increased in the compensation mode such that a total sampling frequency of the time-interleaved analogue-to-digital converter in the compensation mode is at least as high as in the operational mode. Optionally, the total sampling frequency of the time-interleaved analogue-to-digital converter in the operational mode is the same as the total sampling frequency in the compensation mode.
It will be appreciated that the total operational sampling frequency is lower than the highest possible sampling frequency of the time-interleaved analogue-to-digital converter, since in order to allow the sampling frequencies to be increased in the compensation mode, each analogue-to-digital converter is not operating at its maximum possible sampling frequency in the operational mode (i.e. there is headroom on the sampling rate of each analogue-to-digital converter in the operational mode).
In order to achieve a total sampling frequency in the compensation mode that is at least as high as the total operational sampling frequency, the sampling frequency of each analogue-to-digital converter in the operational mode may be multiplied by a respective ratio to calculate its sampling frequency in the compensation mode. The ratio may be the total number of analogue-to-digital converters in the time-interleaved analogue-to-digital converter, divided by the number of currently-functional analogue-to-digital converters in the time-interleaved analogue-to-digital converter. It will be understood that the number of currently-functional analogue-to-digital converters in the time-interleaved analogue-to-digital converter is calculated by subtracting the number of currently non-functional analogue-to-digital converters from the total number of analogue-to-digital converters in the time-interleaved analogue-to-digital converter.
There may be situations in which it is not possible to increase the sampling frequencies of the analogue-to-digital converters, as described above, for example if there is insufficient headroom available on the sampling rate to increase the sampling frequency (further). It is advantageous in such a situation if a further method is applied to (partially or fully) compensate for a non-functional analogue-to-digital converter, so that the overall time-interleaved analogue-to-digital converter may continue to function with reasonable accuracy.
Thus, in some examples, the analogue-to-digital converters of the time-interleaved analogue-to-digital converter, the first and second analogue-to-digital converters are arranged to sample the analogue input sequentially in a sampling sequence. The time-interleaved analogue-to-digital converter is configured for operation in a data-interpolation mode in the event that at least one of the analogue-to-digital converters is in a non-functional state. In the data-interpolation mode, the time-interleaved analogue-to-digital converter is arranged to estimate a value for a digital output associated with the at least one non-functional analogue-to-digital converter by interpolating based on values of the digital outputs of the analogue-to-digital converters arranged to sample before and after the at least one non-functional analogue-to-digital converter in the sampling sequence.
It will be understood that although the digital output of the non-functional analogue-to-digital converter is referred to, this does not refer to an output actually made from the non-functional analogue-to-digital converter (it may in practice not produce any output since it is non-functional), rather this refer to estimating what the digital output of that analogue-to-digital converter would have been at that sampling instance had it been functional.
Similarly, in some examples of the method, the time-interleaved analogue-to-digital converter comprises at least two analogue-to-digital converters arranged to sample an analogue input sequentially in a sampling sequence, and output a respective digital output based on the sampled analogue input; the method comprises, in a data-interpolation mode in which at least one of the analogue-to-digital converters is non-functional, estimating a value for a digital output associated with the at least one non-functional analogue-to-digital converter by interpolating based on values of the digital outputs of the analogue-to-digital converters arranged to sample before and after the at least one non-functional analogue-to-digital converter in the sampling sequence.
This technique also provides an advantageous way to compensate for missing data from a non-functional analogue-to-digital converter. It will be understood that compensating for missing data from a non-functional analogue-to-digital converter by interpolation may be used advantageously independently of the method described above in which sampling frequency of analogue-to-digital converters is increased. Thus, according to a second aspect of the present disclosure, there is provided a time-interleaved analogue-to-digital converter that includes: at least two analogue-to-digital converters, arranged to sample an analogue input sequentially in a sampling sequence, and output a respective digital output based on the sampled analogue input. The time-interleaved analogue-to-digital converter configured for operation in a data-interpolation mode when (i.e. in the event that) at least one of the analogue-to-digital converters is in a non-functional state. In the data-interpolation mode the time-interleaved analogue-to-digital converter is arranged to estimate a value for the digital output associated with the at least one non-functional analogue-to-digital converter by interpolating based on values of the digital outputs of the analogue-to-digital converters arranged to sample before and after the at least one non-functional analogue-to-digital converter in the sampling sequence.
Similarly, according to this disclosure, there is also provided a method of operating a time-interleaved analogue-to-digital converter, wherein the time-interleaved analogue-to-digital converter comprises at least two analogue-to-digital converters, arranged to sample an analogue input sequentially in a sampling sequence, and output a respective digital output based on the sampled analogue input. The method includes: in a data-interpolation mode in which at least one of the analogue-to-digital converters is non-functional, estimating a value for the digital output associated with the at least one non-functional analogue-to-digital converter by interpolating based on values of the digital outputs of the analogue-to-digital converters arranged to sample before and after the at least one non-functional analogue-to-digital converter in the sampling sequence.
It will be understood that features of the aspects described above may also be present in these aspects, and conversely the features described below may also be present in the aspects described above.
In some examples, each analogue-to-digital converter in the sampling sequence may be arranged to sample at the same sampling frequency. The time period between consecutive analogue-to-digital converters sampling in the sampling sequence may be the same for each pair of analogue-to-digital converters (i.e. all analogue-to-digital converters in the sampling sequence may sample at equally spaced times relative to each other). This simplifies the estimation of missing data from a non-functional analogue-to-digital converter.
It will be understood that the sampling sequence refers to an ordering in which the analogue-to-digital converters take samples (e.g. first, then second, then third) repeatedly. It may also refer to the specific timings with which the samples are taken. A particular section of the sampling sequence (i.e. one run-through), with each functional analogue-to-digital converter taking one sample, may be referred to as a sampling cycle.
Where it is stated that interpolation is based on values of the digital outputs of the analogue-to-digital converters that are arranged to sample before and after the at least one non-functional analogue-to-digital converter, it will be appreciated that these analogue-to-digital converters need not be arranged to sample immediately before and after the given non-functional analogue-to-digital converter in the sampling sequence, but rather that one appears somewhere before the particular non-functional analogue-to-digital converter in the sampling sequence and another appears after. However, preferably they come from the same sampling cycle (i.e. they are from the closest instance in time of that functional analogue-to-digital converter taking a sample).
In particular, the samples may not come from the immediately preceding or following analogue-to-digital converters in the sampling sequence, since there may be multiple analogue-to-digital converters adjacent to each other in the sampling sequence which are both or all non-functional.
In some examples, in the data-interpolation mode, the time-interleaved analogue-to-digital converter is arranged to estimate a value for the digital output associated with a non-functional analogue-to-digital converter of the at least one non-functional analogue-to-digital converter by interpolating based on values of the digital outputs of the analogue-to-digital converters arranged to sample immediately before the non-functional analogue-to-digital converter in the sampling sequence and immediately after the non-functional analogue-to-digital converter in the sampling sequence (i.e. the adjacent samples in the sampling sequence). This occurs only where a non-functional analogue-to-digital converter is isolated in the sampling sequence (i.e. not adjacent to one or more other non-functional analogue-to-digital converters).
For example, the sampling sequence may comprise the time-interleaved analogue-to-digital converter sampling in the order of a first analogue-to-digital converter, a second analogue-to-digital converter and a third analogue-to-digital converter (of the at least two analogue-to-digital converters). In the data-interpolation mode, in which the second analogue-to-digital converter may be non-functional, the time-interleaved analogue-to-digital converter may be arranged to estimate a value for the digital output associated with the second analogue-to-digital converter by interpolating based on values of the digital outputs of the first analogue-to-digital converter and the third analogue-to-digital converter.
In other examples, in the data-interpolation mode the time-interleaved analogue-to-digital converter is arranged to estimate a value for the digital output associated with the at least one non-functional analogue-to-digital converter by interpolating based on values of the digital outputs of the analogue-to-digital converter arranged to sample immediately before one of the non-functional analogue-to-digital converters and of the analogue-to-digital converter arranged to sample immediately after another one of the non-functional analogue-to-digital converter in the sampling sequence. Thus, where more than one non-functional analogue-to-digital converter are adjacent to each other in the sampling sequence, the data outputs from the last functional analogue-to-digital converter before the series of non-functional analogue-to-digital converters and the first functional analogue-to-digital converter after the series of non-functional analogue-to-digital converters are used to interpolate for the estimated digital output from each of the non-functional analogue-to-digital converters in the series.
In some examples, the sampling sequence comprises the time-interleaved analogue-to-digital converter sampling in the order of first analogue-to-digital converter, second analogue-to-digital converter, third analogue-to-digital converter and fourth analogue-to-digital converter. In the data-interpolation mode, in which the second and third analogue-to-digital converters may be non-functional, the time-interleaved analogue-to-digital converter may be arranged to estimate a value for the digital outputs associated, respectively, with the second and third analogue-to-digital converters by interpolating based on values of the digital outputs of the first analogue-to-digital converter and the fourth analogue-to-digital converter.
In some examples the value for the digital output associated with the at least one non-functional analogue-to-digital converter is estimated by linear interpolation. This provides a particularly simple method of estimating the missing data. Other types of (non-linear) interpolation may alternatively be used, depending on what is most suitable for estimating the analogue input.
In some examples, the analogue-to-digital converter arranged to sample before the at least one non-functional analogue-to-digital converter in the sampling sequence produces a first digital output, wherein the analogue-to-digital converter arranged to sample after the at least one non-functional analogue-to-digital converter in the sampling sequence produces a second digital output. In some examples, the value for the digital output associated with a first non-functional analogue-to-digital converter of the at least one non-functional analogue-to-digital converter is calculated by dividing the difference between the first digital output and the second digital output by the number of non-functional analogue-to-digital converters. For example, referring to the example above in which the second analogue-to-digital converter is non-functional, the time-interleaved analogue-to-digital converter may be arranged to estimate a value for the digital output associated with the second analogue-to-digital converter by dividing the difference between the first digital output and the second digital output by two.
It will be understood that here the number of non-functional analogue-to-digital converters refers to the number of non-functional analogue-to-digital converters in the sampling sequence that are between the analogue-to-digital converter that produces the first digital output and the analogue-to-digital converter that produces the second digital output (i.e. the number between those two particular analogue-to-digital converters in the sampling sequence-rather than the total number of non-functional analogue-to-digital converter within the time-interleaved analogue-to-digital converter at a given time).
It will be appreciated that where the time-interleaved analogue-to-digital converter (or components thereof) is described as being configured to carry out certain steps, the method may likewise comprise the corresponding step. Similarly, the device may be configured to carry out any of the method steps referred to above.
Certain preferred examples of this disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which:
In this example, each ADC 2a, 2b, 2c receives a corresponding individual timing signal 6a, 6b, 6c which dictates the sample timings (i.e. when and at what frequency) with which that ADC samples the analogue input 4. A first timing signal 6a is provided to the first ADC 2a, and likewise for the other two. These timing signals 6a, 6b, 6c, also referred to as sampling clocks, are shown in greater detail in
Each ADC 2a, 2b, 2c produces a respective digital output 8a, 8b, 8c based on the analogue input 4. These signals are interleaved by a signal interleaving portion 10, so as to reconstruct a digital output signal 14 which encodes the analogue input 4. In particular, the signals are interleaved by charting each digital output 8a, 8b, 8c, relative to its respective sample time, to give an overall digital output signal 14. In this example the signal interleaving portion 10 is located within a field programmable gate array (FPGA) or a digital signal processor (DSP) 12.
Example timing signals 6a, 6b, 6c, 6d during normal operation of the time-interleaved ADC are represented in
The sharp peaks or spikes 16 in each timing signal trigger the corresponding ADC 2a, 2b, 2c, 2d to sample the analogue input 4. Since these timing signals 6a, 6b, 6c trigger the associated ADC to sample the analogue input 4, they dictate, and therefore represent, the sample timings of each ADC (i.e. the frequency, period, and relative time offset of sampling). As can be seen, the timing signals 6a, 6b, 6c, 6d are staggered in time relative to each other, so that each ADC 2a, 2b, 2c, 2d is sampling the analogue signal 4 at a different time (i.e. non-simultaneously).
In this example, each timing signal 6a, 6b, 6c, 6d has the same frequency and therefore the same period 18 between samples for a particular ADC. Dashed lines representing this period relative to the first timing signal 6a are shown in
It can be seen that in one period 18 of the timing signal 6a, referred to as T, there is a single peak of the other three timing signals 6b, 6c, 6d, each offset from the other. Thus, each ADC 2a, 2b, 2c, 2d samples once per time period T, and each has a sampling frequency of f=1/T, meaning that it samples f times per second. Since in this example there are a total of four ADCs 2a, 2b, 2c, 2d the time-interleaved ADC 1 overall samples 4f times per second (or more generally samples at a frequency of N*f, where N is the number of ADCs within the time-interleaved ADC, and f is the frequency of the timing signal(s)).
In the event that one of the ADCs, for example the third ADC 2c, fails (i.e. becomes non-functional), this results in a decrease in sampling frequency of the time-interleaved ADC 1, and also means that, if no remedial action is taken, the samples are no longer being taken by the ADCs at regular, equally spaced intervals. This can give rise to problematic harmonics in the output signal. If a time-interleaved ADC is used in safety critical components of devices, for example aircraft, failure of one of the ADCs within the time-interleaved ADC may mean that the component which uses it must be brought offline and replaced with a back-up method. This may result in an aircraft journey having to be prematurely terminated.
The present disclosure provides methods of compensating for failure of one or more ADCs 2a, 2b, 2c, 2d within the time-interleaved ADC, and thereby preventing the overall time-interleaved ADC 1 from failing in at least some circumstances.
A first aspect of the present disclosure is demonstrated in
In the compensation mode, the frequency of the timing signals 6a′, 6b′, 6c′ of the remaining (non-failed) ADCs 2a, 2b, 2d is increased, so that the sample timings of each ADC 2a, 2b, 2d increase in frequency. This helps to compensate for the lower sampling frequency caused by the absence of any samples from the third ADC 2c.
In this example, the frequency of each of the compensated timing signals 6a′, 6b′, 6d′ has been increased such that the sample rate of the time-interleaved ADC 1 is restored to the same overall sample rate which it has during normal operation (as illustrated in
Thus, in this example, the frequency of each timing signal 6a′ has been increased by a factor of 4/3 so that overall the time-interleaved ADC 1 is still sampling 4 times per reference time period 18. The time period 19′ of each timing signal is now ¾ of the timing signal period 18 which is used during normal operation.
More generally, in at least some examples, the frequency of the timing signals 6a, 6b, 6c, 6d of all functional ADCs may be increased in compensation mode by an amount such that the overall time-interleaved ADC 1 samples at the same rate which it does during normal operation. In order to do this the sampling frequency of each (functional) ADC is increased from:
f Samples/second
By increasing the sampling frequency of each functional ADC within the time-interleaved ADC, each ADC need only increase its sampling frequency by a relatively small amount in order to partially, or even fully compensate, for the faulty ADC(s). This advantage can therefore be achieved even where there is relatively little headroom available on each of the ADCs to increase its sampling frequency.
There may be circumstances in which this method cannot be applied, or can no longer be used (e.g. where there is no headroom left to further increase the sampling frequency of the ADCs).
In this technique, sample data is collected from ADCs that immediately precede and immediately follow the faulty ADC (or ADCs) in the sampling sequence (i.e. the sampling order). In this example, the sampling sequence is the order first ADC 2a, second ADC 2b, third ADC 2c and then fourth ACD 2d (and so on in a repeating cycle). Considering again a scenario in which the third ADC 2c is faulty, the method uses a first sample 40b, collected from the second ADC 2b, and a second sample 40d, collected from the fourth ADC 2d. The method then interpolates from these two data points to construct a data point for the third ADC 2c, which is then included (i.e. in the time-position where the sample from the third ADC 2c should have been) in the digital output signal from the time-interleaved ADC so that the time-interleaved ADC 1 may continue to function largely as it did before the third ADC 2c failed.
In the illustrated example a linear interpolation is used, as explained further below. However, it will be appreciated that any suitable interpolation may be used, for example a polynomial interpolation. Where data is known about the input analogue signal 4, which sets an expectation that the signal will have a certain type of behaviour, this expected behaviour may be taken into account in selecting the type of interpolation to carry out and/or in estimating a value for the digital output of the non-functional ADC.
In this example, a linear function between the collected data points is assumed, as illustrated by the dashed line 42. In normal operation there is a first time period 44 between the second and third ADCs 2b, 2c taking samples, and there is then a second time period 46 between then the third ADC 2c collects its sample, and when the fourth ADC 2d collects its sample. In this example, the timing signals all have equally spaced peaks, therefore third ADC 2c would normally sample exactly halfway between the times at which the second and fourth ADCs 2b, 2d would take samples, and therefore the first time period 44 and the second time period 46 are equal.
The missing data point 48 is estimated in this example by first taking the difference between the value at the second sample 40d and the first sample 40b, and then dividing this amount by two. This calculated amount is then added to the value of the first sample 40b.
Generally, when linearly interpolating for a single missing data point, the following calculation may be used:
It will be appreciated by those skilled in the art that the disclosure has been illustrated by describing one or more specific aspects thereof, but is not limited to these aspects; many variations and modifications are possible, within the scope of the accompanying claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 24386005.3 | Jan 2024 | EP | regional |
