Patent Application
20100067564
The present invention relates in general to wireless communications and specifically to a method and apparatus for performing a multipath search.
The general problem addressed by this invention is how to identify the different multipath components in a received WCDMA signal. This function is typically handled by a block in the receiver called the Multipath Searcher.
The characteristics of a dynamic fading channel are that it will degrade the performance of a multipath searcher using long coherent integration times. Another problem resulting from the characteristics of quickly changing fading channels is that the results from the early portion of the search cannot be meaningfully compared to the results from the later portion of the search because the channel has changed significantly in the intervening time. It is assumed that the searcher correlators are not large enough to cover the required time span in one operation.
A conventional prior art multipath searcher searches the certain length of code space to find the energy peaks. This certain length of code space is called a multipath searching window. The searching window usually is several hundred chips long depending on the multipath profile. In order to achieve a desirable performance, an 8, 4, or 2 samples per chip resolution of the searcher is necessary. Additionally, a certain integration time is needed for every searcher point. This is dwell time D. Normally CDMA system chip rate is several MHz, for example, the chip rate for WCDMA is 3.84 MHz. Due to this high speed chip rate, it is impossible to process the data by means of software in real time. Usually, a bank of hardware correlators has to be used. If a multipath searcher has a 200 chip window and 4 sample per chip resolution, it will need 800 correlators. Usually, a pipeline method with a higher speed system clock is used to save hardware. The higher the clock rate, the more power is consumed by the system. In conventional approaches, correlators will be a large portion of the hardware resources required for the multipath searcher.
That is, the conventional approach employs a bank of correlators in the searcher and then runs the searcher over the certain code space (searching window). In order to locate all possible paths, it is necessary to consider the worst case. The longer the searching window is, the larger the bank of correlators. The control logic is very simple for this approach, but more hardware resources are needed. It is desirable to reduce hardware resource requirements and reduce power consumption.
The present invention describes a method and architecture for implementing a multipath searcher block in a CDMA receiver that uses a time multiplexed non-coherent correlation method to significantly reduce the hardware resources needed to conduct multipath searching. Reducing the overall amount of hardware required further reduces power consumption. The method and apparatus of the present invention can be used for any CDMA based technology.
The present invention solves two problems caused by time multiplexed correlator design. First, the present invention searcher locates all possible multipath energy peaks at the same time within a limited time period to avoid comparing results from a different time period. Second, a robust time multiplexed non-coherent correlation method has been used to overcome the performance degradation caused by time-varying changes in the wireless channel over the correlation period.
An apparatus for performing a multipath search including a plurality of time-multiplexed chip correlators, wherein each of the plurality of time-multiplexed chip correlators has a pipeline, and further wherein each of the plurality of time-multiplexed chip correlators has an accumulation time is described. A method is described for performing a multipath search including performing multipath search slot processing, determining if a current multipath searching slot is a last multipath searching slot, if the current multipath searching slot is not the last multipath searching slot, then repeating the performing step, if the current multipath searching slot is the last multipath searching slot, then initializing a multipath searching slot index, determining if an integration has been completed if the integration has not been completed then repeating all steps and if the integration has been completed, then search results are sorted to locate energy peaks corresponding to multipath locations.
The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. The drawings include the following figures briefly described below where like-numbers on the figures represent similar elements:
The present invention reuses a small bank of correlators to perform a multipath search within a multipath searching window in a time-multiplexed scheme. First, the results of the correlation are accumulated non-coherently. This overcomes a harsh wireless environment. A reasonable time for correlation is used, e.g., 256 chips for WCDMA case. Second, if the multipath searching window is N chips and the resolution is M samples per chip, then total searching size will be N*M points. If the system clock allows a P stage pipeline, then the total number of correlators needed are (N*M)/P. For example, N=256, M=4 and P=8, it will employ 128 correlators to perform the multipath searching. In the present invention, if 4 correlators are used (and re-used) instead of 128, hardware usage will be reduced. In general, Y correlators will be used instead of (N*M)/P. The necessary condition is that N*M/P is an integer multiple of Y. Thus, the hardware resource savings is (N*M)/P/Y. Third, the multipath searching method is very generic. Y correlators will cover Y*M/P chips. The bank of correlators for (Y*M)/P chips will be used one by one for all N chips in the multipath searching window. After one pass, a non-coherent accumulation method is used to repeat the procedure until the multipath searcher dwell time is met.
Y needs to be chosen so that the channel is quasi-static over the time required to complete the multipath search. For a typical situation, 256 chip window (N) with 4 samples per chip (M) and clocking at 8 times the sample rate (P stage pipeline) would mean that typically 128 correlators would be required. Y is a divisor of 128. That is, (N*M)/P is an integer multiple of Y. It is likely that Y will be 16 or 32, allowing a hardware savings factor of 8 or 4, and requiring the channel be quasi-static over 8 or 4 slots. The slot time is about 667 microseconds, consequently, the channel dynamics should be quasi-static over between 2.7 to 5.3 milliseconds. The non-coherent accumulation method reduces the sensitivity to channel changes. The selection of Y is optimized through simulation. Y is a design parameter and is thus, selected permanently—in an IC design, once Y is set, it is not changed.
The pipeline is pre-determined based on the system clock rate. The accumulation time, the searching resolution and the dwell time are programmable.
In the
The multipath searcher architecture block diagram of the present invention is shown in
It is to be understood that the present invention may be implemented in various forms of hardware, software, firmware, special purpose processors, or a combination thereof, for example, within a mobile terminal, access point, or a cellular network. Preferably, the present invention is implemented as a combination of hardware and software. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage device. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units (CPU), a random access memory (RAM), and input/output (I/O) interface(s). The computer platform also includes an operating system and microinstruction code. The various processes and functions described herein may either be part of the microinstruction code or part of the application program (or a combination thereof), which is executed via the operating system. In addition, various other peripheral devices may be connected to the computer platform such as an additional data storage device and a printing device.
It is to be further understood that, because some of the constituent system components and method steps depicted in the accompanying figures are preferably implemented in software, the actual connections between the system components (or the process steps) may differ depending upon the manner in which the present invention is programmed. Given the teachings herein, one of ordinary skill in the related art will be able to contemplate these and similar implementations or configurations of the present invention.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US2005/027698 | 8/5/2005 | WO | 00 | 2/4/2008 |
